1; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=UNPACKED %s
2; RUN: llc < %s -march=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED %s
3; RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED %s
4
5; GCN-LABEL: {{^}}tbuffer_load_d16_x:
6; GCN: v_mov_b32_e32 [[ZEROREG:v[0-9]+]], 0
7; GCN: tbuffer_load_format_d16_x v{{[0-9]+}}, [[ZEROREG]], s[{{[0-9]+:[0-9]+}}],  dfmt:6,  nfmt:1, 0 idxen
8define amdgpu_ps half @tbuffer_load_d16_x(<4 x i32> inreg %rsrc) {
9main_body:
10  %data = call half @llvm.amdgcn.struct.tbuffer.load.f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 22, i32 0)
11  ret half %data
12}
13
14; GCN-LABEL: {{^}}tbuffer_load_d16_xy:
15; GCN: v_mov_b32_e32 [[ZEROREG:v[0-9]+]], 0
16; UNPACKED: tbuffer_load_format_d16_xy v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, [[ZEROREG]], s[{{[0-9]+:[0-9]+}}],  dfmt:6,  nfmt:1, 0 idxen
17; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
18
19; PACKED: tbuffer_load_format_d16_xy v[[FULL:[0-9]+]], [[ZEROREG]], s[{{[0-9]+:[0-9]+}}],  dfmt:6,  nfmt:1, 0 idxen
20; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[FULL]]
21define amdgpu_ps half @tbuffer_load_d16_xy(<4 x i32> inreg %rsrc) {
22main_body:
23  %data = call <2 x half> @llvm.amdgcn.struct.tbuffer.load.v2f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 22, i32 0)
24  %elt = extractelement <2 x half> %data, i32 1
25  ret half %elt
26}
27
28; GCN-LABEL: {{^}}tbuffer_load_d16_xyzw:
29; GCN: v_mov_b32_e32 [[ZEROREG:v[0-9]+]], 0
30; UNPACKED: tbuffer_load_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, [[ZEROREG]], s[{{[0-9]+:[0-9]+}}],  dfmt:6,  nfmt:1, 0 idxen
31; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
32
33; PACKED: tbuffer_load_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, [[ZEROREG]], s[{{[0-9]+:[0-9]+}}],  dfmt:6,  nfmt:1, 0 idxen
34; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[HI]]
35define amdgpu_ps half @tbuffer_load_d16_xyzw(<4 x i32> inreg %rsrc) {
36main_body:
37  %data = call <4 x half> @llvm.amdgcn.struct.tbuffer.load.v4f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 22, i32 0)
38  %elt = extractelement <4 x half> %data, i32 3
39  ret half %elt
40}
41
42declare half @llvm.amdgcn.struct.tbuffer.load.f16(<4 x i32>, i32, i32, i32, i32, i32)
43declare <2 x half> @llvm.amdgcn.struct.tbuffer.load.v2f16(<4 x i32>, i32, i32, i32, i32, i32)
44declare <4 x half> @llvm.amdgcn.struct.tbuffer.load.v4f16(<4 x i32>, i32, i32, i32, i32, i32)
45
46