1;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=SICI 2;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=VI 3 4;CHECK-LABEL: {{^}}buffer_load: 5;CHECK: buffer_load_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen 6;CHECK: buffer_load_dwordx4 v[4:7], {{v[0-9]+}}, s[0:3], 0 idxen glc 7;CHECK: buffer_load_dwordx4 v[8:11], {{v[0-9]+}}, s[0:3], 0 idxen slc 8define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) { 9main_body: 10 %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 0) 11 %data_glc = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 1) 12 %data_slc = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 2) 13 %r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0 14 %r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1 15 %r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2 16 ret {<4 x float>, <4 x float>, <4 x float>} %r2 17} 18 19;CHECK-LABEL: {{^}}buffer_load_immoffs: 20;CHECK: buffer_load_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen offset:40 21define amdgpu_ps <4 x float> @buffer_load_immoffs(<4 x i32> inreg) { 22main_body: 23 %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 40, i32 0, i32 0) 24 ret <4 x float> %data 25} 26 27;CHECK-LABEL: {{^}}buffer_load_immoffs_large: 28;CHECK: s_movk_i32 [[OFFSET:s[0-9]+]], 0x1ffc 29;CHECK: buffer_load_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], [[OFFSET]] idxen offset:4 30define amdgpu_ps <4 x float> @buffer_load_immoffs_large(<4 x i32> inreg) { 31main_body: 32 %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 4, i32 8188, i32 0) 33 ret <4 x float> %data 34} 35 36;CHECK-LABEL: {{^}}buffer_load_idx: 37;CHECK: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 idxen 38define amdgpu_ps <4 x float> @buffer_load_idx(<4 x i32> inreg, i32) { 39main_body: 40 %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 %1, i32 0, i32 0, i32 0) 41 ret <4 x float> %data 42} 43 44;CHECK-LABEL: {{^}}buffer_load_ofs: 45;CHECK: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 idxen offen 46define amdgpu_ps <4 x float> @buffer_load_ofs(<4 x i32> inreg, i32) { 47main_body: 48 %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 %1, i32 0, i32 0) 49 ret <4 x float> %data 50} 51 52;CHECK-LABEL: {{^}}buffer_load_ofs_imm: 53;CHECK: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 idxen offen offset:60 54define amdgpu_ps <4 x float> @buffer_load_ofs_imm(<4 x i32> inreg, i32) { 55main_body: 56 %ofs = add i32 %1, 60 57 %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 %ofs, i32 0, i32 0) 58 ret <4 x float> %data 59} 60 61;CHECK-LABEL: {{^}}buffer_load_both: 62;CHECK: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 idxen offen 63define amdgpu_ps <4 x float> @buffer_load_both(<4 x i32> inreg, i32, i32) { 64main_body: 65 %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 %1, i32 %2, i32 0, i32 0) 66 ret <4 x float> %data 67} 68 69;CHECK-LABEL: {{^}}buffer_load_both_reversed: 70;CHECK: v_mov_b32_e32 v2, v0 71;CHECK: buffer_load_dwordx4 v[0:3], v[1:2], s[0:3], 0 idxen offen 72define amdgpu_ps <4 x float> @buffer_load_both_reversed(<4 x i32> inreg, i32, i32) { 73main_body: 74 %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 %2, i32 %1, i32 0, i32 0) 75 ret <4 x float> %data 76} 77 78;CHECK-LABEL: {{^}}buffer_load_x1: 79;CHECK: buffer_load_dword v0, v[0:1], s[0:3], 0 idxen offen 80define amdgpu_ps float @buffer_load_x1(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) { 81main_body: 82 %data = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 0, i32 0) 83 ret float %data 84} 85 86;CHECK-LABEL: {{^}}buffer_load_x2: 87;CHECK: buffer_load_dwordx2 v[0:1], v[0:1], s[0:3], 0 idxen offen 88define amdgpu_ps <2 x float> @buffer_load_x2(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) { 89main_body: 90 %data = call <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 0, i32 0) 91 ret <2 x float> %data 92} 93 94;CHECK-LABEL: {{^}}buffer_load_negative_offset: 95;CHECK: v_add_{{[iu]}}32_e32 {{v[0-9]+}}, vcc, -16, v0 96;CHECK: buffer_load_dwordx4 v[0:3], {{v\[[0-9]+:[0-9]+\]}}, s[0:3], 0 idxen offen 97define amdgpu_ps <4 x float> @buffer_load_negative_offset(<4 x i32> inreg, i32 %ofs) { 98main_body: 99 %ofs.1 = add i32 %ofs, -16 100 %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 %ofs.1, i32 0, i32 0) 101 ret <4 x float> %data 102} 103 104; SI won't merge ds memory operations, because of the signed offset bug, so 105; we only have check lines for VI. 106; CHECK-LABEL: buffer_load_mmo: 107; VI: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0 108; VI: ds_write2_b32 v{{[0-9]+}}, [[ZERO]], [[ZERO]] offset1:4 109define amdgpu_ps float @buffer_load_mmo(<4 x i32> inreg %rsrc, float addrspace(3)* %lds) { 110entry: 111 store float 0.0, float addrspace(3)* %lds 112 %val = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0) 113 %tmp2 = getelementptr float, float addrspace(3)* %lds, i32 4 114 store float 0.0, float addrspace(3)* %tmp2 115 ret float %val 116} 117 118;CHECK-LABEL: {{^}}buffer_load_int: 119;CHECK: buffer_load_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen 120;CHECK: buffer_load_dwordx2 v[4:5], {{v[0-9]+}}, s[0:3], 0 idxen glc 121;CHECK: buffer_load_dword v6, {{v[0-9]+}}, s[0:3], 0 idxen slc 122define amdgpu_ps {<4 x float>, <2 x float>, float} @buffer_load_int(<4 x i32> inreg) { 123main_body: 124 %data = call <4 x i32> @llvm.amdgcn.struct.buffer.load.v4i32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 0) 125 %data_glc = call <2 x i32> @llvm.amdgcn.struct.buffer.load.v2i32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 1) 126 %data_slc = call i32 @llvm.amdgcn.struct.buffer.load.i32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 2) 127 %fdata = bitcast <4 x i32> %data to <4 x float> 128 %fdata_glc = bitcast <2 x i32> %data_glc to <2 x float> 129 %fdata_slc = bitcast i32 %data_slc to float 130 %r0 = insertvalue {<4 x float>, <2 x float>, float} undef, <4 x float> %fdata, 0 131 %r1 = insertvalue {<4 x float>, <2 x float>, float} %r0, <2 x float> %fdata_glc, 1 132 %r2 = insertvalue {<4 x float>, <2 x float>, float} %r1, float %fdata_slc, 2 133 ret {<4 x float>, <2 x float>, float} %r2 134} 135 136;CHECK-LABEL: {{^}}struct_buffer_load_ubyte: 137;CHECK-NEXT: %bb. 138;CHECK-NEXT: buffer_load_ubyte v{{[0-9]}}, v[0:1], s[0:3], 0 idxen offen 139;CHECK: s_waitcnt vmcnt(0) 140;CHECK-NEXT: v_cvt_f32_ubyte0_e32 v0, v0 141;CHECK-NEXT: ; return to shader part epilog 142define amdgpu_ps float @struct_buffer_load_ubyte(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) { 143main_body: 144 %tmp = call i8 @llvm.amdgcn.struct.buffer.load.i8(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 0, i32 0) 145 %tmp2 = zext i8 %tmp to i32 146 %val = uitofp i32 %tmp2 to float 147 ret float %val 148} 149 150;CHECK-LABEL: {{^}}struct_buffer_load_ushort: 151;CHECK-NEXT: %bb. 152;CHECK-NEXT: buffer_load_ushort v{{[0-9]}}, v[0:1], s[0:3], 0 idxen offen 153;CHECK-NEXT: s_waitcnt vmcnt(0) 154;CHECK-NEXT: v_cvt_f32_u32_e32 v0, v0 155;CHECK-NEXT: ; return to shader part epilog 156define amdgpu_ps float @struct_buffer_load_ushort(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) { 157main_body: 158 %tmp = call i16 @llvm.amdgcn.struct.buffer.load.i16(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 0, i32 0) 159 %tmp2 = zext i16 %tmp to i32 160 %val = uitofp i32 %tmp2 to float 161 ret float %val 162} 163 164;CHECK-LABEL: {{^}}struct_buffer_load_sbyte: 165;CHECK-NEXT: %bb. 166;CHECK-NEXT: buffer_load_sbyte v{{[0-9]}}, v[0:1], s[0:3], 0 idxen offen 167;CHECK-NEXT: s_waitcnt vmcnt(0) 168;CHECK-NEXT: v_cvt_f32_i32_e32 v0, v0 169;CHECK-NEXT: ; return to shader part epilog 170define amdgpu_ps float @struct_buffer_load_sbyte(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) { 171main_body: 172 %tmp = call i8 @llvm.amdgcn.struct.buffer.load.i8(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 0, i32 0) 173 %tmp2 = sext i8 %tmp to i32 174 %val = sitofp i32 %tmp2 to float 175 ret float %val 176} 177 178;CHECK-LABEL: {{^}}struct_buffer_load_sshort: 179;CHECK-NEXT: %bb. 180;CHECK-NEXT: buffer_load_sshort v{{[0-9]}}, v[0:1], s[0:3], 0 idxen offen 181;CHECK-NEXT: s_waitcnt vmcnt(0) 182;CHECK-NEXT: v_cvt_f32_i32_e32 v0, v0 183;CHECK-NEXT: ; return to shader part epilog 184define amdgpu_ps float @struct_buffer_load_sshort(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) { 185main_body: 186 %tmp = call i16 @llvm.amdgcn.struct.buffer.load.i16(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 0, i32 0) 187 %tmp2 = sext i16 %tmp to i32 188 %val = sitofp i32 %tmp2 to float 189 ret float %val 190} 191 192;CHECK-LABEL: {{^}}struct_buffer_load_f16: 193;CHECK-NEXT: %bb. 194;CHECK-NEXT: buffer_load_ushort [[VAL:v[0-9]+]], v1, s[0:3], 0 idxen 195;CHECK: s_waitcnt vmcnt(0) 196;CHECK: ds_write_b16 v0, [[VAL]] 197define amdgpu_ps void @struct_buffer_load_f16(<4 x i32> inreg %rsrc, half addrspace(3)* %ptr, i32 %idx) { 198main_body: 199 %val = call half @llvm.amdgcn.struct.buffer.load.f16(<4 x i32> %rsrc, i32 %idx, i32 0, i32 0, i32 0) 200 store half %val, half addrspace(3)* %ptr 201 ret void 202} 203 204;CHECK-LABEL: {{^}}struct_buffer_load_v2f16: 205;CHECK-NEXT: %bb. 206;CHECK-NEXT: buffer_load_dword [[VAL:v[0-9]+]], v1, s[0:3], 0 idxen 207;CHECK: s_waitcnt vmcnt(0) 208;CHECK: ds_write_b32 v0, [[VAL]] 209define amdgpu_ps void @struct_buffer_load_v2f16(<4 x i32> inreg %rsrc, <2 x half> addrspace(3)* %ptr, i32 %idx) { 210main_body: 211 %val = call <2 x half> @llvm.amdgcn.struct.buffer.load.v2f16(<4 x i32> %rsrc, i32 %idx, i32 0, i32 0, i32 0) 212 store <2 x half> %val, <2 x half> addrspace(3)* %ptr 213 ret void 214} 215 216;CHECK-LABEL: {{^}}struct_buffer_load_v4f16: 217;CHECK-NEXT: %bb. 218;CHECK-NEXT: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]], v1, s[0:3], 0 idxen 219;CHECK: s_waitcnt vmcnt(0) 220;CHECK: ds_write_b64 v0, [[VAL]] 221define amdgpu_ps void @struct_buffer_load_v4f16(<4 x i32> inreg %rsrc, <4 x half> addrspace(3)* %ptr, i32 %idx) { 222main_body: 223 %val = call <4 x half> @llvm.amdgcn.struct.buffer.load.v4f16(<4 x i32> %rsrc, i32 %idx, i32 0, i32 0, i32 0) 224 store <4 x half> %val, <4 x half> addrspace(3)* %ptr 225 ret void 226} 227 228;CHECK-LABEL: {{^}}struct_buffer_load_i16: 229;CHECK-NEXT: %bb. 230;CHECK-NEXT: buffer_load_ushort [[VAL:v[0-9]+]], v1, s[0:3], 0 idxen 231;CHECK: s_waitcnt vmcnt(0) 232;CHECK: ds_write_b16 v0, [[VAL]] 233define amdgpu_ps void @struct_buffer_load_i16(<4 x i32> inreg %rsrc, i16 addrspace(3)* %ptr, i32 %idx) { 234main_body: 235 %val = call i16 @llvm.amdgcn.struct.buffer.load.i16(<4 x i32> %rsrc, i32 %idx, i32 0, i32 0, i32 0) 236 store i16 %val, i16 addrspace(3)* %ptr 237 ret void 238} 239 240;CHECK-LABEL: {{^}}struct_buffer_load_v2i16: 241;CHECK-NEXT: %bb. 242;CHECK-NEXT: buffer_load_dword [[VAL:v[0-9]+]], v1, s[0:3], 0 idxen 243;CHECK: s_waitcnt vmcnt(0) 244;CHECK: ds_write_b32 v0, [[VAL]] 245define amdgpu_ps void @struct_buffer_load_v2i16(<4 x i32> inreg %rsrc, <2 x i16> addrspace(3)* %ptr, i32 %idx) { 246main_body: 247 %val = call <2 x i16> @llvm.amdgcn.struct.buffer.load.v2i16(<4 x i32> %rsrc, i32 %idx, i32 0, i32 0, i32 0) 248 store <2 x i16> %val, <2 x i16> addrspace(3)* %ptr 249 ret void 250} 251 252;CHECK-LABEL: {{^}}struct_buffer_load_v4i16: 253;CHECK-NEXT: %bb. 254;CHECK-NEXT: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]], v1, s[0:3], 0 idxen 255;CHECK: s_waitcnt vmcnt(0) 256;CHECK: ds_write_b64 v0, [[VAL]] 257define amdgpu_ps void @struct_buffer_load_v4i16(<4 x i32> inreg %rsrc, <4 x i16> addrspace(3)* %ptr, i32 %idx) { 258main_body: 259 %val = call <4 x i16> @llvm.amdgcn.struct.buffer.load.v4i16(<4 x i32> %rsrc, i32 %idx, i32 0, i32 0, i32 0) 260 store <4 x i16> %val, <4 x i16> addrspace(3)* %ptr 261 ret void 262} 263 264declare float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32>, i32, i32, i32, i32) #0 265declare <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32>, i32, i32, i32, i32) #0 266declare <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32>, i32, i32, i32, i32) #0 267declare i32 @llvm.amdgcn.struct.buffer.load.i32(<4 x i32>, i32, i32, i32, i32) #0 268declare <2 x i32> @llvm.amdgcn.struct.buffer.load.v2i32(<4 x i32>, i32, i32, i32, i32) #0 269declare <4 x i32> @llvm.amdgcn.struct.buffer.load.v4i32(<4 x i32>, i32, i32, i32, i32) #0 270declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0 271declare i8 @llvm.amdgcn.struct.buffer.load.i8(<4 x i32>, i32, i32, i32, i32) #0 272 273declare half @llvm.amdgcn.struct.buffer.load.f16(<4 x i32>, i32, i32, i32, i32) #0 274declare <2 x half> @llvm.amdgcn.struct.buffer.load.v2f16(<4 x i32>, i32, i32, i32, i32) #0 275declare <4 x half> @llvm.amdgcn.struct.buffer.load.v4f16(<4 x i32>, i32, i32, i32, i32) #0 276 277declare i16 @llvm.amdgcn.struct.buffer.load.i16(<4 x i32>, i32, i32, i32, i32) #0 278declare <2 x i16> @llvm.amdgcn.struct.buffer.load.v2i16(<4 x i32>, i32, i32, i32, i32) #0 279declare <4 x i16> @llvm.amdgcn.struct.buffer.load.v4i16(<4 x i32>, i32, i32, i32, i32) #0 280 281attributes #0 = { nounwind readonly } 282