1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mcpu=gfx1010 -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s 3; RUN: llc -mcpu=gfx900 -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 %s 4; RUN: llc -mcpu=gfx810 -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8 %s 5@esgs_ring = external addrspace(3) global [0 x i32], align 65536 6 7define amdgpu_gs void @main(<4 x i32> %arg, i32 %arg1) { 8; GFX10-LABEL: main: 9; GFX10: ; %bb.0: ; %bb 10; GFX10-NEXT: s_mov_b32 s1, exec_lo 11; GFX10-NEXT: BB0_1: ; =>This Inner Loop Header: Depth=1 12; GFX10-NEXT: v_readfirstlane_b32 s4, v0 13; GFX10-NEXT: v_readfirstlane_b32 s5, v1 14; GFX10-NEXT: v_readfirstlane_b32 s6, v2 15; GFX10-NEXT: v_readfirstlane_b32 s7, v3 16; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1] 17; GFX10-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3] 18; GFX10-NEXT: s_and_b32 s0, vcc_lo, s0 19; GFX10-NEXT: s_and_saveexec_b32 s0, s0 20; GFX10-NEXT: buffer_load_format_d16_xyz v[5:6], v4, s[4:7], 0 idxen 21; GFX10-NEXT: s_waitcnt_depctr 0xffe3 22; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s0 23; GFX10-NEXT: s_cbranch_execnz BB0_1 24; GFX10-NEXT: ; %bb.2: 25; GFX10-NEXT: s_mov_b32 exec_lo, s1 26; GFX10-NEXT: s_waitcnt vmcnt(0) 27; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v5 28; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v6 29; GFX10-NEXT: v_mov_b32_e32 v2, 0 30; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 31; GFX10-NEXT: ds_write2_b32 v2, v0, v1 offset0:7 offset1:8 32; 33; GFX9-LABEL: main: 34; GFX9: ; %bb.0: ; %bb 35; GFX9-NEXT: s_mov_b64 s[2:3], exec 36; GFX9-NEXT: BB0_1: ; =>This Inner Loop Header: Depth=1 37; GFX9-NEXT: v_readfirstlane_b32 s4, v0 38; GFX9-NEXT: v_readfirstlane_b32 s5, v1 39; GFX9-NEXT: v_readfirstlane_b32 s6, v2 40; GFX9-NEXT: v_readfirstlane_b32 s7, v3 41; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, s[4:5], v[0:1] 42; GFX9-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], v[2:3] 43; GFX9-NEXT: s_and_b64 s[0:1], vcc, s[0:1] 44; GFX9-NEXT: s_and_saveexec_b64 s[0:1], s[0:1] 45; GFX9-NEXT: s_nop 0 46; GFX9-NEXT: buffer_load_format_d16_xyz v[5:6], v4, s[4:7], 0 idxen 47; GFX9-NEXT: s_xor_b64 exec, exec, s[0:1] 48; GFX9-NEXT: s_cbranch_execnz BB0_1 49; GFX9-NEXT: ; %bb.2: 50; GFX9-NEXT: s_mov_b64 exec, s[2:3] 51; GFX9-NEXT: s_waitcnt vmcnt(0) 52; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v5 53; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v6 54; GFX9-NEXT: v_mov_b32_e32 v2, 0 55; GFX9-NEXT: ds_write2_b32 v2, v0, v1 offset0:7 offset1:8 56; 57; GFX8-LABEL: main: 58; GFX8: ; %bb.0: ; %bb 59; GFX8-NEXT: s_mov_b64 s[2:3], exec 60; GFX8-NEXT: BB0_1: ; =>This Inner Loop Header: Depth=1 61; GFX8-NEXT: v_readfirstlane_b32 s4, v0 62; GFX8-NEXT: v_readfirstlane_b32 s5, v1 63; GFX8-NEXT: v_readfirstlane_b32 s6, v2 64; GFX8-NEXT: v_readfirstlane_b32 s7, v3 65; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, s[4:5], v[0:1] 66; GFX8-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], v[2:3] 67; GFX8-NEXT: s_and_b64 s[0:1], vcc, s[0:1] 68; GFX8-NEXT: s_and_saveexec_b64 s[0:1], s[0:1] 69; GFX8-NEXT: s_nop 0 70; GFX8-NEXT: buffer_load_format_d16_xyz v[5:6], v4, s[4:7], 0 idxen 71; GFX8-NEXT: s_xor_b64 exec, exec, s[0:1] 72; GFX8-NEXT: s_cbranch_execnz BB0_1 73; GFX8-NEXT: ; %bb.2: 74; GFX8-NEXT: s_mov_b64 exec, s[2:3] 75; GFX8-NEXT: s_waitcnt vmcnt(0) 76; GFX8-NEXT: v_alignbit_b32 v0, v6, v5, 16 77; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v0 78; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0 79; GFX8-NEXT: v_mov_b32_e32 v2, 0 80; GFX8-NEXT: s_mov_b32 m0, -1 81; GFX8-NEXT: ds_write2_b32 v2, v0, v1 offset0:7 offset1:8 82bb: 83 %i = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 undef) 84 %i2 = call nsz arcp <3 x half> @llvm.amdgcn.struct.buffer.load.format.v3f16(<4 x i32> %arg, i32 %arg1, i32 0, i32 0, i32 0) 85 %i3 = bitcast <3 x half> %i2 to <3 x i16> 86 %i4 = extractelement <3 x i16> %i3, i32 1 87 %i5 = bitcast <3 x half> %i2 to <3 x i16> 88 %i6 = extractelement <3 x i16> %i5, i32 2 89 %i7 = zext i16 %i4 to i32 90 %i8 = zext i16 %i6 to i32 91 %i9 = add nuw nsw i32 0, 7 92 %i10 = getelementptr [0 x i32], [0 x i32] addrspace(3)* @esgs_ring, i32 0, i32 %i9 93 store i32 %i7, i32 addrspace(3)* %i10, align 4 94 %i11 = add nuw nsw i32 0, 8 95 %i12 = getelementptr [0 x i32], [0 x i32] addrspace(3)* @esgs_ring, i32 0, i32 %i11 96 store i32 %i8, i32 addrspace(3)* %i12, align 4 97 unreachable 98} 99 100; Function Attrs: nounwind readnone willreturn 101declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #0 102 103; Function Attrs: nounwind readonly willreturn 104declare <3 x half> @llvm.amdgcn.struct.buffer.load.format.v3f16(<4 x i32>, i32, i32, i32, i32 immarg) #1 105 106attributes #0 = { nounwind readnone willreturn } 107attributes #1 = { nounwind readonly willreturn } 108