1;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=SICI
2;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=VI
3
4;CHECK-LABEL: {{^}}buffer_load:
5;CHECK: buffer_load_format_xyzw v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen
6;CHECK: buffer_load_format_xyzw v[4:7], {{v[0-9]+}}, s[0:3], 0 idxen glc
7;CHECK: buffer_load_format_xyzw v[8:11], {{v[0-9]+}}, s[0:3], 0 idxen slc
8define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) {
9main_body:
10  %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 0)
11  %data_glc = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 1)
12  %data_slc = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 2)
13  %r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0
14  %r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1
15  %r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2
16  ret {<4 x float>, <4 x float>, <4 x float>} %r2
17}
18
19;CHECK-LABEL: {{^}}buffer_load_immoffs:
20;CHECK: buffer_load_format_xyzw v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen offset:42
21define amdgpu_ps <4 x float> @buffer_load_immoffs(<4 x i32> inreg) {
22main_body:
23  %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 42, i32 0, i32 0)
24  ret <4 x float> %data
25}
26
27;CHECK-LABEL: {{^}}buffer_load_immoffs_large:
28;CHECK-DAG: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, s[0:3], 60 idxen offset:4092
29;CHECK-DAG: s_movk_i32 [[OFS1:s[0-9]+]], 0x7ffc
30;CHECK-DAG: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, s[0:3], [[OFS1]] idxen offset:4092
31;CHECK-DAG: s_mov_b32 [[OFS2:s[0-9]+]], 0x8ffc
32;CHECK-DAG: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, s[0:3], [[OFS2]] idxen offset:4
33define amdgpu_ps <4 x float> @buffer_load_immoffs_large(<4 x i32> inreg) {
34main_body:
35  %d.0 = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 4092, i32 60, i32 0)
36  %d.1 = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 4092, i32 32764, i32 0)
37  %d.2 = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 4, i32 36860, i32 0)
38  %d.3 = fadd <4 x float> %d.0, %d.1
39  %data = fadd <4 x float> %d.2, %d.3
40  ret <4 x float> %data
41}
42
43;CHECK-LABEL: {{^}}buffer_load_idx:
44;CHECK: buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 idxen
45define amdgpu_ps <4 x float> @buffer_load_idx(<4 x i32> inreg, i32) {
46main_body:
47  %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %0, i32 %1, i32 0, i32 0, i32 0)
48  ret <4 x float> %data
49}
50
51;CHECK-LABEL: {{^}}buffer_load_ofs:
52;CHECK: buffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 idxen offen
53define amdgpu_ps <4 x float> @buffer_load_ofs(<4 x i32> inreg, i32) {
54main_body:
55  %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 %1, i32 0, i32 0)
56  ret <4 x float> %data
57}
58
59;CHECK-LABEL: {{^}}buffer_load_ofs_imm:
60;CHECK: buffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 idxen offen offset:60
61define amdgpu_ps <4 x float> @buffer_load_ofs_imm(<4 x i32> inreg, i32) {
62main_body:
63  %ofs = add i32 %1, 60
64  %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 %ofs, i32 0, i32 0)
65  ret <4 x float> %data
66}
67
68;CHECK-LABEL: {{^}}buffer_load_both:
69;CHECK: buffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 idxen offen
70define amdgpu_ps <4 x float> @buffer_load_both(<4 x i32> inreg, i32, i32) {
71main_body:
72  %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %0, i32 %1, i32 %2, i32 0, i32 0)
73  ret <4 x float> %data
74}
75
76;CHECK-LABEL: {{^}}buffer_load_both_reversed:
77;CHECK: v_mov_b32_e32 v2, v0
78;CHECK: buffer_load_format_xyzw v[0:3], v[1:2], s[0:3], 0 idxen offen
79define amdgpu_ps <4 x float> @buffer_load_both_reversed(<4 x i32> inreg, i32, i32) {
80main_body:
81  %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %0, i32 %2, i32 %1, i32 0, i32 0)
82  ret <4 x float> %data
83}
84
85;CHECK-LABEL: {{^}}buffer_load_x:
86;CHECK: buffer_load_format_x v0, {{v[0-9]+}}, s[0:3], 0 idxen
87define amdgpu_ps float @buffer_load_x(<4 x i32> inreg %rsrc) {
88main_body:
89  %data = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)
90  ret float %data
91}
92
93;CHECK-LABEL: {{^}}buffer_load_x_i32:
94;CHECK: buffer_load_format_x v0, {{v[0-9]+}}, s[0:3], 0 idxen
95define amdgpu_ps float @buffer_load_x_i32(<4 x i32> inreg %rsrc) {
96main_body:
97  %data = call i32 @llvm.amdgcn.struct.buffer.load.format.i32(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)
98  %fdata = bitcast i32 %data to float
99  ret float %fdata
100}
101
102;CHECK-LABEL: {{^}}buffer_load_xy:
103;CHECK: buffer_load_format_xy v[0:1], {{v[0-9]+}}, s[0:3], 0 idxen
104define amdgpu_ps <2 x float> @buffer_load_xy(<4 x i32> inreg %rsrc) {
105main_body:
106  %data = call <2 x float> @llvm.amdgcn.struct.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)
107  ret <2 x float> %data
108}
109
110declare float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32>, i32, i32, i32, i32) #0
111declare <2 x float> @llvm.amdgcn.struct.buffer.load.format.v2f32(<4 x i32>, i32, i32, i32, i32) #0
112declare <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32>, i32, i32, i32, i32) #0
113declare i32 @llvm.amdgcn.struct.buffer.load.format.i32(<4 x i32>, i32, i32, i32, i32) #0
114
115attributes #0 = { nounwind readonly }
116