1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3
4define amdgpu_kernel void @set_inactive(i32 addrspace(1)* %out, i32 %in) {
5; GCN-LABEL: set_inactive:
6; GCN:       ; %bb.0:
7; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
8; GCN-NEXT:    s_load_dword s0, s[0:1], 0x2c
9; GCN-NEXT:    s_mov_b32 s7, 0xf000
10; GCN-NEXT:    s_mov_b32 s6, -1
11; GCN-NEXT:    s_waitcnt lgkmcnt(0)
12; GCN-NEXT:    v_mov_b32_e32 v0, s0
13; GCN-NEXT:    s_not_b64 exec, exec
14; GCN-NEXT:    v_mov_b32_e32 v0, 42
15; GCN-NEXT:    s_not_b64 exec, exec
16; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0
17; GCN-NEXT:    s_endpgm
18  %tmp = call i32 @llvm.amdgcn.set.inactive.i32(i32 %in, i32 42) #0
19  store i32 %tmp, i32 addrspace(1)* %out
20  ret void
21}
22
23define amdgpu_kernel void @set_inactive_64(i64 addrspace(1)* %out, i64 %in) {
24; GCN-LABEL: set_inactive_64:
25; GCN:       ; %bb.0:
26; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
27; GCN-NEXT:    s_mov_b32 s3, 0xf000
28; GCN-NEXT:    s_mov_b32 s2, -1
29; GCN-NEXT:    s_waitcnt lgkmcnt(0)
30; GCN-NEXT:    s_mov_b32 s0, s4
31; GCN-NEXT:    s_mov_b32 s1, s5
32; GCN-NEXT:    v_mov_b32_e32 v0, s6
33; GCN-NEXT:    v_mov_b32_e32 v1, s7
34; GCN-NEXT:    s_not_b64 exec, exec
35; GCN-NEXT:    v_mov_b32_e32 v0, 0
36; GCN-NEXT:    v_mov_b32_e32 v1, 0
37; GCN-NEXT:    s_not_b64 exec, exec
38; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
39; GCN-NEXT:    s_endpgm
40  %tmp = call i64 @llvm.amdgcn.set.inactive.i64(i64 %in, i64 0) #0
41  store i64 %tmp, i64 addrspace(1)* %out
42  ret void
43}
44
45define amdgpu_kernel void @set_inactive_scc(i32 addrspace(1)* %out, i32 %in, <4 x i32> inreg %desc) {
46; GCN-LABEL: set_inactive_scc:
47; GCN:       ; %bb.0:
48; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
49; GCN-NEXT:    s_load_dword s6, s[0:1], 0x2c
50; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
51; GCN-NEXT:    s_waitcnt lgkmcnt(0)
52; GCN-NEXT:    s_buffer_load_dword s0, s[0:3], 0x0
53; GCN-NEXT:    v_mov_b32_e32 v0, s6
54; GCN-NEXT:    s_not_b64 exec, exec
55; GCN-NEXT:    v_mov_b32_e32 v0, 42
56; GCN-NEXT:    s_not_b64 exec, exec
57; GCN-NEXT:    s_waitcnt lgkmcnt(0)
58; GCN-NEXT:    s_cmp_lg_u32 s0, 56
59; GCN-NEXT:    s_mov_b64 s[0:1], -1
60; GCN-NEXT:    s_cbranch_scc1 BB2_3
61; GCN-NEXT:  ; %bb.1: ; %Flow
62; GCN-NEXT:    s_andn2_b64 vcc, exec, s[0:1]
63; GCN-NEXT:    s_cbranch_vccz BB2_4
64; GCN-NEXT:  BB2_2: ; %.exit
65; GCN-NEXT:    s_endpgm
66; GCN-NEXT:  BB2_3: ; %.one
67; GCN-NEXT:    v_add_u32_e32 v1, vcc, 1, v0
68; GCN-NEXT:    s_mov_b32 s7, 0xf000
69; GCN-NEXT:    s_mov_b32 s6, -1
70; GCN-NEXT:    buffer_store_dword v1, off, s[4:7], 0
71; GCN-NEXT:    s_cbranch_execnz BB2_2
72; GCN-NEXT:  BB2_4: ; %.zero
73; GCN-NEXT:    s_mov_b32 s7, 0xf000
74; GCN-NEXT:    s_mov_b32 s6, -1
75; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0
76; GCN-NEXT:    s_endpgm
77  %val = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 0, i32 0)
78  %cmp = icmp eq i32 %val, 56
79  %tmp = call i32 @llvm.amdgcn.set.inactive.i32(i32 %in, i32 42) #0
80  br i1 %cmp, label %.zero, label %.one
81
82.zero:
83  store i32 %tmp, i32 addrspace(1)* %out
84  br label %.exit
85
86.one:
87  %tmp.1 = add i32 %tmp, 1
88  store i32 %tmp.1, i32 addrspace(1)* %out
89  br label %.exit
90
91.exit:
92  ret void
93}
94
95declare i32 @llvm.amdgcn.set.inactive.i32(i32, i32) #0
96declare i64 @llvm.amdgcn.set.inactive.i64(i64, i64) #0
97declare i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32>, i32, i32)
98
99attributes #0 = { convergent readnone }
100