1;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefixes=SICI,PREGFX10 2;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefixes=VI,PREGFX10 3;RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=GFX10 4 5;CHECK-LABEL: {{^}}buffer_load: 6;CHECK: buffer_load_dwordx4 v[0:3], off, s[0:3], 0{{$}} 7;CHECK: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 glc{{$}} 8;CHECK: buffer_load_dwordx4 v[8:11], off, s[0:3], 0 slc{{$}} 9;CHECK: s_waitcnt 10define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) { 11main_body: 12 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 0) 13 %data_glc = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 1) 14 %data_slc = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 2) 15 %r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0 16 %r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1 17 %r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2 18 ret {<4 x float>, <4 x float>, <4 x float>} %r2 19} 20 21;CHECK-LABEL: {{^}}buffer_load_dlc: 22;PREGFX10: buffer_load_dwordx4 v[0:3], off, s[0:3], 0{{$}} 23;PREGFX10: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 glc{{$}} 24;PREGFX10: buffer_load_dwordx4 v[8:11], off, s[0:3], 0 slc{{$}} 25;GFX10: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 dlc{{$}} 26;GFX10: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 glc dlc{{$}} 27;GFX10: buffer_load_dwordx4 v[8:11], off, s[0:3], 0 slc dlc{{$}} 28;CHECK: s_waitcnt 29define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load_dlc(<4 x i32> inreg) { 30main_body: 31 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 4) 32 %data_glc = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 5) 33 %data_slc = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 6) 34 %r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0 35 %r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1 36 %r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2 37 ret {<4 x float>, <4 x float>, <4 x float>} %r2 38} 39 40;CHECK-LABEL: {{^}}buffer_load_immoffs: 41;CHECK: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:40 42;CHECK: s_waitcnt 43define amdgpu_ps <4 x float> @buffer_load_immoffs(<4 x i32> inreg) { 44main_body: 45 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 40, i32 0, i32 0) 46 ret <4 x float> %data 47} 48 49;CHECK-LABEL: {{^}}buffer_load_immoffs_large: 50;CHECK: s_movk_i32 [[OFFSET:s[0-9]+]], 0x1ffc 51;CHECK: buffer_load_dwordx4 v[0:3], off, s[0:3], [[OFFSET]] offset:4 52;CHECK: s_waitcnt 53define amdgpu_ps <4 x float> @buffer_load_immoffs_large(<4 x i32> inreg) { 54main_body: 55 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 4, i32 8188, i32 0) 56 ret <4 x float> %data 57} 58 59;CHECK-LABEL: {{^}}buffer_load_ofs: 60;CHECK: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen 61;CHECK: s_waitcnt 62define amdgpu_ps <4 x float> @buffer_load_ofs(<4 x i32> inreg, i32) { 63main_body: 64 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 %1, i32 0, i32 0) 65 ret <4 x float> %data 66} 67 68;CHECK-LABEL: {{^}}buffer_load_ofs_imm: 69;CHECK: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:60 70;CHECK: s_waitcnt 71define amdgpu_ps <4 x float> @buffer_load_ofs_imm(<4 x i32> inreg, i32) { 72main_body: 73 %ofs = add i32 %1, 60 74 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 %ofs, i32 0, i32 0) 75 ret <4 x float> %data 76} 77 78;CHECK-LABEL: {{^}}buffer_load_x1: 79;CHECK: buffer_load_dword v0, v0, s[0:3], 0 offen 80;CHECK: s_waitcnt 81define amdgpu_ps float @buffer_load_x1(<4 x i32> inreg %rsrc, i32 %ofs) { 82main_body: 83 %data = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %ofs, i32 0, i32 0) 84 ret float %data 85} 86 87;CHECK-LABEL: {{^}}buffer_load_x2: 88;CHECK: buffer_load_dwordx2 v[0:1], v0, s[0:3], 0 offen 89;CHECK: s_waitcnt 90define amdgpu_ps <2 x float> @buffer_load_x2(<4 x i32> inreg %rsrc, i32 %ofs) { 91main_body: 92 %data = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %ofs, i32 0, i32 0) 93 ret <2 x float> %data 94} 95 96;CHECK-LABEL: {{^}}buffer_load_negative_offset: 97;PREGFX10: v_add_{{[iu]}}32_e32 [[VOFS:v[0-9]+]], vcc, -16, v0 98;GFX10: v_add_nc_{{[iu]}}32_e32 [[VOFS:v[0-9]+]], -16, v0 99;CHECK: buffer_load_dwordx4 v[0:3], [[VOFS]], s[0:3], 0 offen 100define amdgpu_ps <4 x float> @buffer_load_negative_offset(<4 x i32> inreg, i32 %ofs) { 101main_body: 102 %ofs.1 = add i32 %ofs, -16 103 %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 %ofs.1, i32 0, i32 0) 104 ret <4 x float> %data 105} 106 107; SI won't merge ds memory operations, because of the signed offset bug, so 108; we only have check lines for VI. 109; CHECK-LABEL: buffer_load_mmo: 110; VI: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0 111; VI: ds_write2_b32 v{{[0-9]+}}, [[ZERO]], [[ZERO]] offset1:4 112define amdgpu_ps float @buffer_load_mmo(<4 x i32> inreg %rsrc, float addrspace(3)* %lds) { 113entry: 114 store float 0.0, float addrspace(3)* %lds 115 %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 0, i32 0) 116 %tmp2 = getelementptr float, float addrspace(3)* %lds, i32 4 117 store float 0.0, float addrspace(3)* %tmp2 118 ret float %val 119} 120 121;CHECK-LABEL: {{^}}buffer_load_x1_offen_merged_and: 122;CHECK-NEXT: %bb. 123;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4 124;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:28 125;CHECK: s_waitcnt 126define amdgpu_ps void @buffer_load_x1_offen_merged_and(<4 x i32> inreg %rsrc, i32 %a) { 127main_body: 128 %a1 = add i32 %a, 4 129 %a2 = add i32 %a, 8 130 %a3 = add i32 %a, 12 131 %a4 = add i32 %a, 16 132 %a5 = add i32 %a, 28 133 %a6 = add i32 %a, 32 134 %r1 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a1, i32 0, i32 0) 135 %r2 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a2, i32 0, i32 0) 136 %r3 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a3, i32 0, i32 0) 137 %r4 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a4, i32 0, i32 0) 138 %r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a5, i32 0, i32 0) 139 %r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a6, i32 0, i32 0) 140 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) 141 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) 142 ret void 143} 144 145;CHECK-LABEL: {{^}}buffer_load_x1_offen_merged_or: 146;CHECK-NEXT: %bb. 147;CHECK-NEXT: v_lshlrev_b32_e32 v{{[0-9]}}, 6, v0 148;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v{{[0-9]}}, s[0:3], 0 offen offset:4 149;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v{{[0-9]}}, s[0:3], 0 offen offset:28 150;CHECK: s_waitcnt 151define amdgpu_ps void @buffer_load_x1_offen_merged_or(<4 x i32> inreg %rsrc, i32 %inp) { 152main_body: 153 %a = shl i32 %inp, 6 154 %a1 = or i32 %a, 4 155 %a2 = or i32 %a, 8 156 %a3 = or i32 %a, 12 157 %a4 = or i32 %a, 16 158 %a5 = or i32 %a, 28 159 %a6 = or i32 %a, 32 160 %r1 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a1, i32 0, i32 0) 161 %r2 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a2, i32 0, i32 0) 162 %r3 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a3, i32 0, i32 0) 163 %r4 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a4, i32 0, i32 0) 164 %r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a5, i32 0, i32 0) 165 %r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a6, i32 0, i32 0) 166 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) 167 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) 168 ret void 169} 170 171;CHECK-LABEL: {{^}}buffer_load_x1_offen_merged_glc_slc: 172;CHECK-NEXT: %bb. 173;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4{{$}} 174;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:12 glc{{$}} 175;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:28 glc slc{{$}} 176;CHECK: s_waitcnt 177define amdgpu_ps void @buffer_load_x1_offen_merged_glc_slc(<4 x i32> inreg %rsrc, i32 %a) { 178main_body: 179 %a1 = add i32 %a, 4 180 %a2 = add i32 %a, 8 181 %a3 = add i32 %a, 12 182 %a4 = add i32 %a, 16 183 %a5 = add i32 %a, 28 184 %a6 = add i32 %a, 32 185 %r1 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a1, i32 0, i32 0) 186 %r2 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a2, i32 0, i32 0) 187 %r3 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a3, i32 0, i32 1) 188 %r4 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a4, i32 0, i32 1) 189 %r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a5, i32 0, i32 3) 190 %r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a6, i32 0, i32 3) 191 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) 192 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) 193 ret void 194} 195 196;CHECK-LABEL: {{^}}buffer_load_x2_offen_merged_and: 197;CHECK-NEXT: %bb. 198;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4 199;CHECK: s_waitcnt 200define amdgpu_ps void @buffer_load_x2_offen_merged_and(<4 x i32> inreg %rsrc, i32 %a) { 201main_body: 202 %a1 = add i32 %a, 4 203 %a2 = add i32 %a, 12 204 %vr1 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %a1, i32 0, i32 0) 205 %vr2 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %a2, i32 0, i32 0) 206 %r1 = extractelement <2 x float> %vr1, i32 0 207 %r2 = extractelement <2 x float> %vr1, i32 1 208 %r3 = extractelement <2 x float> %vr2, i32 0 209 %r4 = extractelement <2 x float> %vr2, i32 1 210 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) 211 ret void 212} 213 214;CHECK-LABEL: {{^}}buffer_load_x2_offen_merged_or: 215;CHECK-NEXT: %bb. 216;CHECK-NEXT: v_lshlrev_b32_e32 v{{[0-9]}}, 4, v0 217;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v{{[0-9]}}, s[0:3], 0 offen offset:4 218;CHECK: s_waitcnt 219define amdgpu_ps void @buffer_load_x2_offen_merged_or(<4 x i32> inreg %rsrc, i32 %inp) { 220main_body: 221 %a = shl i32 %inp, 4 222 %a1 = add i32 %a, 4 223 %a2 = add i32 %a, 12 224 %vr1 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %a1, i32 0, i32 0) 225 %vr2 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %a2, i32 0, i32 0) 226 %r1 = extractelement <2 x float> %vr1, i32 0 227 %r2 = extractelement <2 x float> %vr1, i32 1 228 %r3 = extractelement <2 x float> %vr2, i32 0 229 %r4 = extractelement <2 x float> %vr2, i32 1 230 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) 231 ret void 232} 233 234;CHECK-LABEL: {{^}}buffer_load_x1_offset_merged: 235;CHECK-NEXT: %bb. 236;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:4 237;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:28 238;CHECK: s_waitcnt 239define amdgpu_ps void @buffer_load_x1_offset_merged(<4 x i32> inreg %rsrc) { 240main_body: 241 %r1 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 4, i32 0, i32 0) 242 %r2 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 8, i32 0, i32 0) 243 %r3 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 12, i32 0, i32 0) 244 %r4 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 16, i32 0, i32 0) 245 %r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 28, i32 0, i32 0) 246 %r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 32, i32 0, i32 0) 247 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) 248 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) 249 ret void 250} 251 252;CHECK-LABEL: {{^}}buffer_load_x2_offset_merged: 253;CHECK-NEXT: %bb. 254;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:4 255;CHECK: s_waitcnt 256define amdgpu_ps void @buffer_load_x2_offset_merged(<4 x i32> inreg %rsrc) { 257main_body: 258 %vr1 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 4, i32 0, i32 0) 259 %vr2 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 12, i32 0, i32 0) 260 %r1 = extractelement <2 x float> %vr1, i32 0 261 %r2 = extractelement <2 x float> %vr1, i32 1 262 %r3 = extractelement <2 x float> %vr2, i32 0 263 %r4 = extractelement <2 x float> %vr2, i32 1 264 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) 265 ret void 266} 267 268;CHECK-LABEL: {{^}}buffer_load_int: 269;CHECK: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 270;CHECK: buffer_load_dwordx2 v[4:5], off, s[0:3], 0 glc 271;CHECK: buffer_load_dword v6, off, s[0:3], 0 slc 272;CHECK: s_waitcnt 273define amdgpu_ps {<4 x float>, <2 x float>, float} @buffer_load_int(<4 x i32> inreg) { 274main_body: 275 %data = call <4 x i32> @llvm.amdgcn.raw.buffer.load.v4i32(<4 x i32> %0, i32 0, i32 0, i32 0) 276 %data_glc = call <2 x i32> @llvm.amdgcn.raw.buffer.load.v2i32(<4 x i32> %0, i32 0, i32 0, i32 1) 277 %data_slc = call i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32> %0, i32 0, i32 0, i32 2) 278 %fdata = bitcast <4 x i32> %data to <4 x float> 279 %fdata_glc = bitcast <2 x i32> %data_glc to <2 x float> 280 %fdata_slc = bitcast i32 %data_slc to float 281 %r0 = insertvalue {<4 x float>, <2 x float>, float} undef, <4 x float> %fdata, 0 282 %r1 = insertvalue {<4 x float>, <2 x float>, float} %r0, <2 x float> %fdata_glc, 1 283 %r2 = insertvalue {<4 x float>, <2 x float>, float} %r1, float %fdata_slc, 2 284 ret {<4 x float>, <2 x float>, float} %r2 285} 286 287;CHECK-LABEL: {{^}}raw_buffer_load_ubyte: 288;CHECK-NEXT: %bb. 289;CHECK-NEXT: buffer_load_ubyte v{{[0-9]}}, off, s[0:3], 0 290;CHECK: s_waitcnt vmcnt(0) 291;CHECK-NEXT: v_cvt_f32_ubyte0_e32 v0, v0 292;CHECK-NEXT: ; return to shader part epilog 293define amdgpu_ps float @raw_buffer_load_ubyte(<4 x i32> inreg %rsrc) { 294main_body: 295 %tmp = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 0, i32 0, i32 0) 296 %tmp2 = zext i8 %tmp to i32 297 %val = uitofp i32 %tmp2 to float 298 ret float %val 299} 300 301;CHECK-LABEL: {{^}}raw_buffer_load_i16: 302;CHECK-NEXT: %bb. 303;CHECK-NEXT: buffer_load_ushort v{{[0-9]}}, off, s[0:3], 0 304;CHECK: s_waitcnt vmcnt(0) 305;CHECK-NEXT: v_cvt_f32_u32_e32 v0, v0 306;CHECK-NEXT: ; return to shader part epilog 307define amdgpu_ps float @raw_buffer_load_i16(<4 x i32> inreg %rsrc) { 308main_body: 309 %tmp = call i16 @llvm.amdgcn.raw.buffer.load.i16(<4 x i32> %rsrc, i32 0, i32 0, i32 0) 310 %tmp2 = zext i16 %tmp to i32 311 %val = uitofp i32 %tmp2 to float 312 ret float %val 313} 314 315;CHECK-LABEL: {{^}}raw_buffer_load_sbyte: 316;CHECK-NEXT: %bb. 317;CHECK-NEXT: buffer_load_sbyte v{{[0-9]}}, off, s[0:3], 0 318;CHECK: s_waitcnt vmcnt(0) 319;CHECK-NEXT: v_cvt_f32_i32_e32 v0, v0 320;CHECK-NEXT: ; return to shader part epilog 321define amdgpu_ps float @raw_buffer_load_sbyte(<4 x i32> inreg %rsrc) { 322main_body: 323 %tmp = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 0, i32 0, i32 0) 324 %tmp2 = sext i8 %tmp to i32 325 %val = sitofp i32 %tmp2 to float 326 ret float %val 327} 328 329;CHECK-LABEL: {{^}}raw_buffer_load_sshort: 330;CHECK-NEXT: %bb. 331;CHECK-NEXT: buffer_load_sshort v{{[0-9]}}, off, s[0:3], 0 332;CHECK: s_waitcnt vmcnt(0) 333;CHECK-NEXT: v_cvt_f32_i32_e32 v0, v0 334;CHECK-NEXT: ; return to shader part epilog 335define amdgpu_ps float @raw_buffer_load_sshort(<4 x i32> inreg %rsrc) { 336main_body: 337 %tmp = call i16 @llvm.amdgcn.raw.buffer.load.i16(<4 x i32> %rsrc, i32 0, i32 0, i32 0) 338 %tmp2 = sext i16 %tmp to i32 339 %val = sitofp i32 %tmp2 to float 340 ret float %val 341} 342 343;CHECK-LABEL: {{^}}raw_buffer_load_f16: 344;CHECK-NEXT: %bb. 345;CHECK-NEXT: buffer_load_ushort [[VAL:v[0-9]+]], off, s[0:3], 0 346;CHECK: s_waitcnt vmcnt(0) 347;CHECK: ds_write_b16 v0, [[VAL]] 348define amdgpu_ps void @raw_buffer_load_f16(<4 x i32> inreg %rsrc, half addrspace(3)* %ptr) { 349main_body: 350 %val = call half @llvm.amdgcn.raw.buffer.load.f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0) 351 store half %val, half addrspace(3)* %ptr 352 ret void 353} 354 355;CHECK-LABEL: {{^}}raw_buffer_load_v2f16: 356;CHECK-NEXT: %bb. 357;CHECK-NEXT: buffer_load_dword [[VAL:v[0-9]+]], off, s[0:3], 0 358;CHECK: s_waitcnt vmcnt(0) 359;CHECK: ds_write_b32 v0, [[VAL]] 360define amdgpu_ps void @raw_buffer_load_v2f16(<4 x i32> inreg %rsrc, <2 x half> addrspace(3)* %ptr) { 361main_body: 362 %val = call <2 x half> @llvm.amdgcn.raw.buffer.load.v2f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0) 363 store <2 x half> %val, <2 x half> addrspace(3)* %ptr 364 ret void 365} 366 367;CHECK-LABEL: {{^}}raw_buffer_load_v4f16: 368;CHECK-NEXT: %bb. 369;CHECK-NEXT: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]], off, s[0:3], 0 370;CHECK: s_waitcnt vmcnt(0) 371;CHECK: ds_write_b64 v0, [[VAL]] 372define amdgpu_ps void @raw_buffer_load_v4f16(<4 x i32> inreg %rsrc, <4 x half> addrspace(3)* %ptr) { 373main_body: 374 %val = call <4 x half> @llvm.amdgcn.raw.buffer.load.v4f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0) 375 store <4 x half> %val, <4 x half> addrspace(3)* %ptr 376 ret void 377} 378 379;CHECK-LABEL: {{^}}raw_buffer_load_v2i16: 380;CHECK-NEXT: %bb. 381;CHECK-NEXT: buffer_load_dword [[VAL:v[0-9]+]], off, s[0:3], 0 382;CHECK: s_waitcnt vmcnt(0) 383;CHECK: ds_write_b32 v0, [[VAL]] 384define amdgpu_ps void @raw_buffer_load_v2i16(<4 x i32> inreg %rsrc, <2 x i16> addrspace(3)* %ptr) { 385main_body: 386 %val = call <2 x i16> @llvm.amdgcn.raw.buffer.load.v2i16(<4 x i32> %rsrc, i32 0, i32 0, i32 0) 387 store <2 x i16> %val, <2 x i16> addrspace(3)* %ptr 388 ret void 389} 390 391;CHECK-LABEL: {{^}}raw_buffer_load_v4i16: 392;CHECK-NEXT: %bb. 393;CHECK-NEXT: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]], off, s[0:3], 0 394;CHECK: s_waitcnt vmcnt(0) 395;CHECK: ds_write_b64 v0, [[VAL]] 396define amdgpu_ps void @raw_buffer_load_v4i16(<4 x i32> inreg %rsrc, <4 x i16> addrspace(3)* %ptr) { 397main_body: 398 %val = call <4 x i16> @llvm.amdgcn.raw.buffer.load.v4i16(<4 x i32> %rsrc, i32 0, i32 0, i32 0) 399 store <4 x i16> %val, <4 x i16> addrspace(3)* %ptr 400 ret void 401} 402 403;CHECK-LABEL: {{^}}raw_buffer_load_x1_offset_merged: 404;CHECK-NEXT: %bb. 405;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:4 406;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:28 407;CHECK: s_waitcnt 408define amdgpu_ps void @raw_buffer_load_x1_offset_merged(<4 x i32> inreg %rsrc) { 409main_body: 410 %r1 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 4, i32 0, i32 0) 411 %r2 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 8, i32 0, i32 0) 412 %r3 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 12, i32 0, i32 0) 413 %r4 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 16, i32 0, i32 0) 414 %r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 28, i32 0, i32 0) 415 %r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 32, i32 0, i32 0) 416 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) 417 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) 418 ret void 419} 420 421;CHECK-LABEL: {{^}}raw_buffer_load_x1_offset_swizzled_not_merged: 422;CHECK-NEXT: %bb. 423;CHECK-NEXT: buffer_load_dword v{{[0-9]}}, off, s[0:3], 0 offset:4 424;CHECK-NEXT: buffer_load_dword v{{[0-9]}}, off, s[0:3], 0 offset:8 425;CHECK-NEXT: buffer_load_dword v{{[0-9]}}, off, s[0:3], 0 offset:12 426;CHECK-NEXT: buffer_load_dword v{{[0-9]}}, off, s[0:3], 0 offset:16 427;CHECK-NEXT: buffer_load_dword v{{[0-9]}}, off, s[0:3], 0 offset:28 428;CHECK-NEXT: buffer_load_dword v{{[0-9]}}, off, s[0:3], 0 offset:32 429;CHECK: s_waitcnt 430define amdgpu_ps void @raw_buffer_load_x1_offset_swizzled_not_merged(<4 x i32> inreg %rsrc) { 431main_body: 432 %r1 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 4, i32 0, i32 8) 433 %r2 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 8, i32 0, i32 8) 434 %r3 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 12, i32 0, i32 8) 435 %r4 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 16, i32 0, i32 8) 436 %r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 28, i32 0, i32 8) 437 %r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 32, i32 0, i32 8) 438 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) 439 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) 440 ret void 441} 442 443declare float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32>, i32, i32, i32) #0 444declare <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32>, i32, i32, i32) #0 445declare <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32>, i32, i32, i32) #0 446declare i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32>, i32, i32, i32) #0 447declare <2 x i32> @llvm.amdgcn.raw.buffer.load.v2i32(<4 x i32>, i32, i32, i32) #0 448declare <4 x i32> @llvm.amdgcn.raw.buffer.load.v4i32(<4 x i32>, i32, i32, i32) #0 449declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0 450declare i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32>, i32, i32, i32) #0 451declare i16 @llvm.amdgcn.raw.buffer.load.i16(<4 x i32>, i32, i32, i32) #0 452declare <2 x i16> @llvm.amdgcn.raw.buffer.load.v2i16(<4 x i32>, i32, i32, i32) #0 453declare <4 x i16> @llvm.amdgcn.raw.buffer.load.v4i16(<4 x i32>, i32, i32, i32) #0 454declare half @llvm.amdgcn.raw.buffer.load.f16(<4 x i32>, i32, i32, i32) #0 455declare <2 x half> @llvm.amdgcn.raw.buffer.load.v2f16(<4 x i32>, i32, i32, i32) #0 456declare <4 x half> @llvm.amdgcn.raw.buffer.load.v4f16(<4 x i32>, i32, i32, i32) #0 457 458attributes #0 = { nounwind readonly } 459