1; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX11 %s
2; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX11 %s
3
4; GFX11-LABEL: {{^}}lds_direct_load:
5; GFX11: s_mov_b32 m0
6; GFX11: lds_direct_load v{{[0-9]+}}
7; GFX11: s_mov_b32 m0
8; GFX11: lds_direct_load v{{[0-9]+}}
9; GFX11: s_mov_b32 m0
10; GFX11: lds_direct_load v{{[0-9]+}}
11; GFX11: v_add_f32
12; GFX11: buffer_store_b32
13; GFX11: buffer_store_b32
14; GFX11: buffer_store_b32
15; GFX11: buffer_store_b32
16; GFX11: buffer_store_b32
17; GFX11: buffer_store_b32
18define amdgpu_ps void @lds_direct_load(<4 x i32> inreg %buf, i32 inreg %arg0,
19                                       i32 inreg %arg1, i32 inreg %arg2) #0 {
20main_body:
21  %p0 = call float @llvm.amdgcn.lds.direct.load(i32 %arg0)
22  ; Ensure memory clustering is occuring for lds_direct_load
23  %p5 = fadd float %p0, 1.0
24  %p1 = call float @llvm.amdgcn.lds.direct.load(i32 %arg1)
25  %p2 = call float @llvm.amdgcn.lds.direct.load(i32 %arg2)
26  %p3 = call float @llvm.amdgcn.lds.direct.load(i32 %arg1)
27  %p4 = call float @llvm.amdgcn.lds.direct.load(i32 %arg2)
28  call void @llvm.amdgcn.raw.buffer.store.f32(float %p5, <4 x i32> %buf, i32 4, i32 0, i32 0)
29  call void @llvm.amdgcn.raw.buffer.store.f32(float %p1, <4 x i32> %buf, i32 4, i32 1, i32 0)
30  call void @llvm.amdgcn.raw.buffer.store.f32(float %p2, <4 x i32> %buf, i32 4, i32 2, i32 0)
31  call void @llvm.amdgcn.raw.buffer.store.f32(float %p3, <4 x i32> %buf, i32 4, i32 3, i32 0)
32  call void @llvm.amdgcn.raw.buffer.store.f32(float %p4, <4 x i32> %buf, i32 4, i32 4, i32 0)
33  call void @llvm.amdgcn.raw.buffer.store.f32(float %p0, <4 x i32> %buf, i32 4, i32 5, i32 0)
34  ret void
35}
36
37declare float @llvm.amdgcn.lds.direct.load(i32) #1
38declare void @llvm.amdgcn.raw.buffer.store.f32(float, <4 x i32>, i32, i32, i32)
39
40attributes #0 = { nounwind }
41attributes #1 = { nounwind readonly }
42