1; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-NOENV %s
2; RUN: llc -mtriple=amdgcn--amdhsa-opencl -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-OPENCL %s
3; RUN: llc -mtriple=amdgcn-mesa-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,OS-MESA3D,MESA,ALL %s
4; RUN: llc -mtriple=amdgcn-mesa-unknown -verify-machineinstrs < %s | FileCheck -check-prefixes=OS-UNKNOWN,MESA,ALL %s
5
6; ALL-LABEL: {{^}}test:
7; CO-V2: enable_sgpr_kernarg_segment_ptr = 1
8; CO-V2: s_load_dword s{{[0-9]+}}, s[4:5], 0xa
9
10; OS-UNKNOWN: s_load_dword s{{[0-9]+}}, s[0:1], 0xa
11define void @test(i32 addrspace(1)* %out) #1 {
12  %kernarg.segment.ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr()
13  %header.ptr = bitcast i8 addrspace(2)* %kernarg.segment.ptr to i32 addrspace(2)*
14  %gep = getelementptr i32, i32 addrspace(2)* %header.ptr, i64 10
15  %value = load i32, i32 addrspace(2)* %gep
16  store i32 %value, i32 addrspace(1)* %out
17  ret void
18}
19
20; ALL-LABEL: {{^}}test_implicit:
21; 10 + 9 (36 prepended implicit bytes) + 2(out pointer) = 21 = 0x15
22; OS-UNKNOWN: s_load_dword s{{[0-9]+}}, s[0:1], 0x15
23define void @test_implicit(i32 addrspace(1)* %out) #1 {
24  %implicitarg.ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr()
25  %header.ptr = bitcast i8 addrspace(2)* %implicitarg.ptr to i32 addrspace(2)*
26  %gep = getelementptr i32, i32 addrspace(2)* %header.ptr, i64 10
27  %value = load i32, i32 addrspace(2)* %gep
28  store i32 %value, i32 addrspace(1)* %out
29  ret void
30}
31
32; ALL-LABEL: {{^}}test_implicit_alignment
33; HSA-NOENV: kernarg_segment_byte_size = 10
34; HSA-OPENCL: kernarg_segment_byte_size = 48
35; OS-MESA3D: kernarg_segment_byte_size = 28
36; OS-UNKNOWN: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xc
37; HSA: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x4
38; OS-MESA3D: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x3
39; ALL: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[VAL]]
40; MESA: buffer_store_dword [[V_VAL]]
41; HSA: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[V_VAL]]
42define void @test_implicit_alignment(i32 addrspace(1)* %out, <2 x i8> %in) #1 {
43  %implicitarg.ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr()
44  %arg.ptr = bitcast i8 addrspace(2)* %implicitarg.ptr to i32 addrspace(2)*
45  %val = load i32, i32 addrspace(2)* %arg.ptr
46  store i32 %val, i32 addrspace(1)* %out
47  ret void
48}
49
50declare i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr() #0
51declare i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() #0
52
53attributes #0 = { nounwind readnone }
54attributes #1 = { nounwind }
55