1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx1013 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX1013 %s
3; RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX1030 %s
4; RUN: not --crash llc -march=amdgcn -mcpu=gfx1012 -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERR %s
5
6; uint4 llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(uint node_ptr, float ray_extent, float3 ray_origin, float3 ray_dir, float3 ray_inv_dir, uint4 texture_descr)
7; uint4 llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(uint node_ptr, float ray_extent, float3 ray_origin, half3 ray_dir, half3 ray_inv_dir, uint4 texture_descr)
8; uint4 llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(ulong node_ptr, float ray_extent, float3 ray_origin, float3 ray_dir, float3 ray_inv_dir, uint4 texture_descr)
9; uint4 llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(ulong node_ptr, float ray_extent, float3 ray_origin, half3 ray_dir, half3 ray_inv_dir, uint4 texture_descr)
10
11declare <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(i32, float, <3 x float>, <3 x float>, <3 x float>, <4 x i32>)
12declare <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32, float, <3 x float>, <3 x half>, <3 x half>, <4 x i32>)
13declare <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64, float, <3 x float>, <3 x float>, <3 x float>, <4 x i32>)
14declare <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64, float, <3 x float>, <3 x half>, <3 x half>, <4 x i32>)
15
16; ERR: in function image_bvh_intersect_ray{{.*}}intrinsic not supported on subtarget
17; Arguments are flattened to represent the actual VGPR_A layout, so we have no
18; extra moves in the generated kernel.
19define amdgpu_ps <4 x float> @image_bvh_intersect_ray(i32 %node_ptr, float %ray_extent, float %ray_origin_x, float %ray_origin_y, float %ray_origin_z, float %ray_dir_x, float %ray_dir_y, float %ray_dir_z, float %ray_inv_dir_x, float %ray_inv_dir_y, float %ray_inv_dir_z, <4 x i32> inreg %tdescr) {
20; GCN-LABEL: image_bvh_intersect_ray:
21; GCN:       ; %bb.0: ; %main_body
22; GCN-NEXT:    image_bvh_intersect_ray v[0:3], v[0:15], s[0:3]
23; GCN-NEXT:    s_waitcnt vmcnt(0)
24; GCN-NEXT:    ; return to shader part epilog
25main_body:
26  %ray_origin0 = insertelement <3 x float> undef, float %ray_origin_x, i32 0
27  %ray_origin1 = insertelement <3 x float> %ray_origin0, float %ray_origin_y, i32 1
28  %ray_origin = insertelement <3 x float> %ray_origin1, float %ray_origin_z, i32 2
29  %ray_dir0 = insertelement <3 x float> undef, float %ray_dir_x, i32 0
30  %ray_dir1 = insertelement <3 x float> %ray_dir0, float %ray_dir_y, i32 1
31  %ray_dir = insertelement <3 x float> %ray_dir1, float %ray_dir_z, i32 2
32  %ray_inv_dir0 = insertelement <3 x float> undef, float %ray_inv_dir_x, i32 0
33  %ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float %ray_inv_dir_y, i32 1
34  %ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float %ray_inv_dir_z, i32 2
35  %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
36 %r = bitcast <4 x i32> %v to <4 x float>
37 ret <4 x float> %r
38}
39
40define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16(i32 inreg %node_ptr, float inreg %ray_extent, <3 x float> inreg %ray_origin, <3 x half> inreg %ray_dir, <3 x half> inreg %ray_inv_dir, <4 x i32> inreg %tdescr) {
41; GCN-LABEL: image_bvh_intersect_ray_a16:
42; GCN:       ; %bb.0: ; %main_body
43; GCN-NEXT:    s_mov_b32 s15, s12
44; GCN-NEXT:    s_mov_b32 s12, s9
45; GCN-NEXT:    s_lshr_b32 s9, s7, 16
46; GCN-NEXT:    s_pack_ll_b32_b16 s6, s6, s7
47; GCN-NEXT:    s_pack_ll_b32_b16 s7, s9, s8
48; GCN-NEXT:    v_mov_b32_e32 v0, s0
49; GCN-NEXT:    v_mov_b32_e32 v1, s1
50; GCN-NEXT:    v_mov_b32_e32 v2, s2
51; GCN-NEXT:    v_mov_b32_e32 v3, s3
52; GCN-NEXT:    v_mov_b32_e32 v4, s4
53; GCN-NEXT:    v_mov_b32_e32 v5, s5
54; GCN-NEXT:    v_mov_b32_e32 v6, s6
55; GCN-NEXT:    v_mov_b32_e32 v7, s7
56; GCN-NEXT:    s_mov_b32 s14, s11
57; GCN-NEXT:    s_mov_b32 s13, s10
58; GCN-NEXT:    image_bvh_intersect_ray v[0:3], v[0:7], s[12:15] a16
59; GCN-NEXT:    s_waitcnt vmcnt(0)
60; GCN-NEXT:    ; return to shader part epilog
61main_body:
62  %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr)
63  %r = bitcast <4 x i32> %v to <4 x float>
64  ret <4 x float> %r
65}
66
67; Arguments are flattened to represent the actual VGPR_A layout, so we have no
68; extra moves in the generated kernel.
69define amdgpu_ps <4 x float> @image_bvh64_intersect_ray(<2 x i32> %node_ptr_vec, float %ray_extent, float %ray_origin_x, float %ray_origin_y, float %ray_origin_z, float %ray_dir_x, float %ray_dir_y, float %ray_dir_z, float %ray_inv_dir_x, float %ray_inv_dir_y, float %ray_inv_dir_z, <4 x i32> inreg %tdescr) {
70; GCN-LABEL: image_bvh64_intersect_ray:
71; GCN:       ; %bb.0: ; %main_body
72; GCN-NEXT:    image_bvh64_intersect_ray v[0:3], v[0:15], s[0:3]
73; GCN-NEXT:    s_waitcnt vmcnt(0)
74; GCN-NEXT:    ; return to shader part epilog
75main_body:
76  %node_ptr = bitcast <2 x i32> %node_ptr_vec to i64
77  %ray_origin0 = insertelement <3 x float> undef, float %ray_origin_x, i32 0
78  %ray_origin1 = insertelement <3 x float> %ray_origin0, float %ray_origin_y, i32 1
79  %ray_origin = insertelement <3 x float> %ray_origin1, float %ray_origin_z, i32 2
80  %ray_dir0 = insertelement <3 x float> undef, float %ray_dir_x, i32 0
81  %ray_dir1 = insertelement <3 x float> %ray_dir0, float %ray_dir_y, i32 1
82  %ray_dir = insertelement <3 x float> %ray_dir1, float %ray_dir_z, i32 2
83  %ray_inv_dir0 = insertelement <3 x float> undef, float %ray_inv_dir_x, i32 0
84  %ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float %ray_inv_dir_y, i32 1
85  %ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float %ray_inv_dir_z, i32 2
86  %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
87 %r = bitcast <4 x i32> %v to <4 x float>
88 ret <4 x float> %r
89}
90
91define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_a16(i64 inreg %node_ptr, float inreg %ray_extent, <3 x float> inreg %ray_origin, <3 x half> inreg %ray_dir, <3 x half> inreg %ray_inv_dir, <4 x i32> inreg %tdescr) {
92; GCN-LABEL: image_bvh64_intersect_ray_a16:
93; GCN:       ; %bb.0: ; %main_body
94; GCN-NEXT:    s_mov_b32 s14, s12
95; GCN-NEXT:    s_mov_b32 s12, s10
96; GCN-NEXT:    s_lshr_b32 s10, s8, 16
97; GCN-NEXT:    s_pack_ll_b32_b16 s7, s7, s8
98; GCN-NEXT:    s_pack_ll_b32_b16 s8, s10, s9
99; GCN-NEXT:    v_mov_b32_e32 v0, s0
100; GCN-NEXT:    v_mov_b32_e32 v1, s1
101; GCN-NEXT:    v_mov_b32_e32 v2, s2
102; GCN-NEXT:    v_mov_b32_e32 v3, s3
103; GCN-NEXT:    v_mov_b32_e32 v4, s4
104; GCN-NEXT:    v_mov_b32_e32 v5, s5
105; GCN-NEXT:    v_mov_b32_e32 v6, s6
106; GCN-NEXT:    v_mov_b32_e32 v7, s7
107; GCN-NEXT:    v_mov_b32_e32 v8, s8
108; GCN-NEXT:    s_mov_b32 s15, s13
109; GCN-NEXT:    s_mov_b32 s13, s11
110; GCN-NEXT:    image_bvh64_intersect_ray v[0:3], v[0:15], s[12:15] a16
111; GCN-NEXT:    s_waitcnt vmcnt(0)
112; GCN-NEXT:    ; return to shader part epilog
113main_body:
114  %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr)
115  %r = bitcast <4 x i32> %v to <4 x float>
116  ret <4 x float> %r
117}
118
119; TODO: NSA reassign is very limited and cannot work with VGPR tuples and subregs.
120
121define amdgpu_kernel void @image_bvh_intersect_ray_nsa_reassign(i32* %p_node_ptr, float* %p_ray, <4 x i32> inreg %tdescr) {
122; GFX1013-LABEL: image_bvh_intersect_ray_nsa_reassign:
123; GFX1013:       ; %bb.0: ; %main_body
124; GFX1013-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
125; GFX1013-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
126; GFX1013-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
127; GFX1013-NEXT:    v_mov_b32_e32 v6, 4.0
128; GFX1013-NEXT:    v_mov_b32_e32 v7, 0x40a00000
129; GFX1013-NEXT:    v_mov_b32_e32 v8, 0x40c00000
130; GFX1013-NEXT:    v_mov_b32_e32 v9, 0x40e00000
131; GFX1013-NEXT:    v_mov_b32_e32 v10, 0x41000000
132; GFX1013-NEXT:    s_waitcnt lgkmcnt(0)
133; GFX1013-NEXT:    v_add_co_u32 v2, s4, s4, v0
134; GFX1013-NEXT:    v_add_co_ci_u32_e64 v3, s4, s5, 0, s4
135; GFX1013-NEXT:    v_add_co_u32 v4, s4, s6, v0
136; GFX1013-NEXT:    v_add_co_ci_u32_e64 v5, s4, s7, 0, s4
137; GFX1013-NEXT:    flat_load_dword v0, v[2:3]
138; GFX1013-NEXT:    flat_load_dword v1, v[4:5]
139; GFX1013-NEXT:    v_mov_b32_e32 v2, 0
140; GFX1013-NEXT:    v_mov_b32_e32 v3, 1.0
141; GFX1013-NEXT:    v_mov_b32_e32 v4, 2.0
142; GFX1013-NEXT:    v_mov_b32_e32 v5, 0x40400000
143; GFX1013-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
144; GFX1013-NEXT:    image_bvh_intersect_ray v[0:3], v[0:15], s[0:3]
145; GFX1013-NEXT:    s_waitcnt vmcnt(0)
146; GFX1013-NEXT:    flat_store_dwordx4 v[0:1], v[0:3]
147; GFX1013-NEXT:    s_endpgm
148;
149; GFX1030-LABEL: image_bvh_intersect_ray_nsa_reassign:
150; GFX1030:       ; %bb.0: ; %main_body
151; GFX1030-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
152; GFX1030-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
153; GFX1030-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
154; GFX1030-NEXT:    v_mov_b32_e32 v10, 0x41000000
155; GFX1030-NEXT:    v_mov_b32_e32 v9, 0x40e00000
156; GFX1030-NEXT:    v_mov_b32_e32 v8, 0x40c00000
157; GFX1030-NEXT:    v_mov_b32_e32 v7, 0x40a00000
158; GFX1030-NEXT:    v_mov_b32_e32 v6, 4.0
159; GFX1030-NEXT:    v_mov_b32_e32 v5, 0x40400000
160; GFX1030-NEXT:    v_mov_b32_e32 v4, 2.0
161; GFX1030-NEXT:    s_waitcnt lgkmcnt(0)
162; GFX1030-NEXT:    v_add_co_u32 v0, s4, s4, v2
163; GFX1030-NEXT:    v_add_co_ci_u32_e64 v1, s4, s5, 0, s4
164; GFX1030-NEXT:    v_add_co_u32 v2, s4, s6, v2
165; GFX1030-NEXT:    v_add_co_ci_u32_e64 v3, s4, s7, 0, s4
166; GFX1030-NEXT:    flat_load_dword v0, v[0:1]
167; GFX1030-NEXT:    flat_load_dword v1, v[2:3]
168; GFX1030-NEXT:    v_mov_b32_e32 v2, 0
169; GFX1030-NEXT:    v_mov_b32_e32 v3, 1.0
170; GFX1030-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
171; GFX1030-NEXT:    image_bvh_intersect_ray v[0:3], v[0:15], s[0:3]
172; GFX1030-NEXT:    s_waitcnt vmcnt(0)
173; GFX1030-NEXT:    flat_store_dwordx4 v[0:1], v[0:3]
174; GFX1030-NEXT:    s_endpgm
175main_body:
176  %lid = tail call i32 @llvm.amdgcn.workitem.id.x()
177  %gep_node_ptr = getelementptr inbounds i32, i32* %p_node_ptr, i32 %lid
178  %node_ptr = load i32, i32* %gep_node_ptr, align 4
179  %gep_ray = getelementptr inbounds float, float* %p_ray, i32 %lid
180  %ray_extent = load float, float* %gep_ray, align 4
181  %ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0
182  %ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1
183  %ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2
184  %ray_dir0 = insertelement <3 x float> undef, float 3.0, i32 0
185  %ray_dir1 = insertelement <3 x float> %ray_dir0, float 4.0, i32 1
186  %ray_dir = insertelement <3 x float> %ray_dir1, float 5.0, i32 2
187  %ray_inv_dir0 = insertelement <3 x float> undef, float 6.0, i32 0
188  %ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float 7.0, i32 1
189  %ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float 8.0, i32 2
190  %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
191  store <4 x i32> %v, <4 x i32>* undef
192  ret void
193}
194
195define amdgpu_kernel void @image_bvh_intersect_ray_a16_nsa_reassign(i32* %p_node_ptr, float* %p_ray, <4 x i32> inreg %tdescr) {
196; GFX1013-LABEL: image_bvh_intersect_ray_a16_nsa_reassign:
197; GFX1013:       ; %bb.0: ; %main_body
198; GFX1013-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
199; GFX1013-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
200; GFX1013-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
201; GFX1013-NEXT:    v_mov_b32_e32 v6, 0x46004500
202; GFX1013-NEXT:    v_mov_b32_e32 v7, 0x48004700
203; GFX1013-NEXT:    s_waitcnt lgkmcnt(0)
204; GFX1013-NEXT:    v_add_co_u32 v2, s4, s4, v0
205; GFX1013-NEXT:    v_add_co_ci_u32_e64 v3, s4, s5, 0, s4
206; GFX1013-NEXT:    v_add_co_u32 v4, s4, s6, v0
207; GFX1013-NEXT:    v_add_co_ci_u32_e64 v5, s4, s7, 0, s4
208; GFX1013-NEXT:    flat_load_dword v0, v[2:3]
209; GFX1013-NEXT:    flat_load_dword v1, v[4:5]
210; GFX1013-NEXT:    v_mov_b32_e32 v2, 0
211; GFX1013-NEXT:    v_mov_b32_e32 v3, 1.0
212; GFX1013-NEXT:    v_mov_b32_e32 v4, 2.0
213; GFX1013-NEXT:    v_mov_b32_e32 v5, 0x44004200
214; GFX1013-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
215; GFX1013-NEXT:    image_bvh_intersect_ray v[0:3], v[0:7], s[0:3] a16
216; GFX1013-NEXT:    s_waitcnt vmcnt(0)
217; GFX1013-NEXT:    flat_store_dwordx4 v[0:1], v[0:3]
218; GFX1013-NEXT:    s_endpgm
219;
220; GFX1030-LABEL: image_bvh_intersect_ray_a16_nsa_reassign:
221; GFX1030:       ; %bb.0: ; %main_body
222; GFX1030-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
223; GFX1030-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
224; GFX1030-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
225; GFX1030-NEXT:    v_mov_b32_e32 v4, 2.0
226; GFX1030-NEXT:    v_mov_b32_e32 v5, 0x44004200
227; GFX1030-NEXT:    v_mov_b32_e32 v6, 0x46004500
228; GFX1030-NEXT:    v_mov_b32_e32 v7, 0x48004700
229; GFX1030-NEXT:    s_waitcnt lgkmcnt(0)
230; GFX1030-NEXT:    v_add_co_u32 v0, s4, s4, v2
231; GFX1030-NEXT:    v_add_co_ci_u32_e64 v1, s4, s5, 0, s4
232; GFX1030-NEXT:    v_add_co_u32 v2, s4, s6, v2
233; GFX1030-NEXT:    v_add_co_ci_u32_e64 v3, s4, s7, 0, s4
234; GFX1030-NEXT:    flat_load_dword v0, v[0:1]
235; GFX1030-NEXT:    flat_load_dword v1, v[2:3]
236; GFX1030-NEXT:    v_mov_b32_e32 v2, 0
237; GFX1030-NEXT:    v_mov_b32_e32 v3, 1.0
238; GFX1030-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
239; GFX1030-NEXT:    image_bvh_intersect_ray v[0:3], v[0:7], s[0:3] a16
240; GFX1030-NEXT:    s_waitcnt vmcnt(0)
241; GFX1030-NEXT:    flat_store_dwordx4 v[0:1], v[0:3]
242; GFX1030-NEXT:    s_endpgm
243main_body:
244  %lid = tail call i32 @llvm.amdgcn.workitem.id.x()
245  %gep_node_ptr = getelementptr inbounds i32, i32* %p_node_ptr, i32 %lid
246  %node_ptr = load i32, i32* %gep_node_ptr, align 4
247  %gep_ray = getelementptr inbounds float, float* %p_ray, i32 %lid
248  %ray_extent = load float, float* %gep_ray, align 4
249  %ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0
250  %ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1
251  %ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2
252  %ray_dir0 = insertelement <3 x half> undef, half 3.0, i32 0
253  %ray_dir1 = insertelement <3 x half> %ray_dir0, half 4.0, i32 1
254  %ray_dir = insertelement <3 x half> %ray_dir1, half 5.0, i32 2
255  %ray_inv_dir0 = insertelement <3 x half> undef, half 6.0, i32 0
256  %ray_inv_dir1 = insertelement <3 x half> %ray_inv_dir0, half 7.0, i32 1
257  %ray_inv_dir = insertelement <3 x half> %ray_inv_dir1, half 8.0, i32 2
258  %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr)
259  store <4 x i32> %v, <4 x i32>* undef
260  ret void
261}
262
263define amdgpu_kernel void @image_bvh64_intersect_ray_nsa_reassign(float* %p_ray, <4 x i32> inreg %tdescr) {
264; GFX1013-LABEL: image_bvh64_intersect_ray_nsa_reassign:
265; GFX1013:       ; %bb.0: ; %main_body
266; GFX1013-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
267; GFX1013-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
268; GFX1013-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
269; GFX1013-NEXT:    v_mov_b32_e32 v3, 0
270; GFX1013-NEXT:    v_mov_b32_e32 v4, 1.0
271; GFX1013-NEXT:    v_mov_b32_e32 v5, 2.0
272; GFX1013-NEXT:    v_mov_b32_e32 v6, 0x40400000
273; GFX1013-NEXT:    v_mov_b32_e32 v7, 4.0
274; GFX1013-NEXT:    v_mov_b32_e32 v8, 0x40a00000
275; GFX1013-NEXT:    v_mov_b32_e32 v9, 0x40c00000
276; GFX1013-NEXT:    v_mov_b32_e32 v10, 0x40e00000
277; GFX1013-NEXT:    v_mov_b32_e32 v11, 0x41000000
278; GFX1013-NEXT:    s_waitcnt lgkmcnt(0)
279; GFX1013-NEXT:    v_add_co_u32 v0, s4, s4, v0
280; GFX1013-NEXT:    v_add_co_ci_u32_e64 v1, s4, s5, 0, s4
281; GFX1013-NEXT:    flat_load_dword v2, v[0:1]
282; GFX1013-NEXT:    v_mov_b32_e32 v0, 0xb36211c7
283; GFX1013-NEXT:    v_mov_b32_e32 v1, 0x102
284; GFX1013-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
285; GFX1013-NEXT:    image_bvh64_intersect_ray v[0:3], v[0:15], s[0:3]
286; GFX1013-NEXT:    s_waitcnt vmcnt(0)
287; GFX1013-NEXT:    flat_store_dwordx4 v[0:1], v[0:3]
288; GFX1013-NEXT:    s_endpgm
289;
290; GFX1030-LABEL: image_bvh64_intersect_ray_nsa_reassign:
291; GFX1030:       ; %bb.0: ; %main_body
292; GFX1030-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
293; GFX1030-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
294; GFX1030-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
295; GFX1030-NEXT:    v_mov_b32_e32 v3, 0
296; GFX1030-NEXT:    v_mov_b32_e32 v11, 0x41000000
297; GFX1030-NEXT:    v_mov_b32_e32 v10, 0x40e00000
298; GFX1030-NEXT:    v_mov_b32_e32 v9, 0x40c00000
299; GFX1030-NEXT:    v_mov_b32_e32 v8, 0x40a00000
300; GFX1030-NEXT:    v_mov_b32_e32 v7, 4.0
301; GFX1030-NEXT:    v_mov_b32_e32 v6, 0x40400000
302; GFX1030-NEXT:    v_mov_b32_e32 v5, 2.0
303; GFX1030-NEXT:    v_mov_b32_e32 v4, 1.0
304; GFX1030-NEXT:    s_waitcnt lgkmcnt(0)
305; GFX1030-NEXT:    v_add_co_u32 v0, s4, s4, v0
306; GFX1030-NEXT:    v_add_co_ci_u32_e64 v1, s4, s5, 0, s4
307; GFX1030-NEXT:    flat_load_dword v2, v[0:1]
308; GFX1030-NEXT:    v_mov_b32_e32 v1, 0x102
309; GFX1030-NEXT:    v_mov_b32_e32 v0, 0xb36211c7
310; GFX1030-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
311; GFX1030-NEXT:    image_bvh64_intersect_ray v[0:3], v[0:15], s[0:3]
312; GFX1030-NEXT:    s_waitcnt vmcnt(0)
313; GFX1030-NEXT:    flat_store_dwordx4 v[0:1], v[0:3]
314; GFX1030-NEXT:    s_endpgm
315main_body:
316  %lid = tail call i32 @llvm.amdgcn.workitem.id.x()
317  %gep_ray = getelementptr inbounds float, float* %p_ray, i32 %lid
318  %ray_extent = load float, float* %gep_ray, align 4
319  %ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0
320  %ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1
321  %ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2
322  %ray_dir0 = insertelement <3 x float> undef, float 3.0, i32 0
323  %ray_dir1 = insertelement <3 x float> %ray_dir0, float 4.0, i32 1
324  %ray_dir = insertelement <3 x float> %ray_dir1, float 5.0, i32 2
325  %ray_inv_dir0 = insertelement <3 x float> undef, float 6.0, i32 0
326  %ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float 7.0, i32 1
327  %ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float 8.0, i32 2
328  %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64 1111111111111, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
329  store <4 x i32> %v, <4 x i32>* undef
330  ret void
331}
332
333define amdgpu_kernel void @image_bvh64_intersect_ray_a16_nsa_reassign(float* %p_ray, <4 x i32> inreg %tdescr) {
334; GFX1013-LABEL: image_bvh64_intersect_ray_a16_nsa_reassign:
335; GFX1013:       ; %bb.0: ; %main_body
336; GFX1013-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
337; GFX1013-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
338; GFX1013-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
339; GFX1013-NEXT:    v_mov_b32_e32 v3, 0
340; GFX1013-NEXT:    v_mov_b32_e32 v4, 1.0
341; GFX1013-NEXT:    v_mov_b32_e32 v5, 2.0
342; GFX1013-NEXT:    v_mov_b32_e32 v6, 0x44004200
343; GFX1013-NEXT:    v_mov_b32_e32 v7, 0x46004500
344; GFX1013-NEXT:    v_mov_b32_e32 v8, 0x48004700
345; GFX1013-NEXT:    s_waitcnt lgkmcnt(0)
346; GFX1013-NEXT:    v_add_co_u32 v0, s4, s4, v0
347; GFX1013-NEXT:    v_add_co_ci_u32_e64 v1, s4, s5, 0, s4
348; GFX1013-NEXT:    flat_load_dword v2, v[0:1]
349; GFX1013-NEXT:    v_mov_b32_e32 v0, 0xb36211c6
350; GFX1013-NEXT:    v_mov_b32_e32 v1, 0x102
351; GFX1013-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
352; GFX1013-NEXT:    image_bvh64_intersect_ray v[0:3], v[0:15], s[0:3] a16
353; GFX1013-NEXT:    s_waitcnt vmcnt(0)
354; GFX1013-NEXT:    flat_store_dwordx4 v[0:1], v[0:3]
355; GFX1013-NEXT:    s_endpgm
356;
357; GFX1030-LABEL: image_bvh64_intersect_ray_a16_nsa_reassign:
358; GFX1030:       ; %bb.0: ; %main_body
359; GFX1030-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
360; GFX1030-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
361; GFX1030-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
362; GFX1030-NEXT:    v_mov_b32_e32 v3, 0
363; GFX1030-NEXT:    v_mov_b32_e32 v5, 2.0
364; GFX1030-NEXT:    v_mov_b32_e32 v4, 1.0
365; GFX1030-NEXT:    v_mov_b32_e32 v6, 0x44004200
366; GFX1030-NEXT:    v_mov_b32_e32 v7, 0x46004500
367; GFX1030-NEXT:    v_mov_b32_e32 v8, 0x48004700
368; GFX1030-NEXT:    s_waitcnt lgkmcnt(0)
369; GFX1030-NEXT:    v_add_co_u32 v0, s4, s4, v0
370; GFX1030-NEXT:    v_add_co_ci_u32_e64 v1, s4, s5, 0, s4
371; GFX1030-NEXT:    flat_load_dword v2, v[0:1]
372; GFX1030-NEXT:    v_mov_b32_e32 v1, 0x102
373; GFX1030-NEXT:    v_mov_b32_e32 v0, 0xb36211c6
374; GFX1030-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
375; GFX1030-NEXT:    image_bvh64_intersect_ray v[0:3], v[0:15], s[0:3] a16
376; GFX1030-NEXT:    s_waitcnt vmcnt(0)
377; GFX1030-NEXT:    flat_store_dwordx4 v[0:1], v[0:3]
378; GFX1030-NEXT:    s_endpgm
379main_body:
380  %lid = tail call i32 @llvm.amdgcn.workitem.id.x()
381  %gep_ray = getelementptr inbounds float, float* %p_ray, i32 %lid
382  %ray_extent = load float, float* %gep_ray, align 4
383  %ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0
384  %ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1
385  %ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2
386  %ray_dir0 = insertelement <3 x half> undef, half 3.0, i32 0
387  %ray_dir1 = insertelement <3 x half> %ray_dir0, half 4.0, i32 1
388  %ray_dir = insertelement <3 x half> %ray_dir1, half 5.0, i32 2
389  %ray_inv_dir0 = insertelement <3 x half> undef, half 6.0, i32 0
390  %ray_inv_dir1 = insertelement <3 x half> %ray_inv_dir0, half 7.0, i32 1
391  %ray_inv_dir = insertelement <3 x half> %ray_inv_dir1, half 8.0, i32 2
392  %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64 1111111111110, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr)
393  store <4 x i32> %v, <4 x i32>* undef
394  ret void
395}
396
397declare i32 @llvm.amdgcn.workitem.id.x()
398