1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3
4define amdgpu_ps void @v_interp_f32(float inreg %i, float inreg %j, i32 inreg %m0) #0 {
5; GCN-LABEL: v_interp_f32:
6; GCN:       ; %bb.0: ; %main_body
7; GCN-NEXT:    s_mov_b32 s3, exec_lo
8; GCN-NEXT:    s_wqm_b32 exec_lo, exec_lo
9; GCN-NEXT:    s_mov_b32 m0, s2
10; GCN-NEXT:    lds_param_load v0, attr0.y wait_vdst:15
11; GCN-NEXT:    lds_param_load v1, attr1.x wait_vdst:15
12; GCN-NEXT:    s_mov_b32 exec_lo, s3
13; GCN-NEXT:    v_mov_b32_e32 v2, s0
14; GCN-NEXT:    v_mov_b32_e32 v4, s1
15; GCN-NEXT:    v_interp_p10_f32 v3, v0, v2, v0 wait_exp:1
16; GCN-NEXT:    v_interp_p10_f32 v2, v1, v2, v1
17; GCN-NEXT:    v_interp_p2_f32 v5, v0, v4, v3 wait_exp:7
18; GCN-NEXT:    v_interp_p2_f32 v4, v1, v4, v5 wait_exp:7
19; GCN-NEXT:    exp mrt0 v3, v2, v5, v4 done
20; GCN-NEXT:    s_endpgm
21main_body:
22  %p0 = call float @llvm.amdgcn.lds.param.load(i32 1, i32 0, i32 %m0)
23  %p1 = call float @llvm.amdgcn.lds.param.load(i32 0, i32 1, i32 %m0)
24  %p0_0 = call float @llvm.amdgcn.interp.inreg.p10(float %p0, float %i, float %p0)
25  %p1_0 = call float @llvm.amdgcn.interp.inreg.p2(float %p0, float %j, float %p0_0)
26  %p0_1 = call float @llvm.amdgcn.interp.inreg.p10(float %p1, float %i, float %p1)
27  %p1_1 = call float @llvm.amdgcn.interp.inreg.p2(float %p1, float %j, float %p1_0)
28  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %p0_0, float %p0_1, float %p1_0, float %p1_1, i1 true, i1 true) #0
29  ret void
30}
31
32define amdgpu_ps void @v_interp_f32_many(float inreg %i, float inreg %j, i32 inreg %m0) #0 {
33; GCN-LABEL: v_interp_f32_many:
34; GCN:       ; %bb.0: ; %main_body
35; GCN-NEXT:    s_mov_b32 s3, exec_lo
36; GCN-NEXT:    s_wqm_b32 exec_lo, exec_lo
37; GCN-NEXT:    s_mov_b32 m0, s2
38; GCN-NEXT:    lds_param_load v0, attr0.x wait_vdst:15
39; GCN-NEXT:    lds_param_load v1, attr1.x wait_vdst:15
40; GCN-NEXT:    lds_param_load v2, attr2.x wait_vdst:15
41; GCN-NEXT:    lds_param_load v3, attr3.x wait_vdst:15
42; GCN-NEXT:    s_mov_b32 exec_lo, s3
43; GCN-NEXT:    v_mov_b32_e32 v4, s0
44; GCN-NEXT:    v_mov_b32_e32 v5, s1
45; GCN-NEXT:    v_interp_p10_f32 v6, v0, v4, v0 wait_exp:3
46; GCN-NEXT:    v_interp_p10_f32 v7, v1, v4, v1 wait_exp:2
47; GCN-NEXT:    v_interp_p10_f32 v8, v2, v4, v2 wait_exp:1
48; GCN-NEXT:    v_interp_p10_f32 v4, v3, v4, v3
49; GCN-NEXT:    v_interp_p2_f32 v6, v0, v5, v6 wait_exp:7
50; GCN-NEXT:    v_interp_p2_f32 v7, v1, v5, v7 wait_exp:7
51; GCN-NEXT:    v_interp_p2_f32 v8, v2, v5, v8 wait_exp:7
52; GCN-NEXT:    v_interp_p2_f32 v4, v3, v5, v4 wait_exp:7
53; GCN-NEXT:    exp mrt0 v6, v7, v8, v4 done
54; GCN-NEXT:    s_endpgm
55main_body:
56  %p0 = call float @llvm.amdgcn.lds.param.load(i32 0, i32 0, i32 %m0)
57  %p1 = call float @llvm.amdgcn.lds.param.load(i32 0, i32 1, i32 %m0)
58  %p2 = call float @llvm.amdgcn.lds.param.load(i32 0, i32 2, i32 %m0)
59  %p3 = call float @llvm.amdgcn.lds.param.load(i32 0, i32 3, i32 %m0)
60  %p0_0 = call float @llvm.amdgcn.interp.inreg.p10(float %p0, float %i, float %p0)
61  %p0_1 = call float @llvm.amdgcn.interp.inreg.p2(float %p0, float %j, float %p0_0)
62  %p1_0 = call float @llvm.amdgcn.interp.inreg.p10(float %p1, float %i, float %p1)
63  %p1_1 = call float @llvm.amdgcn.interp.inreg.p2(float %p1, float %j, float %p1_0)
64  %p2_0 = call float @llvm.amdgcn.interp.inreg.p10(float %p2, float %i, float %p2)
65  %p2_1 = call float @llvm.amdgcn.interp.inreg.p2(float %p2, float %j, float %p2_0)
66  %p3_0 = call float @llvm.amdgcn.interp.inreg.p10(float %p3, float %i, float %p3)
67  %p3_1 = call float @llvm.amdgcn.interp.inreg.p2(float %p3, float %j, float %p3_0)
68  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %p0_1, float %p1_1, float %p2_1, float %p3_1, i1 true, i1 true) #0
69  ret void
70}
71
72define amdgpu_ps void @v_interp_f32_many_vm(float addrspace(1)* %ptr, i32 inreg %m0) #0 {
73; GCN-LABEL: v_interp_f32_many_vm:
74; GCN:       ; %bb.0: ; %main_body
75; GCN-NEXT:    global_load_b64 v[0:1], v[0:1], off offset:4
76; GCN-NEXT:    s_mov_b32 m0, s0
77; GCN-NEXT:    s_mov_b32 s0, exec_lo
78; GCN-NEXT:    s_wqm_b32 exec_lo, exec_lo
79; GCN-NEXT:    lds_param_load v2, attr0.x wait_vdst:15
80; GCN-NEXT:    lds_param_load v3, attr1.x wait_vdst:15
81; GCN-NEXT:    lds_param_load v4, attr2.x wait_vdst:15
82; GCN-NEXT:    lds_param_load v5, attr3.x wait_vdst:15
83; GCN-NEXT:    s_mov_b32 exec_lo, s0
84; GCN-NEXT:    s_waitcnt vmcnt(0)
85; GCN-NEXT:    v_interp_p10_f32 v6, v2, v0, v2 wait_exp:3
86; GCN-NEXT:    v_interp_p10_f32 v7, v3, v0, v3 wait_exp:2
87; GCN-NEXT:    v_interp_p10_f32 v8, v4, v0, v4 wait_exp:1
88; GCN-NEXT:    v_interp_p10_f32 v0, v5, v0, v5
89; GCN-NEXT:    v_interp_p2_f32 v6, v2, v1, v6 wait_exp:7
90; GCN-NEXT:    v_interp_p2_f32 v7, v3, v1, v7 wait_exp:7
91; GCN-NEXT:    v_interp_p2_f32 v8, v4, v1, v8 wait_exp:7
92; GCN-NEXT:    v_interp_p2_f32 v0, v5, v1, v0 wait_exp:7
93; GCN-NEXT:    exp mrt0 v6, v7, v8, v0 done
94; GCN-NEXT:    s_endpgm
95main_body:
96  %i.ptr = getelementptr float, float addrspace(1)* %ptr, i32 1
97  %i = load float, float addrspace(1)* %i.ptr, align 4
98  %j.ptr = getelementptr float, float addrspace(1)* %ptr, i32 2
99  %j = load float, float addrspace(1)* %j.ptr, align 4
100  %p0 = call float @llvm.amdgcn.lds.param.load(i32 0, i32 0, i32 %m0)
101  %p1 = call float @llvm.amdgcn.lds.param.load(i32 0, i32 1, i32 %m0)
102  %p2 = call float @llvm.amdgcn.lds.param.load(i32 0, i32 2, i32 %m0)
103  %p3 = call float @llvm.amdgcn.lds.param.load(i32 0, i32 3, i32 %m0)
104  %p0_0 = call float @llvm.amdgcn.interp.inreg.p10(float %p0, float %i, float %p0)
105  %p0_1 = call float @llvm.amdgcn.interp.inreg.p2(float %p0, float %j, float %p0_0)
106  %p1_0 = call float @llvm.amdgcn.interp.inreg.p10(float %p1, float %i, float %p1)
107  %p1_1 = call float @llvm.amdgcn.interp.inreg.p2(float %p1, float %j, float %p1_0)
108  %p2_0 = call float @llvm.amdgcn.interp.inreg.p10(float %p2, float %i, float %p2)
109  %p2_1 = call float @llvm.amdgcn.interp.inreg.p2(float %p2, float %j, float %p2_0)
110  %p3_0 = call float @llvm.amdgcn.interp.inreg.p10(float %p3, float %i, float %p3)
111  %p3_1 = call float @llvm.amdgcn.interp.inreg.p2(float %p3, float %j, float %p3_0)
112  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %p0_1, float %p1_1, float %p2_1, float %p3_1, i1 true, i1 true) #0
113  ret void
114}
115
116define amdgpu_ps half @v_interp_f16(float inreg %i, float inreg %j, i32 inreg %m0) #0 {
117; GCN-LABEL: v_interp_f16:
118; GCN:       ; %bb.0: ; %main_body
119; GCN-NEXT:    s_mov_b32 s3, exec_lo
120; GCN-NEXT:    s_wqm_b32 exec_lo, exec_lo
121; GCN-NEXT:    s_mov_b32 m0, s2
122; GCN-NEXT:    lds_param_load v1, attr0.x wait_vdst:15
123; GCN-NEXT:    s_mov_b32 exec_lo, s3
124; GCN-NEXT:    v_mov_b32_e32 v0, s0
125; GCN-NEXT:    v_mov_b32_e32 v2, s1
126; GCN-NEXT:    v_interp_p10_f16_f32 v3, v1, v0, v1
127; GCN-NEXT:    v_interp_p10_f16_f32 v0, v1, v0, v1 op_sel:[1,0,1,0] wait_exp:7
128; GCN-NEXT:    v_interp_p2_f16_f32 v3, v1, v2, v3 wait_exp:7
129; GCN-NEXT:    v_interp_p2_f16_f32 v0, v1, v2, v0 op_sel:[1,0,0,0] wait_exp:7
130; GCN-NEXT:    v_add_f16_e32 v0, v3, v0
131; GCN-NEXT:    ; return to shader part epilog
132main_body:
133  %p0 = call float @llvm.amdgcn.lds.param.load(i32 0, i32 0, i32 %m0)
134  %l_p0 = call float @llvm.amdgcn.interp.inreg.p10.f16(float %p0, float %i, float %p0, i1 0)
135  %l_p1 = call half @llvm.amdgcn.interp.inreg.p2.f16(float %p0, float %j, float %l_p0, i1 0)
136  %h_p0 = call float @llvm.amdgcn.interp.inreg.p10.f16(float %p0, float %i, float %p0, i1 1)
137  %h_p1 = call half @llvm.amdgcn.interp.inreg.p2.f16(float %p0, float %j, float %h_p0, i1 1)
138  %res = fadd half %l_p1, %h_p1
139  ret half %res
140}
141
142declare float @llvm.amdgcn.lds.param.load(i32, i32, i32) #1
143declare float @llvm.amdgcn.interp.inreg.p10(float, float, float) #0
144declare float @llvm.amdgcn.interp.inreg.p2(float, float, float) #0
145declare float @llvm.amdgcn.interp.inreg.p10.f16(float, float, float, i1) #0
146declare half @llvm.amdgcn.interp.inreg.p2.f16(float, float, float, i1) #0
147declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
148declare void @llvm.amdgcn.exp.f16(i32, i32, float, float, float, float, i1, i1) #0
149
150attributes #0 = { nounwind }
151attributes #1 = { nounwind readnone }
152