1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10 %s
3
4define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s) {
5; GFX10-LABEL: sample_d_1d:
6; GFX10:       ; %bb.0: ; %main_body
7; GFX10-NEXT:    image_sample_d_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
8; GFX10-NEXT:    ; implicit-def: $vcc_hi
9; GFX10-NEXT:    s_waitcnt vmcnt(0)
10; GFX10-NEXT:    ; return to shader part epilog
11main_body:
12  %v = call <4 x float> @llvm.amdgcn.image.sample.d.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
13  ret <4 x float> %v
14}
15
16define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) {
17; GFX10-LABEL: sample_d_2d:
18; GFX10:       ; %bb.0: ; %main_body
19; GFX10-NEXT:    v_mov_b32_e32 v7, 0xffff
20; GFX10-NEXT:    ; implicit-def: $vcc_hi
21; GFX10-NEXT:    v_and_b32_e32 v2, v7, v2
22; GFX10-NEXT:    v_and_b32_e32 v0, v7, v0
23; GFX10-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
24; GFX10-NEXT:    v_lshl_or_b32 v3, v1, 16, v0
25; GFX10-NEXT:    image_sample_d_g16 v[0:3], [v3, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
26; GFX10-NEXT:    s_waitcnt vmcnt(0)
27; GFX10-NEXT:    ; return to shader part epilog
28main_body:
29  %v = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
30  ret <4 x float> %v
31}
32
33define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %drdh, half %dsdv, half %dtdv, half %drdv, float %s, float %t, float %r) {
34; GFX10-LABEL: sample_d_3d:
35; GFX10:       ; %bb.0: ; %main_body
36; GFX10-NEXT:    v_mov_b32_e32 v9, 0xffff
37; GFX10-NEXT:    ; implicit-def: $vcc_hi
38; GFX10-NEXT:    v_and_b32_e32 v3, v9, v3
39; GFX10-NEXT:    v_and_b32_e32 v0, v9, v0
40; GFX10-NEXT:    v_lshl_or_b32 v3, v4, 16, v3
41; GFX10-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
42; GFX10-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v3, v5, v6, v7, v8], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
43; GFX10-NEXT:    s_waitcnt vmcnt(0)
44; GFX10-NEXT:    ; return to shader part epilog
45main_body:
46  %v = call <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %drdh, half %dsdv, half %dtdv, half %drdv, float %s, float %t, float %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
47  ret <4 x float> %v
48}
49
50define amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s) {
51; GFX10-LABEL: sample_c_d_1d:
52; GFX10:       ; %bb.0: ; %main_body
53; GFX10-NEXT:    image_sample_c_d_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
54; GFX10-NEXT:    ; implicit-def: $vcc_hi
55; GFX10-NEXT:    s_waitcnt vmcnt(0)
56; GFX10-NEXT:    ; return to shader part epilog
57main_body:
58  %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
59  ret <4 x float> %v
60}
61
62define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) {
63; GFX10-LABEL: sample_c_d_2d:
64; GFX10:       ; %bb.0: ; %main_body
65; GFX10-NEXT:    v_mov_b32_e32 v10, 0xffff
66; GFX10-NEXT:    ; implicit-def: $vcc_hi
67; GFX10-NEXT:    v_and_b32_e32 v3, v10, v3
68; GFX10-NEXT:    v_and_b32_e32 v1, v10, v1
69; GFX10-NEXT:    v_lshl_or_b32 v3, v4, 16, v3
70; GFX10-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
71; GFX10-NEXT:    image_sample_c_d_g16 v[0:3], [v0, v1, v3, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
72; GFX10-NEXT:    s_waitcnt vmcnt(0)
73; GFX10-NEXT:    ; return to shader part epilog
74main_body:
75  %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
76  ret <4 x float> %v
77}
78
79define amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s, float %clamp) {
80; GFX10-LABEL: sample_d_cl_1d:
81; GFX10:       ; %bb.0: ; %main_body
82; GFX10-NEXT:    image_sample_d_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
83; GFX10-NEXT:    ; implicit-def: $vcc_hi
84; GFX10-NEXT:    s_waitcnt vmcnt(0)
85; GFX10-NEXT:    ; return to shader part epilog
86main_body:
87  %v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
88  ret <4 x float> %v
89}
90
91define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) {
92; GFX10-LABEL: sample_d_cl_2d:
93; GFX10:       ; %bb.0: ; %main_body
94; GFX10-NEXT:    v_mov_b32_e32 v7, 0xffff
95; GFX10-NEXT:    ; implicit-def: $vcc_hi
96; GFX10-NEXT:    v_and_b32_e32 v0, v7, v0
97; GFX10-NEXT:    v_and_b32_e32 v2, v7, v2
98; GFX10-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
99; GFX10-NEXT:    v_lshl_or_b32 v3, v3, 16, v2
100; GFX10-NEXT:    image_sample_d_cl_g16 v[0:3], [v0, v3, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
101; GFX10-NEXT:    s_waitcnt vmcnt(0)
102; GFX10-NEXT:    ; return to shader part epilog
103main_body:
104  %v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
105  ret <4 x float> %v
106}
107
108define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp) {
109; GFX10-LABEL: sample_c_d_cl_1d:
110; GFX10:       ; %bb.0: ; %main_body
111; GFX10-NEXT:    image_sample_c_d_cl_g16 v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
112; GFX10-NEXT:    ; implicit-def: $vcc_hi
113; GFX10-NEXT:    s_waitcnt vmcnt(0)
114; GFX10-NEXT:    ; return to shader part epilog
115main_body:
116  %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
117  ret <4 x float> %v
118}
119
120define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) {
121; GFX10-LABEL: sample_c_d_cl_2d:
122; GFX10:       ; %bb.0: ; %main_body
123; GFX10-NEXT:    v_mov_b32_e32 v8, 0xffff
124; GFX10-NEXT:    ; implicit-def: $vcc_hi
125; GFX10-NEXT:    v_and_b32_e32 v3, v8, v3
126; GFX10-NEXT:    v_and_b32_e32 v1, v8, v1
127; GFX10-NEXT:    v_lshl_or_b32 v3, v4, 16, v3
128; GFX10-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
129; GFX10-NEXT:    image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v5, v6, v7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
130; GFX10-NEXT:    s_waitcnt vmcnt(0)
131; GFX10-NEXT:    ; return to shader part epilog
132main_body:
133  %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
134  ret <4 x float> %v
135}
136
137define amdgpu_ps <4 x float> @sample_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s) {
138; GFX10-LABEL: sample_cd_1d:
139; GFX10:       ; %bb.0: ; %main_body
140; GFX10-NEXT:    image_sample_cd_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
141; GFX10-NEXT:    ; implicit-def: $vcc_hi
142; GFX10-NEXT:    s_waitcnt vmcnt(0)
143; GFX10-NEXT:    ; return to shader part epilog
144main_body:
145  %v = call <4 x float> @llvm.amdgcn.image.sample.cd.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
146  ret <4 x float> %v
147}
148
149define amdgpu_ps <4 x float> @sample_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) {
150; GFX10-LABEL: sample_cd_2d:
151; GFX10:       ; %bb.0: ; %main_body
152; GFX10-NEXT:    v_mov_b32_e32 v7, 0xffff
153; GFX10-NEXT:    ; implicit-def: $vcc_hi
154; GFX10-NEXT:    v_and_b32_e32 v2, v7, v2
155; GFX10-NEXT:    v_and_b32_e32 v0, v7, v0
156; GFX10-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
157; GFX10-NEXT:    v_lshl_or_b32 v3, v1, 16, v0
158; GFX10-NEXT:    image_sample_cd_g16 v[0:3], [v3, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
159; GFX10-NEXT:    s_waitcnt vmcnt(0)
160; GFX10-NEXT:    ; return to shader part epilog
161main_body:
162  %v = call <4 x float> @llvm.amdgcn.image.sample.cd.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
163  ret <4 x float> %v
164}
165
166define amdgpu_ps <4 x float> @sample_c_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s) {
167; GFX10-LABEL: sample_c_cd_1d:
168; GFX10:       ; %bb.0: ; %main_body
169; GFX10-NEXT:    image_sample_c_cd_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
170; GFX10-NEXT:    ; implicit-def: $vcc_hi
171; GFX10-NEXT:    s_waitcnt vmcnt(0)
172; GFX10-NEXT:    ; return to shader part epilog
173main_body:
174  %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
175  ret <4 x float> %v
176}
177
178define amdgpu_ps <4 x float> @sample_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) {
179; GFX10-LABEL: sample_c_cd_2d:
180; GFX10:       ; %bb.0: ; %main_body
181; GFX10-NEXT:    v_mov_b32_e32 v10, 0xffff
182; GFX10-NEXT:    ; implicit-def: $vcc_hi
183; GFX10-NEXT:    v_and_b32_e32 v3, v10, v3
184; GFX10-NEXT:    v_and_b32_e32 v1, v10, v1
185; GFX10-NEXT:    v_lshl_or_b32 v3, v4, 16, v3
186; GFX10-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
187; GFX10-NEXT:    image_sample_c_cd_g16 v[0:3], [v0, v1, v3, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
188; GFX10-NEXT:    s_waitcnt vmcnt(0)
189; GFX10-NEXT:    ; return to shader part epilog
190main_body:
191  %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
192  ret <4 x float> %v
193}
194
195define amdgpu_ps <4 x float> @sample_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s, float %clamp) {
196; GFX10-LABEL: sample_cd_cl_1d:
197; GFX10:       ; %bb.0: ; %main_body
198; GFX10-NEXT:    image_sample_cd_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
199; GFX10-NEXT:    ; implicit-def: $vcc_hi
200; GFX10-NEXT:    s_waitcnt vmcnt(0)
201; GFX10-NEXT:    ; return to shader part epilog
202main_body:
203  %v = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
204  ret <4 x float> %v
205}
206
207define amdgpu_ps <4 x float> @sample_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) {
208; GFX10-LABEL: sample_cd_cl_2d:
209; GFX10:       ; %bb.0: ; %main_body
210; GFX10-NEXT:    v_mov_b32_e32 v7, 0xffff
211; GFX10-NEXT:    ; implicit-def: $vcc_hi
212; GFX10-NEXT:    v_and_b32_e32 v0, v7, v0
213; GFX10-NEXT:    v_and_b32_e32 v2, v7, v2
214; GFX10-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
215; GFX10-NEXT:    v_lshl_or_b32 v3, v3, 16, v2
216; GFX10-NEXT:    image_sample_cd_cl_g16 v[0:3], [v0, v3, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
217; GFX10-NEXT:    s_waitcnt vmcnt(0)
218; GFX10-NEXT:    ; return to shader part epilog
219main_body:
220  %v = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
221  ret <4 x float> %v
222}
223
224define amdgpu_ps <4 x float> @sample_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp) {
225; GFX10-LABEL: sample_c_cd_cl_1d:
226; GFX10:       ; %bb.0: ; %main_body
227; GFX10-NEXT:    image_sample_c_cd_cl_g16 v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
228; GFX10-NEXT:    ; implicit-def: $vcc_hi
229; GFX10-NEXT:    s_waitcnt vmcnt(0)
230; GFX10-NEXT:    ; return to shader part epilog
231main_body:
232  %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
233  ret <4 x float> %v
234}
235
236define amdgpu_ps <4 x float> @sample_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) {
237; GFX10-LABEL: sample_c_cd_cl_2d:
238; GFX10:       ; %bb.0: ; %main_body
239; GFX10-NEXT:    v_mov_b32_e32 v8, 0xffff
240; GFX10-NEXT:    ; implicit-def: $vcc_hi
241; GFX10-NEXT:    v_and_b32_e32 v3, v8, v3
242; GFX10-NEXT:    v_and_b32_e32 v1, v8, v1
243; GFX10-NEXT:    v_lshl_or_b32 v3, v4, 16, v3
244; GFX10-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
245; GFX10-NEXT:    image_sample_c_cd_cl_g16 v[0:3], [v0, v1, v3, v5, v6, v7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
246; GFX10-NEXT:    s_waitcnt vmcnt(0)
247; GFX10-NEXT:    ; return to shader part epilog
248main_body:
249  %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
250  ret <4 x float> %v
251}
252
253define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice) {
254; GFX10-LABEL: sample_c_d_o_2darray_V1:
255; GFX10:       ; %bb.0: ; %main_body
256; GFX10-NEXT:    v_mov_b32_e32 v9, 0xffff
257; GFX10-NEXT:    ; implicit-def: $vcc_hi
258; GFX10-NEXT:    v_and_b32_e32 v4, v9, v4
259; GFX10-NEXT:    v_and_b32_e32 v2, v9, v2
260; GFX10-NEXT:    v_lshl_or_b32 v4, v5, 16, v4
261; GFX10-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
262; GFX10-NEXT:    image_sample_c_d_o_g16 v0, [v0, v1, v2, v4, v6, v7, v8], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
263; GFX10-NEXT:    s_waitcnt vmcnt(0)
264; GFX10-NEXT:    ; return to shader part epilog
265main_body:
266  %v = call float @llvm.amdgcn.image.sample.c.d.o.2darray.f16.f32.f32(i32 4, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
267  ret float %v
268}
269
270define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice) {
271; GFX10-LABEL: sample_c_d_o_2darray_V2:
272; GFX10:       ; %bb.0: ; %main_body
273; GFX10-NEXT:    v_mov_b32_e32 v9, 0xffff
274; GFX10-NEXT:    ; implicit-def: $vcc_hi
275; GFX10-NEXT:    v_and_b32_e32 v4, v9, v4
276; GFX10-NEXT:    v_and_b32_e32 v2, v9, v2
277; GFX10-NEXT:    v_lshl_or_b32 v4, v5, 16, v4
278; GFX10-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
279; GFX10-NEXT:    image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v4, v6, v7, v8], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY
280; GFX10-NEXT:    s_waitcnt vmcnt(0)
281; GFX10-NEXT:    ; return to shader part epilog
282main_body:
283  %v = call <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f16.f32(i32 6, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
284  ret <2 x float> %v
285}
286
287declare <4 x float> @llvm.amdgcn.image.sample.d.1d.v4f32.f16.f32(i32, half, half, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
288declare <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f16.f32(i32, half, half, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
289declare <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f16.f32(i32, half, half, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
290declare <4 x float> @llvm.amdgcn.image.sample.c.d.1d.v4f32.f16.f32(i32, float, half, half, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
291declare <4 x float> @llvm.amdgcn.image.sample.c.d.2d.v4f32.f16.f32(i32, float, half, half, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
292declare <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f16.f32(i32, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
293declare <4 x float> @llvm.amdgcn.image.sample.d.cl.2d.v4f32.f16.f32(i32, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
294declare <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f16.f32(i32, float, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
295declare <4 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v4f32.f16.f32(i32, float, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
296
297declare <4 x float> @llvm.amdgcn.image.sample.cd.1d.v4f32.f16.f32(i32, half, half, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
298declare <4 x float> @llvm.amdgcn.image.sample.cd.2d.v4f32.f16.f32(i32, half, half, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
299declare <4 x float> @llvm.amdgcn.image.sample.c.cd.1d.v4f32.f16.f32(i32, float, half, half, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
300declare <4 x float> @llvm.amdgcn.image.sample.c.cd.2d.v4f32.f16.f32(i32, float, half, half, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
301declare <4 x float> @llvm.amdgcn.image.sample.cd.cl.1d.v4f32.f16.f32(i32, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
302declare <4 x float> @llvm.amdgcn.image.sample.cd.cl.2d.v4f32.f16.f32(i32, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
303declare <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.1d.v4f32.f16.f32(i32, float, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
304declare <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.2d.v4f32.f16.f32(i32, float, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
305
306declare float @llvm.amdgcn.image.sample.c.d.o.2darray.f16.f32.f32(i32, i32, float, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
307declare <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f16.f32(i32, i32, float, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
308
309attributes #0 = { nounwind }
310attributes #1 = { nounwind readonly }
311attributes #2 = { nounwind readnone }
312