1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10 %s 3 4define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s) { 5; GFX10-LABEL: sample_d_1d: 6; GFX10: ; %bb.0: ; %main_body 7; GFX10-NEXT: image_sample_d_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D 8; GFX10-NEXT: s_waitcnt vmcnt(0) 9; GFX10-NEXT: ; return to shader part epilog 10main_body: 11 %v = call <4 x float> @llvm.amdgcn.image.sample.d.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 12 ret <4 x float> %v 13} 14 15define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) { 16; GFX10-LABEL: sample_d_2d: 17; GFX10: ; %bb.0: ; %main_body 18; GFX10-NEXT: v_and_b32_e32 v2, 0xffff, v2 19; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0 20; GFX10-NEXT: v_lshl_or_b32 v2, v3, 16, v2 21; GFX10-NEXT: v_lshl_or_b32 v0, v1, 16, v0 22; GFX10-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D 23; GFX10-NEXT: s_waitcnt vmcnt(0) 24; GFX10-NEXT: ; return to shader part epilog 25main_body: 26 %v = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 27 ret <4 x float> %v 28} 29 30define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %drdh, half %dsdv, half %dtdv, half %drdv, float %s, float %t, float %r) { 31; GFX10-LABEL: sample_d_3d: 32; GFX10: ; %bb.0: ; %main_body 33; GFX10-NEXT: v_mov_b32_e32 v9, v3 34; GFX10-NEXT: v_mov_b32_e32 v3, v2 35; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0 36; GFX10-NEXT: v_and_b32_e32 v2, 0xffff, v9 37; GFX10-NEXT: v_lshl_or_b32 v4, v4, 16, v2 38; GFX10-NEXT: v_lshl_or_b32 v2, v1, 16, v0 39; GFX10-NEXT: image_sample_d_g16 v[0:3], v[2:8], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D 40; GFX10-NEXT: s_waitcnt vmcnt(0) 41; GFX10-NEXT: ; return to shader part epilog 42main_body: 43 %v = call <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %drdh, half %dsdv, half %dtdv, half %drdv, float %s, float %t, float %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 44 ret <4 x float> %v 45} 46 47define amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s) { 48; GFX10-LABEL: sample_c_d_1d: 49; GFX10: ; %bb.0: ; %main_body 50; GFX10-NEXT: image_sample_c_d_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D 51; GFX10-NEXT: s_waitcnt vmcnt(0) 52; GFX10-NEXT: ; return to shader part epilog 53main_body: 54 %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 55 ret <4 x float> %v 56} 57 58define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) { 59; GFX10-LABEL: sample_c_d_2d: 60; GFX10: ; %bb.0: ; %main_body 61; GFX10-NEXT: v_and_b32_e32 v3, 0xffff, v3 62; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1 63; GFX10-NEXT: v_lshl_or_b32 v3, v4, 16, v3 64; GFX10-NEXT: v_lshl_or_b32 v1, v2, 16, v1 65; GFX10-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v3, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D 66; GFX10-NEXT: s_waitcnt vmcnt(0) 67; GFX10-NEXT: ; return to shader part epilog 68main_body: 69 %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 70 ret <4 x float> %v 71} 72 73define amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s, float %clamp) { 74; GFX10-LABEL: sample_d_cl_1d: 75; GFX10: ; %bb.0: ; %main_body 76; GFX10-NEXT: image_sample_d_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D 77; GFX10-NEXT: s_waitcnt vmcnt(0) 78; GFX10-NEXT: ; return to shader part epilog 79main_body: 80 %v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 81 ret <4 x float> %v 82} 83 84define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) { 85; GFX10-LABEL: sample_d_cl_2d: 86; GFX10: ; %bb.0: ; %main_body 87; GFX10-NEXT: v_and_b32_e32 v2, 0xffff, v2 88; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0 89; GFX10-NEXT: v_lshl_or_b32 v2, v3, 16, v2 90; GFX10-NEXT: v_lshl_or_b32 v0, v1, 16, v0 91; GFX10-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D 92; GFX10-NEXT: s_waitcnt vmcnt(0) 93; GFX10-NEXT: ; return to shader part epilog 94main_body: 95 %v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 96 ret <4 x float> %v 97} 98 99define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp) { 100; GFX10-LABEL: sample_c_d_cl_1d: 101; GFX10: ; %bb.0: ; %main_body 102; GFX10-NEXT: image_sample_c_d_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D 103; GFX10-NEXT: s_waitcnt vmcnt(0) 104; GFX10-NEXT: ; return to shader part epilog 105main_body: 106 %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 107 ret <4 x float> %v 108} 109 110define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) { 111; GFX10-LABEL: sample_c_d_cl_2d: 112; GFX10: ; %bb.0: ; %main_body 113; GFX10-NEXT: v_mov_b32_e32 v8, v2 114; GFX10-NEXT: v_mov_b32_e32 v2, v0 115; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v3 116; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1 117; GFX10-NEXT: v_lshl_or_b32 v4, v4, 16, v0 118; GFX10-NEXT: v_lshl_or_b32 v3, v8, 16, v1 119; GFX10-NEXT: image_sample_c_d_cl_g16 v[0:3], v[2:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D 120; GFX10-NEXT: s_waitcnt vmcnt(0) 121; GFX10-NEXT: ; return to shader part epilog 122main_body: 123 %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 124 ret <4 x float> %v 125} 126 127define amdgpu_ps <4 x float> @sample_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s) { 128; GFX10-LABEL: sample_cd_1d: 129; GFX10: ; %bb.0: ; %main_body 130; GFX10-NEXT: image_sample_cd_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D 131; GFX10-NEXT: s_waitcnt vmcnt(0) 132; GFX10-NEXT: ; return to shader part epilog 133main_body: 134 %v = call <4 x float> @llvm.amdgcn.image.sample.cd.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 135 ret <4 x float> %v 136} 137 138define amdgpu_ps <4 x float> @sample_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) { 139; GFX10-LABEL: sample_cd_2d: 140; GFX10: ; %bb.0: ; %main_body 141; GFX10-NEXT: v_and_b32_e32 v2, 0xffff, v2 142; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0 143; GFX10-NEXT: v_lshl_or_b32 v2, v3, 16, v2 144; GFX10-NEXT: v_lshl_or_b32 v0, v1, 16, v0 145; GFX10-NEXT: image_sample_cd_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D 146; GFX10-NEXT: s_waitcnt vmcnt(0) 147; GFX10-NEXT: ; return to shader part epilog 148main_body: 149 %v = call <4 x float> @llvm.amdgcn.image.sample.cd.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 150 ret <4 x float> %v 151} 152 153define amdgpu_ps <4 x float> @sample_c_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s) { 154; GFX10-LABEL: sample_c_cd_1d: 155; GFX10: ; %bb.0: ; %main_body 156; GFX10-NEXT: image_sample_c_cd_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D 157; GFX10-NEXT: s_waitcnt vmcnt(0) 158; GFX10-NEXT: ; return to shader part epilog 159main_body: 160 %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 161 ret <4 x float> %v 162} 163 164define amdgpu_ps <4 x float> @sample_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) { 165; GFX10-LABEL: sample_c_cd_2d: 166; GFX10: ; %bb.0: ; %main_body 167; GFX10-NEXT: v_and_b32_e32 v3, 0xffff, v3 168; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1 169; GFX10-NEXT: v_lshl_or_b32 v3, v4, 16, v3 170; GFX10-NEXT: v_lshl_or_b32 v1, v2, 16, v1 171; GFX10-NEXT: image_sample_c_cd_g16 v[0:3], [v0, v1, v3, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D 172; GFX10-NEXT: s_waitcnt vmcnt(0) 173; GFX10-NEXT: ; return to shader part epilog 174main_body: 175 %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 176 ret <4 x float> %v 177} 178 179define amdgpu_ps <4 x float> @sample_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s, float %clamp) { 180; GFX10-LABEL: sample_cd_cl_1d: 181; GFX10: ; %bb.0: ; %main_body 182; GFX10-NEXT: image_sample_cd_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D 183; GFX10-NEXT: s_waitcnt vmcnt(0) 184; GFX10-NEXT: ; return to shader part epilog 185main_body: 186 %v = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 187 ret <4 x float> %v 188} 189 190define amdgpu_ps <4 x float> @sample_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) { 191; GFX10-LABEL: sample_cd_cl_2d: 192; GFX10: ; %bb.0: ; %main_body 193; GFX10-NEXT: v_and_b32_e32 v2, 0xffff, v2 194; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0 195; GFX10-NEXT: v_lshl_or_b32 v2, v3, 16, v2 196; GFX10-NEXT: v_lshl_or_b32 v0, v1, 16, v0 197; GFX10-NEXT: image_sample_cd_cl_g16 v[0:3], [v0, v2, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D 198; GFX10-NEXT: s_waitcnt vmcnt(0) 199; GFX10-NEXT: ; return to shader part epilog 200main_body: 201 %v = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 202 ret <4 x float> %v 203} 204 205define amdgpu_ps <4 x float> @sample_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp) { 206; GFX10-LABEL: sample_c_cd_cl_1d: 207; GFX10: ; %bb.0: ; %main_body 208; GFX10-NEXT: image_sample_c_cd_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D 209; GFX10-NEXT: s_waitcnt vmcnt(0) 210; GFX10-NEXT: ; return to shader part epilog 211main_body: 212 %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 213 ret <4 x float> %v 214} 215 216define amdgpu_ps <4 x float> @sample_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) { 217; GFX10-LABEL: sample_c_cd_cl_2d: 218; GFX10: ; %bb.0: ; %main_body 219; GFX10-NEXT: v_mov_b32_e32 v8, v2 220; GFX10-NEXT: v_mov_b32_e32 v2, v0 221; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v3 222; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1 223; GFX10-NEXT: v_lshl_or_b32 v4, v4, 16, v0 224; GFX10-NEXT: v_lshl_or_b32 v3, v8, 16, v1 225; GFX10-NEXT: image_sample_c_cd_cl_g16 v[0:3], v[2:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D 226; GFX10-NEXT: s_waitcnt vmcnt(0) 227; GFX10-NEXT: ; return to shader part epilog 228main_body: 229 %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 230 ret <4 x float> %v 231} 232 233define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice) { 234; GFX10-LABEL: sample_c_d_o_2darray_V1: 235; GFX10: ; %bb.0: ; %main_body 236; GFX10-NEXT: v_mov_b32_e32 v9, v2 237; GFX10-NEXT: v_mov_b32_e32 v10, v3 238; GFX10-NEXT: v_mov_b32_e32 v3, v1 239; GFX10-NEXT: v_mov_b32_e32 v2, v0 240; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v4 241; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v9 242; GFX10-NEXT: v_lshl_or_b32 v5, v5, 16, v0 243; GFX10-NEXT: v_lshl_or_b32 v4, v10, 16, v1 244; GFX10-NEXT: image_sample_c_d_o_g16 v0, v[2:8], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY 245; GFX10-NEXT: s_waitcnt vmcnt(0) 246; GFX10-NEXT: ; return to shader part epilog 247main_body: 248 %v = call float @llvm.amdgcn.image.sample.c.d.o.2darray.f16.f32.f32(i32 4, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 249 ret float %v 250} 251 252define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice) { 253; GFX10-LABEL: sample_c_d_o_2darray_V2: 254; GFX10: ; %bb.0: ; %main_body 255; GFX10-NEXT: v_mov_b32_e32 v9, v2 256; GFX10-NEXT: v_mov_b32_e32 v10, v3 257; GFX10-NEXT: v_mov_b32_e32 v3, v1 258; GFX10-NEXT: v_mov_b32_e32 v2, v0 259; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v4 260; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v9 261; GFX10-NEXT: v_lshl_or_b32 v5, v5, 16, v0 262; GFX10-NEXT: v_lshl_or_b32 v4, v10, 16, v1 263; GFX10-NEXT: image_sample_c_d_o_g16 v[0:1], v[2:8], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY 264; GFX10-NEXT: s_waitcnt vmcnt(0) 265; GFX10-NEXT: ; return to shader part epilog 266main_body: 267 %v = call <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f16.f32(i32 6, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 268 ret <2 x float> %v 269} 270 271declare <4 x float> @llvm.amdgcn.image.sample.d.1d.v4f32.f16.f32(i32, half, half, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 272declare <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f16.f32(i32, half, half, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 273declare <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f16.f32(i32, half, half, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 274declare <4 x float> @llvm.amdgcn.image.sample.c.d.1d.v4f32.f16.f32(i32, float, half, half, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 275declare <4 x float> @llvm.amdgcn.image.sample.c.d.2d.v4f32.f16.f32(i32, float, half, half, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 276declare <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f16.f32(i32, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 277declare <4 x float> @llvm.amdgcn.image.sample.d.cl.2d.v4f32.f16.f32(i32, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 278declare <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f16.f32(i32, float, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 279declare <4 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v4f32.f16.f32(i32, float, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 280 281declare <4 x float> @llvm.amdgcn.image.sample.cd.1d.v4f32.f16.f32(i32, half, half, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 282declare <4 x float> @llvm.amdgcn.image.sample.cd.2d.v4f32.f16.f32(i32, half, half, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 283declare <4 x float> @llvm.amdgcn.image.sample.c.cd.1d.v4f32.f16.f32(i32, float, half, half, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 284declare <4 x float> @llvm.amdgcn.image.sample.c.cd.2d.v4f32.f16.f32(i32, float, half, half, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 285declare <4 x float> @llvm.amdgcn.image.sample.cd.cl.1d.v4f32.f16.f32(i32, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 286declare <4 x float> @llvm.amdgcn.image.sample.cd.cl.2d.v4f32.f16.f32(i32, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 287declare <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.1d.v4f32.f16.f32(i32, float, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 288declare <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.2d.v4f32.f16.f32(i32, float, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 289 290declare float @llvm.amdgcn.image.sample.c.d.o.2darray.f16.f32.f32(i32, i32, float, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 291declare <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f16.f32(i32, i32, float, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 292 293attributes #0 = { nounwind } 294attributes #1 = { nounwind readonly } 295attributes #2 = { nounwind readnone } 296