1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10 %s
3; RUN: llc -march=amdgcn -mcpu=gfx1010 -global-isel -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10GISEL %s
4; TODO: global-isel produces more code - there will need to be some more combines in the postregbankselectcombine phase
5; Depends on some other changes to pass this test - those are in review separately
6
7define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dsdv, half %s) {
8; GFX10-LABEL: sample_d_1d:
9; GFX10:       ; %bb.0: ; %main_body
10; GFX10-NEXT:    image_sample_d v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
11; GFX10-NEXT:    s_waitcnt vmcnt(0)
12; GFX10-NEXT:    ; return to shader part epilog
13;
14; GFX10GISEL-LABEL: sample_d_1d:
15; GFX10GISEL:       ; %bb.0: ; %main_body
16; GFX10GISEL-NEXT:    s_lshl_b32 s12, s0, 16
17; GFX10GISEL-NEXT:    v_and_or_b32 v2, 0xffff, v2, s12
18; GFX10GISEL-NEXT:    image_sample_d v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
19; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
20; GFX10GISEL-NEXT:    ; return to shader part epilog
21main_body:
22  %v = call <4 x float> @llvm.amdgcn.image.sample.d.1d.v4f32.f32.f16(i32 15, float %dsdh, float %dsdv, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
23  ret <4 x float> %v
24}
25
26define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t) {
27; GFX10-LABEL: sample_d_2d:
28; GFX10:       ; %bb.0: ; %main_body
29; GFX10-NEXT:    v_and_b32_e32 v4, 0xffff, v4
30; GFX10-NEXT:    v_lshl_or_b32 v4, v5, 16, v4
31; GFX10-NEXT:    image_sample_d v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
32; GFX10-NEXT:    s_waitcnt vmcnt(0)
33; GFX10-NEXT:    ; return to shader part epilog
34;
35; GFX10GISEL-LABEL: sample_d_2d:
36; GFX10GISEL:       ; %bb.0: ; %main_body
37; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
38; GFX10GISEL-NEXT:    v_and_or_b32 v4, 0xffff, v4, v5
39; GFX10GISEL-NEXT:    image_sample_d v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
40; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
41; GFX10GISEL-NEXT:    ; return to shader part epilog
42main_body:
43  %v = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32.f16(i32 15, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
44  ret <4 x float> %v
45}
46
47define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dtdh, float %drdh, float %dsdv, float %dtdv, float %drdv, half %s, half %t, half %r) {
48; GFX10-LABEL: sample_d_3d:
49; GFX10:       ; %bb.0: ; %main_body
50; GFX10-NEXT:    v_mov_b32_e32 v15, v8
51; GFX10-NEXT:    v_mov_b32_e32 v8, v0
52; GFX10-NEXT:    v_and_b32_e32 v0, 0xffff, v6
53; GFX10-NEXT:    v_mov_b32_e32 v13, v5
54; GFX10-NEXT:    v_mov_b32_e32 v12, v4
55; GFX10-NEXT:    v_mov_b32_e32 v11, v3
56; GFX10-NEXT:    v_mov_b32_e32 v10, v2
57; GFX10-NEXT:    v_mov_b32_e32 v9, v1
58; GFX10-NEXT:    v_lshl_or_b32 v14, v7, 16, v0
59; GFX10-NEXT:    image_sample_d v[0:3], v[8:15], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16
60; GFX10-NEXT:    s_waitcnt vmcnt(0)
61; GFX10-NEXT:    ; return to shader part epilog
62;
63; GFX10GISEL-LABEL: sample_d_3d:
64; GFX10GISEL:       ; %bb.0: ; %main_body
65; GFX10GISEL-NEXT:    v_mov_b32_e32 v9, 0xffff
66; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
67; GFX10GISEL-NEXT:    s_lshl_b32 s12, s0, 16
68; GFX10GISEL-NEXT:    v_and_or_b32 v6, v6, v9, v7
69; GFX10GISEL-NEXT:    v_and_or_b32 v7, v8, v9, s12
70; GFX10GISEL-NEXT:    image_sample_d v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16
71; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
72; GFX10GISEL-NEXT:    ; return to shader part epilog
73main_body:
74  %v = call <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f32.f16(i32 15, float %dsdh, float %dtdh, float %drdh, float %dsdv, float %dtdv, float %drdv, half %s, half %t, half %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
75  ret <4 x float> %v
76}
77
78define amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dsdv, half %s) {
79; GFX10-LABEL: sample_c_d_1d:
80; GFX10:       ; %bb.0: ; %main_body
81; GFX10-NEXT:    image_sample_c_d v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
82; GFX10-NEXT:    s_waitcnt vmcnt(0)
83; GFX10-NEXT:    ; return to shader part epilog
84;
85; GFX10GISEL-LABEL: sample_c_d_1d:
86; GFX10GISEL:       ; %bb.0: ; %main_body
87; GFX10GISEL-NEXT:    s_lshl_b32 s12, s0, 16
88; GFX10GISEL-NEXT:    v_and_or_b32 v3, 0xffff, v3, s12
89; GFX10GISEL-NEXT:    image_sample_c_d v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
90; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
91; GFX10GISEL-NEXT:    ; return to shader part epilog
92main_body:
93  %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.1d.v4f32.f32.f16(i32 15, float %zcompare, float %dsdh, float %dsdv, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
94  ret <4 x float> %v
95}
96
97define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t) {
98; GFX10-LABEL: sample_c_d_2d:
99; GFX10:       ; %bb.0: ; %main_body
100; GFX10-NEXT:    v_and_b32_e32 v5, 0xffff, v5
101; GFX10-NEXT:    v_lshl_or_b32 v5, v6, 16, v5
102; GFX10-NEXT:    image_sample_c_d v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
103; GFX10-NEXT:    s_waitcnt vmcnt(0)
104; GFX10-NEXT:    ; return to shader part epilog
105;
106; GFX10GISEL-LABEL: sample_c_d_2d:
107; GFX10GISEL:       ; %bb.0: ; %main_body
108; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
109; GFX10GISEL-NEXT:    v_and_or_b32 v5, 0xffff, v5, v6
110; GFX10GISEL-NEXT:    image_sample_c_d v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
111; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
112; GFX10GISEL-NEXT:    ; return to shader part epilog
113main_body:
114  %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.2d.v4f32.f32.f16(i32 15, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
115  ret <4 x float> %v
116}
117
118define amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dsdv, half %s, half %clamp) {
119; GFX10-LABEL: sample_d_cl_1d:
120; GFX10:       ; %bb.0: ; %main_body
121; GFX10-NEXT:    v_and_b32_e32 v2, 0xffff, v2
122; GFX10-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
123; GFX10-NEXT:    image_sample_d_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
124; GFX10-NEXT:    s_waitcnt vmcnt(0)
125; GFX10-NEXT:    ; return to shader part epilog
126;
127; GFX10GISEL-LABEL: sample_d_cl_1d:
128; GFX10GISEL:       ; %bb.0: ; %main_body
129; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
130; GFX10GISEL-NEXT:    v_and_or_b32 v2, 0xffff, v2, v3
131; GFX10GISEL-NEXT:    image_sample_d_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
132; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
133; GFX10GISEL-NEXT:    ; return to shader part epilog
134main_body:
135  %v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f32.f16(i32 15, float %dsdh, float %dsdv, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
136  ret <4 x float> %v
137}
138
139define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %clamp) {
140; GFX10-LABEL: sample_d_cl_2d:
141; GFX10:       ; %bb.0: ; %main_body
142; GFX10-NEXT:    v_mov_b32_e32 v11, v6
143; GFX10-NEXT:    v_mov_b32_e32 v6, v0
144; GFX10-NEXT:    v_and_b32_e32 v0, 0xffff, v4
145; GFX10-NEXT:    v_mov_b32_e32 v9, v3
146; GFX10-NEXT:    v_mov_b32_e32 v8, v2
147; GFX10-NEXT:    v_mov_b32_e32 v7, v1
148; GFX10-NEXT:    v_lshl_or_b32 v10, v5, 16, v0
149; GFX10-NEXT:    image_sample_d_cl v[0:3], v[6:11], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
150; GFX10-NEXT:    s_waitcnt vmcnt(0)
151; GFX10-NEXT:    ; return to shader part epilog
152;
153; GFX10GISEL-LABEL: sample_d_cl_2d:
154; GFX10GISEL:       ; %bb.0: ; %main_body
155; GFX10GISEL-NEXT:    v_mov_b32_e32 v7, 0xffff
156; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
157; GFX10GISEL-NEXT:    s_lshl_b32 s12, s0, 16
158; GFX10GISEL-NEXT:    v_and_or_b32 v4, v4, v7, v5
159; GFX10GISEL-NEXT:    v_and_or_b32 v5, v6, v7, s12
160; GFX10GISEL-NEXT:    image_sample_d_cl v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
161; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
162; GFX10GISEL-NEXT:    ; return to shader part epilog
163main_body:
164  %v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.2d.v4f32.f32.f16(i32 15, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
165  ret <4 x float> %v
166}
167
168define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dsdv, half %s, half %clamp) {
169; GFX10-LABEL: sample_c_d_cl_1d:
170; GFX10:       ; %bb.0: ; %main_body
171; GFX10-NEXT:    v_and_b32_e32 v3, 0xffff, v3
172; GFX10-NEXT:    v_lshl_or_b32 v3, v4, 16, v3
173; GFX10-NEXT:    image_sample_c_d_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
174; GFX10-NEXT:    s_waitcnt vmcnt(0)
175; GFX10-NEXT:    ; return to shader part epilog
176;
177; GFX10GISEL-LABEL: sample_c_d_cl_1d:
178; GFX10GISEL:       ; %bb.0: ; %main_body
179; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
180; GFX10GISEL-NEXT:    v_and_or_b32 v3, 0xffff, v3, v4
181; GFX10GISEL-NEXT:    image_sample_c_d_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
182; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
183; GFX10GISEL-NEXT:    ; return to shader part epilog
184main_body:
185  %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f32.f16(i32 15, float %zcompare, float %dsdh, float %dsdv, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
186  ret <4 x float> %v
187}
188
189define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %clamp) {
190; GFX10-LABEL: sample_c_d_cl_2d:
191; GFX10:       ; %bb.0: ; %main_body
192; GFX10-NEXT:    v_mov_b32_e32 v13, v7
193; GFX10-NEXT:    v_mov_b32_e32 v7, v0
194; GFX10-NEXT:    v_and_b32_e32 v0, 0xffff, v5
195; GFX10-NEXT:    v_mov_b32_e32 v11, v4
196; GFX10-NEXT:    v_mov_b32_e32 v10, v3
197; GFX10-NEXT:    v_mov_b32_e32 v9, v2
198; GFX10-NEXT:    v_mov_b32_e32 v8, v1
199; GFX10-NEXT:    v_lshl_or_b32 v12, v6, 16, v0
200; GFX10-NEXT:    image_sample_c_d_cl v[0:3], v[7:13], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
201; GFX10-NEXT:    s_waitcnt vmcnt(0)
202; GFX10-NEXT:    ; return to shader part epilog
203;
204; GFX10GISEL-LABEL: sample_c_d_cl_2d:
205; GFX10GISEL:       ; %bb.0: ; %main_body
206; GFX10GISEL-NEXT:    v_mov_b32_e32 v8, 0xffff
207; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
208; GFX10GISEL-NEXT:    s_lshl_b32 s12, s0, 16
209; GFX10GISEL-NEXT:    v_and_or_b32 v5, v5, v8, v6
210; GFX10GISEL-NEXT:    v_and_or_b32 v6, v7, v8, s12
211; GFX10GISEL-NEXT:    image_sample_c_d_cl v[0:3], v[0:6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
212; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
213; GFX10GISEL-NEXT:    ; return to shader part epilog
214main_body:
215  %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v4f32.f32.f16(i32 15, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
216  ret <4 x float> %v
217}
218
219define amdgpu_ps <4 x float> @sample_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dsdv, half %s) {
220; GFX10-LABEL: sample_cd_1d:
221; GFX10:       ; %bb.0: ; %main_body
222; GFX10-NEXT:    image_sample_cd v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
223; GFX10-NEXT:    s_waitcnt vmcnt(0)
224; GFX10-NEXT:    ; return to shader part epilog
225;
226; GFX10GISEL-LABEL: sample_cd_1d:
227; GFX10GISEL:       ; %bb.0: ; %main_body
228; GFX10GISEL-NEXT:    s_lshl_b32 s12, s0, 16
229; GFX10GISEL-NEXT:    v_and_or_b32 v2, 0xffff, v2, s12
230; GFX10GISEL-NEXT:    image_sample_cd v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
231; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
232; GFX10GISEL-NEXT:    ; return to shader part epilog
233main_body:
234  %v = call <4 x float> @llvm.amdgcn.image.sample.cd.1d.v4f32.f32.f16(i32 15, float %dsdh, float %dsdv, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
235  ret <4 x float> %v
236}
237
238define amdgpu_ps <4 x float> @sample_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t) {
239; GFX10-LABEL: sample_cd_2d:
240; GFX10:       ; %bb.0: ; %main_body
241; GFX10-NEXT:    v_and_b32_e32 v4, 0xffff, v4
242; GFX10-NEXT:    v_lshl_or_b32 v4, v5, 16, v4
243; GFX10-NEXT:    image_sample_cd v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
244; GFX10-NEXT:    s_waitcnt vmcnt(0)
245; GFX10-NEXT:    ; return to shader part epilog
246;
247; GFX10GISEL-LABEL: sample_cd_2d:
248; GFX10GISEL:       ; %bb.0: ; %main_body
249; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
250; GFX10GISEL-NEXT:    v_and_or_b32 v4, 0xffff, v4, v5
251; GFX10GISEL-NEXT:    image_sample_cd v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
252; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
253; GFX10GISEL-NEXT:    ; return to shader part epilog
254main_body:
255  %v = call <4 x float> @llvm.amdgcn.image.sample.cd.2d.v4f32.f32.f16(i32 15, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
256  ret <4 x float> %v
257}
258
259define amdgpu_ps <4 x float> @sample_c_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dsdv, half %s) {
260; GFX10-LABEL: sample_c_cd_1d:
261; GFX10:       ; %bb.0: ; %main_body
262; GFX10-NEXT:    image_sample_c_cd v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
263; GFX10-NEXT:    s_waitcnt vmcnt(0)
264; GFX10-NEXT:    ; return to shader part epilog
265;
266; GFX10GISEL-LABEL: sample_c_cd_1d:
267; GFX10GISEL:       ; %bb.0: ; %main_body
268; GFX10GISEL-NEXT:    s_lshl_b32 s12, s0, 16
269; GFX10GISEL-NEXT:    v_and_or_b32 v3, 0xffff, v3, s12
270; GFX10GISEL-NEXT:    image_sample_c_cd v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
271; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
272; GFX10GISEL-NEXT:    ; return to shader part epilog
273main_body:
274  %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.1d.v4f32.f32.f16(i32 15, float %zcompare, float %dsdh, float %dsdv, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
275  ret <4 x float> %v
276}
277
278define amdgpu_ps <4 x float> @sample_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t) {
279; GFX10-LABEL: sample_c_cd_2d:
280; GFX10:       ; %bb.0: ; %main_body
281; GFX10-NEXT:    v_and_b32_e32 v5, 0xffff, v5
282; GFX10-NEXT:    v_lshl_or_b32 v5, v6, 16, v5
283; GFX10-NEXT:    image_sample_c_cd v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
284; GFX10-NEXT:    s_waitcnt vmcnt(0)
285; GFX10-NEXT:    ; return to shader part epilog
286;
287; GFX10GISEL-LABEL: sample_c_cd_2d:
288; GFX10GISEL:       ; %bb.0: ; %main_body
289; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
290; GFX10GISEL-NEXT:    v_and_or_b32 v5, 0xffff, v5, v6
291; GFX10GISEL-NEXT:    image_sample_c_cd v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
292; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
293; GFX10GISEL-NEXT:    ; return to shader part epilog
294main_body:
295  %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.2d.v4f32.f32.f16(i32 15, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
296  ret <4 x float> %v
297}
298
299define amdgpu_ps <4 x float> @sample_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dsdv, half %s, half %clamp) {
300; GFX10-LABEL: sample_cd_cl_1d:
301; GFX10:       ; %bb.0: ; %main_body
302; GFX10-NEXT:    v_and_b32_e32 v2, 0xffff, v2
303; GFX10-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
304; GFX10-NEXT:    image_sample_cd_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
305; GFX10-NEXT:    s_waitcnt vmcnt(0)
306; GFX10-NEXT:    ; return to shader part epilog
307;
308; GFX10GISEL-LABEL: sample_cd_cl_1d:
309; GFX10GISEL:       ; %bb.0: ; %main_body
310; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
311; GFX10GISEL-NEXT:    v_and_or_b32 v2, 0xffff, v2, v3
312; GFX10GISEL-NEXT:    image_sample_cd_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
313; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
314; GFX10GISEL-NEXT:    ; return to shader part epilog
315main_body:
316  %v = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.1d.v4f32.f32.f16(i32 15, float %dsdh, float %dsdv, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
317  ret <4 x float> %v
318}
319
320define amdgpu_ps <4 x float> @sample_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %clamp) {
321; GFX10-LABEL: sample_cd_cl_2d:
322; GFX10:       ; %bb.0: ; %main_body
323; GFX10-NEXT:    v_mov_b32_e32 v11, v6
324; GFX10-NEXT:    v_mov_b32_e32 v6, v0
325; GFX10-NEXT:    v_and_b32_e32 v0, 0xffff, v4
326; GFX10-NEXT:    v_mov_b32_e32 v9, v3
327; GFX10-NEXT:    v_mov_b32_e32 v8, v2
328; GFX10-NEXT:    v_mov_b32_e32 v7, v1
329; GFX10-NEXT:    v_lshl_or_b32 v10, v5, 16, v0
330; GFX10-NEXT:    image_sample_cd_cl v[0:3], v[6:11], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
331; GFX10-NEXT:    s_waitcnt vmcnt(0)
332; GFX10-NEXT:    ; return to shader part epilog
333;
334; GFX10GISEL-LABEL: sample_cd_cl_2d:
335; GFX10GISEL:       ; %bb.0: ; %main_body
336; GFX10GISEL-NEXT:    v_mov_b32_e32 v7, 0xffff
337; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
338; GFX10GISEL-NEXT:    s_lshl_b32 s12, s0, 16
339; GFX10GISEL-NEXT:    v_and_or_b32 v4, v4, v7, v5
340; GFX10GISEL-NEXT:    v_and_or_b32 v5, v6, v7, s12
341; GFX10GISEL-NEXT:    image_sample_cd_cl v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
342; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
343; GFX10GISEL-NEXT:    ; return to shader part epilog
344main_body:
345  %v = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.2d.v4f32.f32.f16(i32 15, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
346  ret <4 x float> %v
347}
348
349define amdgpu_ps <4 x float> @sample_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dsdv, half %s, half %clamp) {
350; GFX10-LABEL: sample_c_cd_cl_1d:
351; GFX10:       ; %bb.0: ; %main_body
352; GFX10-NEXT:    v_and_b32_e32 v3, 0xffff, v3
353; GFX10-NEXT:    v_lshl_or_b32 v3, v4, 16, v3
354; GFX10-NEXT:    image_sample_c_cd_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
355; GFX10-NEXT:    s_waitcnt vmcnt(0)
356; GFX10-NEXT:    ; return to shader part epilog
357;
358; GFX10GISEL-LABEL: sample_c_cd_cl_1d:
359; GFX10GISEL:       ; %bb.0: ; %main_body
360; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
361; GFX10GISEL-NEXT:    v_and_or_b32 v3, 0xffff, v3, v4
362; GFX10GISEL-NEXT:    image_sample_c_cd_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
363; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
364; GFX10GISEL-NEXT:    ; return to shader part epilog
365main_body:
366  %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.1d.v4f32.f32.f16(i32 15, float %zcompare, float %dsdh, float %dsdv, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
367  ret <4 x float> %v
368}
369
370define amdgpu_ps <4 x float> @sample_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %clamp) {
371; GFX10-LABEL: sample_c_cd_cl_2d:
372; GFX10:       ; %bb.0: ; %main_body
373; GFX10-NEXT:    v_mov_b32_e32 v13, v7
374; GFX10-NEXT:    v_mov_b32_e32 v7, v0
375; GFX10-NEXT:    v_and_b32_e32 v0, 0xffff, v5
376; GFX10-NEXT:    v_mov_b32_e32 v11, v4
377; GFX10-NEXT:    v_mov_b32_e32 v10, v3
378; GFX10-NEXT:    v_mov_b32_e32 v9, v2
379; GFX10-NEXT:    v_mov_b32_e32 v8, v1
380; GFX10-NEXT:    v_lshl_or_b32 v12, v6, 16, v0
381; GFX10-NEXT:    image_sample_c_cd_cl v[0:3], v[7:13], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
382; GFX10-NEXT:    s_waitcnt vmcnt(0)
383; GFX10-NEXT:    ; return to shader part epilog
384;
385; GFX10GISEL-LABEL: sample_c_cd_cl_2d:
386; GFX10GISEL:       ; %bb.0: ; %main_body
387; GFX10GISEL-NEXT:    v_mov_b32_e32 v8, 0xffff
388; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
389; GFX10GISEL-NEXT:    s_lshl_b32 s12, s0, 16
390; GFX10GISEL-NEXT:    v_and_or_b32 v5, v5, v8, v6
391; GFX10GISEL-NEXT:    v_and_or_b32 v6, v7, v8, s12
392; GFX10GISEL-NEXT:    image_sample_c_cd_cl v[0:3], v[0:6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
393; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
394; GFX10GISEL-NEXT:    ; return to shader part epilog
395main_body:
396  %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.2d.v4f32.f32.f16(i32 15, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
397  ret <4 x float> %v
398}
399
400define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %slice) {
401; GFX10-LABEL: sample_c_d_o_2darray_V1:
402; GFX10:       ; %bb.0: ; %main_body
403; GFX10-NEXT:    v_mov_b32_e32 v15, v8
404; GFX10-NEXT:    v_mov_b32_e32 v8, v0
405; GFX10-NEXT:    v_and_b32_e32 v0, 0xffff, v6
406; GFX10-NEXT:    v_mov_b32_e32 v13, v5
407; GFX10-NEXT:    v_mov_b32_e32 v12, v4
408; GFX10-NEXT:    v_mov_b32_e32 v11, v3
409; GFX10-NEXT:    v_mov_b32_e32 v10, v2
410; GFX10-NEXT:    v_mov_b32_e32 v9, v1
411; GFX10-NEXT:    v_lshl_or_b32 v14, v7, 16, v0
412; GFX10-NEXT:    image_sample_c_d_o v0, v[8:15], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
413; GFX10-NEXT:    s_waitcnt vmcnt(0)
414; GFX10-NEXT:    ; return to shader part epilog
415;
416; GFX10GISEL-LABEL: sample_c_d_o_2darray_V1:
417; GFX10GISEL:       ; %bb.0: ; %main_body
418; GFX10GISEL-NEXT:    v_mov_b32_e32 v9, 0xffff
419; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
420; GFX10GISEL-NEXT:    s_lshl_b32 s12, s0, 16
421; GFX10GISEL-NEXT:    v_and_or_b32 v6, v6, v9, v7
422; GFX10GISEL-NEXT:    v_and_or_b32 v7, v8, v9, s12
423; GFX10GISEL-NEXT:    image_sample_c_d_o v0, v[0:7], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
424; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
425; GFX10GISEL-NEXT:    ; return to shader part epilog
426main_body:
427  %v = call float @llvm.amdgcn.image.sample.c.d.o.2darray.f32.f32.f16(i32 4, i32 %offset, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
428  ret float %v
429}
430
431define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %slice) {
432; GFX10-LABEL: sample_c_d_o_2darray_V2:
433; GFX10:       ; %bb.0: ; %main_body
434; GFX10-NEXT:    v_mov_b32_e32 v15, v8
435; GFX10-NEXT:    v_mov_b32_e32 v8, v0
436; GFX10-NEXT:    v_and_b32_e32 v0, 0xffff, v6
437; GFX10-NEXT:    v_mov_b32_e32 v13, v5
438; GFX10-NEXT:    v_mov_b32_e32 v12, v4
439; GFX10-NEXT:    v_mov_b32_e32 v11, v3
440; GFX10-NEXT:    v_mov_b32_e32 v10, v2
441; GFX10-NEXT:    v_mov_b32_e32 v9, v1
442; GFX10-NEXT:    v_lshl_or_b32 v14, v7, 16, v0
443; GFX10-NEXT:    image_sample_c_d_o v[0:1], v[8:15], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY a16
444; GFX10-NEXT:    s_waitcnt vmcnt(0)
445; GFX10-NEXT:    ; return to shader part epilog
446;
447; GFX10GISEL-LABEL: sample_c_d_o_2darray_V2:
448; GFX10GISEL:       ; %bb.0: ; %main_body
449; GFX10GISEL-NEXT:    v_mov_b32_e32 v9, 0xffff
450; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
451; GFX10GISEL-NEXT:    s_lshl_b32 s12, s0, 16
452; GFX10GISEL-NEXT:    v_and_or_b32 v6, v6, v9, v7
453; GFX10GISEL-NEXT:    v_and_or_b32 v7, v8, v9, s12
454; GFX10GISEL-NEXT:    image_sample_c_d_o v[0:1], v[0:7], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY a16
455; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
456; GFX10GISEL-NEXT:    ; return to shader part epilog
457main_body:
458  %v = call <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f32.f16(i32 6, i32 %offset, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
459  ret <2 x float> %v
460}
461
462declare <4 x float> @llvm.amdgcn.image.sample.d.1d.v4f32.f32.f16(i32, float, float, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
463declare <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32.f16(i32, float, float, float, float, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
464declare <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f32.f16(i32, float, float, float, float, float, float, half, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
465declare <4 x float> @llvm.amdgcn.image.sample.c.d.1d.v4f32.f32.f16(i32, float, float, float, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
466declare <4 x float> @llvm.amdgcn.image.sample.c.d.2d.v4f32.f32.f16(i32, float, float, float, float, float, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
467declare <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f32.f16(i32, float, float, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
468declare <4 x float> @llvm.amdgcn.image.sample.d.cl.2d.v4f32.f32.f16(i32, float, float, float, float, half, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
469declare <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f32.f16(i32, float, float, float, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
470declare <4 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v4f32.f32.f16(i32, float, float, float, float, float, half, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
471
472declare <4 x float> @llvm.amdgcn.image.sample.cd.1d.v4f32.f32.f16(i32, float, float, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
473declare <4 x float> @llvm.amdgcn.image.sample.cd.2d.v4f32.f32.f16(i32, float, float, float, float, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
474declare <4 x float> @llvm.amdgcn.image.sample.c.cd.1d.v4f32.f32.f16(i32, float, float, float, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
475declare <4 x float> @llvm.amdgcn.image.sample.c.cd.2d.v4f32.f32.f16(i32, float, float, float, float, float, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
476declare <4 x float> @llvm.amdgcn.image.sample.cd.cl.1d.v4f32.f32.f16(i32, float, float, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
477declare <4 x float> @llvm.amdgcn.image.sample.cd.cl.2d.v4f32.f32.f16(i32, float, float, float, float, half, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
478declare <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.1d.v4f32.f32.f16(i32, float, float, float, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
479declare <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.2d.v4f32.f32.f16(i32, float, float, float, float, float, half, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
480
481declare float @llvm.amdgcn.image.sample.c.d.o.2darray.f32.f32.f16(i32, i32, float, float, float, float, float, half, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
482declare <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f32.f16(i32, i32, float, float, float, float, float, half, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
483
484define amdgpu_ps <4 x float> @sample_g16_noa16_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s) {
485; GFX10-LABEL: sample_g16_noa16_d_1d:
486; GFX10:       ; %bb.0: ; %main_body
487; GFX10-NEXT:    image_sample_d_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
488; GFX10-NEXT:    s_waitcnt vmcnt(0)
489; GFX10-NEXT:    ; return to shader part epilog
490;
491; GFX10GISEL-LABEL: sample_g16_noa16_d_1d:
492; GFX10GISEL:       ; %bb.0: ; %main_body
493; GFX10GISEL-NEXT:    v_mov_b32_e32 v3, 0xffff
494; GFX10GISEL-NEXT:    s_lshl_b32 s12, s0, 16
495; GFX10GISEL-NEXT:    v_and_or_b32 v0, v0, v3, s12
496; GFX10GISEL-NEXT:    v_and_or_b32 v1, v1, v3, s12
497; GFX10GISEL-NEXT:    image_sample_d_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
498; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
499; GFX10GISEL-NEXT:    ; return to shader part epilog
500main_body:
501  %v = call <4 x float> @llvm.amdgcn.image.sample.d.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
502  ret <4 x float> %v
503}
504
505define amdgpu_ps <4 x float> @sample_g16_noa16_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) {
506; GFX10-LABEL: sample_g16_noa16_d_2d:
507; GFX10:       ; %bb.0: ; %main_body
508; GFX10-NEXT:    v_mov_b32_e32 v6, 0xffff
509; GFX10-NEXT:    v_and_b32_e32 v2, v6, v2
510; GFX10-NEXT:    v_and_b32_e32 v0, v6, v0
511; GFX10-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
512; GFX10-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
513; GFX10-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
514; GFX10-NEXT:    s_waitcnt vmcnt(0)
515; GFX10-NEXT:    ; return to shader part epilog
516;
517; GFX10GISEL-LABEL: sample_g16_noa16_d_2d:
518; GFX10GISEL:       ; %bb.0: ; %main_body
519; GFX10GISEL-NEXT:    v_mov_b32_e32 v6, 0xffff
520; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
521; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
522; GFX10GISEL-NEXT:    v_and_or_b32 v0, v0, v6, v1
523; GFX10GISEL-NEXT:    v_and_or_b32 v1, v2, v6, v3
524; GFX10GISEL-NEXT:    image_sample_d_g16 v[0:3], [v0, v1, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
525; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
526; GFX10GISEL-NEXT:    ; return to shader part epilog
527main_body:
528  %v = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
529  ret <4 x float> %v
530}
531
532define amdgpu_ps <4 x float> @sample_g16_noa16_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %drdh, half %dsdv, half %dtdv, half %drdv, float %s, float %t, float %r) {
533; GFX10-LABEL: sample_g16_noa16_d_3d:
534; GFX10:       ; %bb.0: ; %main_body
535; GFX10-NEXT:    v_mov_b32_e32 v9, v3
536; GFX10-NEXT:    v_mov_b32_e32 v3, v2
537; GFX10-NEXT:    v_mov_b32_e32 v2, 0xffff
538; GFX10-NEXT:    v_and_b32_e32 v9, v2, v9
539; GFX10-NEXT:    v_and_b32_e32 v0, v2, v0
540; GFX10-NEXT:    v_lshl_or_b32 v4, v4, 16, v9
541; GFX10-NEXT:    v_lshl_or_b32 v2, v1, 16, v0
542; GFX10-NEXT:    image_sample_d_g16 v[0:3], v[2:8], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
543; GFX10-NEXT:    s_waitcnt vmcnt(0)
544; GFX10-NEXT:    ; return to shader part epilog
545;
546; GFX10GISEL-LABEL: sample_g16_noa16_d_3d:
547; GFX10GISEL:       ; %bb.0: ; %main_body
548; GFX10GISEL-NEXT:    v_mov_b32_e32 v9, v2
549; GFX10GISEL-NEXT:    v_mov_b32_e32 v10, v3
550; GFX10GISEL-NEXT:    v_mov_b32_e32 v11, 0xffff
551; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
552; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
553; GFX10GISEL-NEXT:    s_lshl_b32 s12, s0, 16
554; GFX10GISEL-NEXT:    v_and_or_b32 v3, v9, v11, s12
555; GFX10GISEL-NEXT:    v_and_or_b32 v2, v0, v11, v1
556; GFX10GISEL-NEXT:    v_and_or_b32 v4, v10, v11, v4
557; GFX10GISEL-NEXT:    v_and_or_b32 v5, v5, v11, s12
558; GFX10GISEL-NEXT:    image_sample_d_g16 v[0:3], v[2:8], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
559; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
560; GFX10GISEL-NEXT:    ; return to shader part epilog
561main_body:
562  %v = call <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %drdh, half %dsdv, half %dtdv, half %drdv, float %s, float %t, float %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
563  ret <4 x float> %v
564}
565
566define amdgpu_ps <4 x float> @sample_g16_noa16_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s) {
567; GFX10-LABEL: sample_g16_noa16_c_d_1d:
568; GFX10:       ; %bb.0: ; %main_body
569; GFX10-NEXT:    image_sample_c_d_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
570; GFX10-NEXT:    s_waitcnt vmcnt(0)
571; GFX10-NEXT:    ; return to shader part epilog
572;
573; GFX10GISEL-LABEL: sample_g16_noa16_c_d_1d:
574; GFX10GISEL:       ; %bb.0: ; %main_body
575; GFX10GISEL-NEXT:    v_mov_b32_e32 v4, 0xffff
576; GFX10GISEL-NEXT:    s_lshl_b32 s12, s0, 16
577; GFX10GISEL-NEXT:    v_and_or_b32 v1, v1, v4, s12
578; GFX10GISEL-NEXT:    v_and_or_b32 v2, v2, v4, s12
579; GFX10GISEL-NEXT:    image_sample_c_d_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
580; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
581; GFX10GISEL-NEXT:    ; return to shader part epilog
582main_body:
583  %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
584  ret <4 x float> %v
585}
586
587define amdgpu_ps <4 x float> @sample_g16_noa16_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) {
588; GFX10-LABEL: sample_g16_noa16_c_d_2d:
589; GFX10:       ; %bb.0: ; %main_body
590; GFX10-NEXT:    v_mov_b32_e32 v7, 0xffff
591; GFX10-NEXT:    v_and_b32_e32 v3, v7, v3
592; GFX10-NEXT:    v_and_b32_e32 v1, v7, v1
593; GFX10-NEXT:    v_lshl_or_b32 v3, v4, 16, v3
594; GFX10-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
595; GFX10-NEXT:    image_sample_c_d_g16 v[0:3], [v0, v1, v3, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
596; GFX10-NEXT:    s_waitcnt vmcnt(0)
597; GFX10-NEXT:    ; return to shader part epilog
598;
599; GFX10GISEL-LABEL: sample_g16_noa16_c_d_2d:
600; GFX10GISEL:       ; %bb.0: ; %main_body
601; GFX10GISEL-NEXT:    v_mov_b32_e32 v7, 0xffff
602; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
603; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
604; GFX10GISEL-NEXT:    v_and_or_b32 v1, v1, v7, v2
605; GFX10GISEL-NEXT:    v_and_or_b32 v2, v3, v7, v4
606; GFX10GISEL-NEXT:    image_sample_c_d_g16 v[0:3], [v0, v1, v2, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
607; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
608; GFX10GISEL-NEXT:    ; return to shader part epilog
609main_body:
610  %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
611  ret <4 x float> %v
612}
613
614define amdgpu_ps <4 x float> @sample_g16_noa16_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s, float %clamp) {
615; GFX10-LABEL: sample_g16_noa16_d_cl_1d:
616; GFX10:       ; %bb.0: ; %main_body
617; GFX10-NEXT:    image_sample_d_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
618; GFX10-NEXT:    s_waitcnt vmcnt(0)
619; GFX10-NEXT:    ; return to shader part epilog
620;
621; GFX10GISEL-LABEL: sample_g16_noa16_d_cl_1d:
622; GFX10GISEL:       ; %bb.0: ; %main_body
623; GFX10GISEL-NEXT:    v_mov_b32_e32 v4, 0xffff
624; GFX10GISEL-NEXT:    s_lshl_b32 s12, s0, 16
625; GFX10GISEL-NEXT:    v_and_or_b32 v0, v0, v4, s12
626; GFX10GISEL-NEXT:    v_and_or_b32 v1, v1, v4, s12
627; GFX10GISEL-NEXT:    image_sample_d_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
628; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
629; GFX10GISEL-NEXT:    ; return to shader part epilog
630main_body:
631  %v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
632  ret <4 x float> %v
633}
634
635define amdgpu_ps <4 x float> @sample_g16_noa16_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) {
636; GFX10-LABEL: sample_g16_noa16_d_cl_2d:
637; GFX10:       ; %bb.0: ; %main_body
638; GFX10-NEXT:    v_mov_b32_e32 v7, 0xffff
639; GFX10-NEXT:    v_and_b32_e32 v2, v7, v2
640; GFX10-NEXT:    v_and_b32_e32 v0, v7, v0
641; GFX10-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
642; GFX10-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
643; GFX10-NEXT:    image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
644; GFX10-NEXT:    s_waitcnt vmcnt(0)
645; GFX10-NEXT:    ; return to shader part epilog
646;
647; GFX10GISEL-LABEL: sample_g16_noa16_d_cl_2d:
648; GFX10GISEL:       ; %bb.0: ; %main_body
649; GFX10GISEL-NEXT:    v_mov_b32_e32 v7, 0xffff
650; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
651; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
652; GFX10GISEL-NEXT:    v_and_or_b32 v0, v0, v7, v1
653; GFX10GISEL-NEXT:    v_and_or_b32 v1, v2, v7, v3
654; GFX10GISEL-NEXT:    image_sample_d_cl_g16 v[0:3], [v0, v1, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
655; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
656; GFX10GISEL-NEXT:    ; return to shader part epilog
657main_body:
658  %v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
659  ret <4 x float> %v
660}
661
662define amdgpu_ps <4 x float> @sample_g16_noa16_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp) {
663; GFX10-LABEL: sample_g16_noa16_c_d_cl_1d:
664; GFX10:       ; %bb.0: ; %main_body
665; GFX10-NEXT:    image_sample_c_d_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
666; GFX10-NEXT:    s_waitcnt vmcnt(0)
667; GFX10-NEXT:    ; return to shader part epilog
668;
669; GFX10GISEL-LABEL: sample_g16_noa16_c_d_cl_1d:
670; GFX10GISEL:       ; %bb.0: ; %main_body
671; GFX10GISEL-NEXT:    v_mov_b32_e32 v5, 0xffff
672; GFX10GISEL-NEXT:    s_lshl_b32 s12, s0, 16
673; GFX10GISEL-NEXT:    v_and_or_b32 v1, v1, v5, s12
674; GFX10GISEL-NEXT:    v_and_or_b32 v2, v2, v5, s12
675; GFX10GISEL-NEXT:    image_sample_c_d_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
676; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
677; GFX10GISEL-NEXT:    ; return to shader part epilog
678main_body:
679  %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
680  ret <4 x float> %v
681}
682
683define amdgpu_ps <4 x float> @sample_g16_noa16_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) {
684; GFX10-LABEL: sample_g16_noa16_c_d_cl_2d:
685; GFX10:       ; %bb.0: ; %main_body
686; GFX10-NEXT:    v_mov_b32_e32 v8, v2
687; GFX10-NEXT:    v_mov_b32_e32 v2, v0
688; GFX10-NEXT:    v_mov_b32_e32 v0, 0xffff
689; GFX10-NEXT:    v_and_b32_e32 v3, v0, v3
690; GFX10-NEXT:    v_and_b32_e32 v0, v0, v1
691; GFX10-NEXT:    v_lshl_or_b32 v4, v4, 16, v3
692; GFX10-NEXT:    v_lshl_or_b32 v3, v8, 16, v0
693; GFX10-NEXT:    image_sample_c_d_cl_g16 v[0:3], v[2:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
694; GFX10-NEXT:    s_waitcnt vmcnt(0)
695; GFX10-NEXT:    ; return to shader part epilog
696;
697; GFX10GISEL-LABEL: sample_g16_noa16_c_d_cl_2d:
698; GFX10GISEL:       ; %bb.0: ; %main_body
699; GFX10GISEL-NEXT:    v_mov_b32_e32 v8, v2
700; GFX10GISEL-NEXT:    v_mov_b32_e32 v9, v3
701; GFX10GISEL-NEXT:    v_mov_b32_e32 v2, v0
702; GFX10GISEL-NEXT:    v_mov_b32_e32 v0, 0xffff
703; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
704; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v3, 16, v8
705; GFX10GISEL-NEXT:    v_and_or_b32 v4, v9, v0, v4
706; GFX10GISEL-NEXT:    v_and_or_b32 v3, v1, v0, v3
707; GFX10GISEL-NEXT:    image_sample_c_d_cl_g16 v[0:3], v[2:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
708; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
709; GFX10GISEL-NEXT:    ; return to shader part epilog
710main_body:
711  %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
712  ret <4 x float> %v
713}
714
715define amdgpu_ps <4 x float> @sample_g16_noa16_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s) {
716; GFX10-LABEL: sample_g16_noa16_cd_1d:
717; GFX10:       ; %bb.0: ; %main_body
718; GFX10-NEXT:    image_sample_cd_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
719; GFX10-NEXT:    s_waitcnt vmcnt(0)
720; GFX10-NEXT:    ; return to shader part epilog
721;
722; GFX10GISEL-LABEL: sample_g16_noa16_cd_1d:
723; GFX10GISEL:       ; %bb.0: ; %main_body
724; GFX10GISEL-NEXT:    v_mov_b32_e32 v3, 0xffff
725; GFX10GISEL-NEXT:    s_lshl_b32 s12, s0, 16
726; GFX10GISEL-NEXT:    v_and_or_b32 v0, v0, v3, s12
727; GFX10GISEL-NEXT:    v_and_or_b32 v1, v1, v3, s12
728; GFX10GISEL-NEXT:    image_sample_cd_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
729; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
730; GFX10GISEL-NEXT:    ; return to shader part epilog
731main_body:
732  %v = call <4 x float> @llvm.amdgcn.image.sample.cd.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
733  ret <4 x float> %v
734}
735
736define amdgpu_ps <4 x float> @sample_g16_noa16_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) {
737; GFX10-LABEL: sample_g16_noa16_cd_2d:
738; GFX10:       ; %bb.0: ; %main_body
739; GFX10-NEXT:    v_mov_b32_e32 v6, 0xffff
740; GFX10-NEXT:    v_and_b32_e32 v2, v6, v2
741; GFX10-NEXT:    v_and_b32_e32 v0, v6, v0
742; GFX10-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
743; GFX10-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
744; GFX10-NEXT:    image_sample_cd_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
745; GFX10-NEXT:    s_waitcnt vmcnt(0)
746; GFX10-NEXT:    ; return to shader part epilog
747;
748; GFX10GISEL-LABEL: sample_g16_noa16_cd_2d:
749; GFX10GISEL:       ; %bb.0: ; %main_body
750; GFX10GISEL-NEXT:    v_mov_b32_e32 v6, 0xffff
751; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
752; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
753; GFX10GISEL-NEXT:    v_and_or_b32 v0, v0, v6, v1
754; GFX10GISEL-NEXT:    v_and_or_b32 v1, v2, v6, v3
755; GFX10GISEL-NEXT:    image_sample_cd_g16 v[0:3], [v0, v1, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
756; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
757; GFX10GISEL-NEXT:    ; return to shader part epilog
758main_body:
759  %v = call <4 x float> @llvm.amdgcn.image.sample.cd.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
760  ret <4 x float> %v
761}
762
763define amdgpu_ps <4 x float> @sample_g16_noa16_c_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s) {
764; GFX10-LABEL: sample_g16_noa16_c_cd_1d:
765; GFX10:       ; %bb.0: ; %main_body
766; GFX10-NEXT:    image_sample_c_cd_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
767; GFX10-NEXT:    s_waitcnt vmcnt(0)
768; GFX10-NEXT:    ; return to shader part epilog
769;
770; GFX10GISEL-LABEL: sample_g16_noa16_c_cd_1d:
771; GFX10GISEL:       ; %bb.0: ; %main_body
772; GFX10GISEL-NEXT:    v_mov_b32_e32 v4, 0xffff
773; GFX10GISEL-NEXT:    s_lshl_b32 s12, s0, 16
774; GFX10GISEL-NEXT:    v_and_or_b32 v1, v1, v4, s12
775; GFX10GISEL-NEXT:    v_and_or_b32 v2, v2, v4, s12
776; GFX10GISEL-NEXT:    image_sample_c_cd_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
777; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
778; GFX10GISEL-NEXT:    ; return to shader part epilog
779main_body:
780  %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
781  ret <4 x float> %v
782}
783
784define amdgpu_ps <4 x float> @sample_g16_noa16_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) {
785; GFX10-LABEL: sample_g16_noa16_c_cd_2d:
786; GFX10:       ; %bb.0: ; %main_body
787; GFX10-NEXT:    v_mov_b32_e32 v7, 0xffff
788; GFX10-NEXT:    v_and_b32_e32 v3, v7, v3
789; GFX10-NEXT:    v_and_b32_e32 v1, v7, v1
790; GFX10-NEXT:    v_lshl_or_b32 v3, v4, 16, v3
791; GFX10-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
792; GFX10-NEXT:    image_sample_c_cd_g16 v[0:3], [v0, v1, v3, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
793; GFX10-NEXT:    s_waitcnt vmcnt(0)
794; GFX10-NEXT:    ; return to shader part epilog
795;
796; GFX10GISEL-LABEL: sample_g16_noa16_c_cd_2d:
797; GFX10GISEL:       ; %bb.0: ; %main_body
798; GFX10GISEL-NEXT:    v_mov_b32_e32 v7, 0xffff
799; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
800; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
801; GFX10GISEL-NEXT:    v_and_or_b32 v1, v1, v7, v2
802; GFX10GISEL-NEXT:    v_and_or_b32 v2, v3, v7, v4
803; GFX10GISEL-NEXT:    image_sample_c_cd_g16 v[0:3], [v0, v1, v2, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
804; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
805; GFX10GISEL-NEXT:    ; return to shader part epilog
806main_body:
807  %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
808  ret <4 x float> %v
809}
810
811define amdgpu_ps <4 x float> @sample_g16_noa16_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s, float %clamp) {
812; GFX10-LABEL: sample_g16_noa16_cd_cl_1d:
813; GFX10:       ; %bb.0: ; %main_body
814; GFX10-NEXT:    image_sample_cd_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
815; GFX10-NEXT:    s_waitcnt vmcnt(0)
816; GFX10-NEXT:    ; return to shader part epilog
817;
818; GFX10GISEL-LABEL: sample_g16_noa16_cd_cl_1d:
819; GFX10GISEL:       ; %bb.0: ; %main_body
820; GFX10GISEL-NEXT:    v_mov_b32_e32 v4, 0xffff
821; GFX10GISEL-NEXT:    s_lshl_b32 s12, s0, 16
822; GFX10GISEL-NEXT:    v_and_or_b32 v0, v0, v4, s12
823; GFX10GISEL-NEXT:    v_and_or_b32 v1, v1, v4, s12
824; GFX10GISEL-NEXT:    image_sample_cd_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
825; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
826; GFX10GISEL-NEXT:    ; return to shader part epilog
827main_body:
828  %v = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
829  ret <4 x float> %v
830}
831
832define amdgpu_ps <4 x float> @sample_g16_noa16_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) {
833; GFX10-LABEL: sample_g16_noa16_cd_cl_2d:
834; GFX10:       ; %bb.0: ; %main_body
835; GFX10-NEXT:    v_mov_b32_e32 v7, 0xffff
836; GFX10-NEXT:    v_and_b32_e32 v2, v7, v2
837; GFX10-NEXT:    v_and_b32_e32 v0, v7, v0
838; GFX10-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
839; GFX10-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
840; GFX10-NEXT:    image_sample_cd_cl_g16 v[0:3], [v0, v2, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
841; GFX10-NEXT:    s_waitcnt vmcnt(0)
842; GFX10-NEXT:    ; return to shader part epilog
843;
844; GFX10GISEL-LABEL: sample_g16_noa16_cd_cl_2d:
845; GFX10GISEL:       ; %bb.0: ; %main_body
846; GFX10GISEL-NEXT:    v_mov_b32_e32 v7, 0xffff
847; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
848; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
849; GFX10GISEL-NEXT:    v_and_or_b32 v0, v0, v7, v1
850; GFX10GISEL-NEXT:    v_and_or_b32 v1, v2, v7, v3
851; GFX10GISEL-NEXT:    image_sample_cd_cl_g16 v[0:3], [v0, v1, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
852; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
853; GFX10GISEL-NEXT:    ; return to shader part epilog
854main_body:
855  %v = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
856  ret <4 x float> %v
857}
858
859define amdgpu_ps <4 x float> @sample_g16_noa16_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp) {
860; GFX10-LABEL: sample_g16_noa16_c_cd_cl_1d:
861; GFX10:       ; %bb.0: ; %main_body
862; GFX10-NEXT:    image_sample_c_cd_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
863; GFX10-NEXT:    s_waitcnt vmcnt(0)
864; GFX10-NEXT:    ; return to shader part epilog
865;
866; GFX10GISEL-LABEL: sample_g16_noa16_c_cd_cl_1d:
867; GFX10GISEL:       ; %bb.0: ; %main_body
868; GFX10GISEL-NEXT:    v_mov_b32_e32 v5, 0xffff
869; GFX10GISEL-NEXT:    s_lshl_b32 s12, s0, 16
870; GFX10GISEL-NEXT:    v_and_or_b32 v1, v1, v5, s12
871; GFX10GISEL-NEXT:    v_and_or_b32 v2, v2, v5, s12
872; GFX10GISEL-NEXT:    image_sample_c_cd_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
873; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
874; GFX10GISEL-NEXT:    ; return to shader part epilog
875main_body:
876  %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
877  ret <4 x float> %v
878}
879
880define amdgpu_ps <4 x float> @sample_g16_noa16_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) {
881; GFX10-LABEL: sample_g16_noa16_c_cd_cl_2d:
882; GFX10:       ; %bb.0: ; %main_body
883; GFX10-NEXT:    v_mov_b32_e32 v8, v2
884; GFX10-NEXT:    v_mov_b32_e32 v2, v0
885; GFX10-NEXT:    v_mov_b32_e32 v0, 0xffff
886; GFX10-NEXT:    v_and_b32_e32 v3, v0, v3
887; GFX10-NEXT:    v_and_b32_e32 v0, v0, v1
888; GFX10-NEXT:    v_lshl_or_b32 v4, v4, 16, v3
889; GFX10-NEXT:    v_lshl_or_b32 v3, v8, 16, v0
890; GFX10-NEXT:    image_sample_c_cd_cl_g16 v[0:3], v[2:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
891; GFX10-NEXT:    s_waitcnt vmcnt(0)
892; GFX10-NEXT:    ; return to shader part epilog
893;
894; GFX10GISEL-LABEL: sample_g16_noa16_c_cd_cl_2d:
895; GFX10GISEL:       ; %bb.0: ; %main_body
896; GFX10GISEL-NEXT:    v_mov_b32_e32 v8, v2
897; GFX10GISEL-NEXT:    v_mov_b32_e32 v9, v3
898; GFX10GISEL-NEXT:    v_mov_b32_e32 v2, v0
899; GFX10GISEL-NEXT:    v_mov_b32_e32 v0, 0xffff
900; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
901; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v3, 16, v8
902; GFX10GISEL-NEXT:    v_and_or_b32 v4, v9, v0, v4
903; GFX10GISEL-NEXT:    v_and_or_b32 v3, v1, v0, v3
904; GFX10GISEL-NEXT:    image_sample_c_cd_cl_g16 v[0:3], v[2:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
905; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
906; GFX10GISEL-NEXT:    ; return to shader part epilog
907main_body:
908  %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
909  ret <4 x float> %v
910}
911
912define amdgpu_ps float @sample_g16_noa16_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice) {
913; GFX10-LABEL: sample_g16_noa16_c_d_o_2darray_V1:
914; GFX10:       ; %bb.0: ; %main_body
915; GFX10-NEXT:    v_mov_b32_e32 v9, v2
916; GFX10-NEXT:    v_mov_b32_e32 v2, v0
917; GFX10-NEXT:    v_mov_b32_e32 v0, 0xffff
918; GFX10-NEXT:    v_mov_b32_e32 v10, v3
919; GFX10-NEXT:    v_mov_b32_e32 v3, v1
920; GFX10-NEXT:    v_and_b32_e32 v1, v0, v4
921; GFX10-NEXT:    v_and_b32_e32 v0, v0, v9
922; GFX10-NEXT:    v_lshl_or_b32 v5, v5, 16, v1
923; GFX10-NEXT:    v_lshl_or_b32 v4, v10, 16, v0
924; GFX10-NEXT:    image_sample_c_d_o_g16 v0, v[2:8], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
925; GFX10-NEXT:    s_waitcnt vmcnt(0)
926; GFX10-NEXT:    ; return to shader part epilog
927;
928; GFX10GISEL-LABEL: sample_g16_noa16_c_d_o_2darray_V1:
929; GFX10GISEL:       ; %bb.0: ; %main_body
930; GFX10GISEL-NEXT:    v_mov_b32_e32 v9, v3
931; GFX10GISEL-NEXT:    v_mov_b32_e32 v10, v2
932; GFX10GISEL-NEXT:    v_mov_b32_e32 v11, v4
933; GFX10GISEL-NEXT:    v_mov_b32_e32 v2, v0
934; GFX10GISEL-NEXT:    v_mov_b32_e32 v3, v1
935; GFX10GISEL-NEXT:    v_mov_b32_e32 v0, 0xffff
936; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v1, 16, v9
937; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
938; GFX10GISEL-NEXT:    v_and_or_b32 v4, v10, v0, v1
939; GFX10GISEL-NEXT:    v_and_or_b32 v5, v11, v0, v5
940; GFX10GISEL-NEXT:    image_sample_c_d_o_g16 v0, v[2:8], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
941; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
942; GFX10GISEL-NEXT:    ; return to shader part epilog
943main_body:
944  %v = call float @llvm.amdgcn.image.sample.c.d.o.2darray.f32.f16.f32(i32 4, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
945  ret float %v
946}
947
948define amdgpu_ps <2 x float> @sample_g16_noa16_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice) {
949; GFX10-LABEL: sample_g16_noa16_c_d_o_2darray_V2:
950; GFX10:       ; %bb.0: ; %main_body
951; GFX10-NEXT:    v_mov_b32_e32 v9, v2
952; GFX10-NEXT:    v_mov_b32_e32 v2, v0
953; GFX10-NEXT:    v_mov_b32_e32 v0, 0xffff
954; GFX10-NEXT:    v_mov_b32_e32 v10, v3
955; GFX10-NEXT:    v_mov_b32_e32 v3, v1
956; GFX10-NEXT:    v_and_b32_e32 v1, v0, v4
957; GFX10-NEXT:    v_and_b32_e32 v0, v0, v9
958; GFX10-NEXT:    v_lshl_or_b32 v5, v5, 16, v1
959; GFX10-NEXT:    v_lshl_or_b32 v4, v10, 16, v0
960; GFX10-NEXT:    image_sample_c_d_o_g16 v[0:1], v[2:8], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY
961; GFX10-NEXT:    s_waitcnt vmcnt(0)
962; GFX10-NEXT:    ; return to shader part epilog
963;
964; GFX10GISEL-LABEL: sample_g16_noa16_c_d_o_2darray_V2:
965; GFX10GISEL:       ; %bb.0: ; %main_body
966; GFX10GISEL-NEXT:    v_mov_b32_e32 v9, v3
967; GFX10GISEL-NEXT:    v_mov_b32_e32 v10, v2
968; GFX10GISEL-NEXT:    v_mov_b32_e32 v11, v4
969; GFX10GISEL-NEXT:    v_mov_b32_e32 v2, v0
970; GFX10GISEL-NEXT:    v_mov_b32_e32 v3, v1
971; GFX10GISEL-NEXT:    v_mov_b32_e32 v0, 0xffff
972; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v1, 16, v9
973; GFX10GISEL-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
974; GFX10GISEL-NEXT:    v_and_or_b32 v4, v10, v0, v1
975; GFX10GISEL-NEXT:    v_and_or_b32 v5, v11, v0, v5
976; GFX10GISEL-NEXT:    image_sample_c_d_o_g16 v[0:1], v[2:8], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY
977; GFX10GISEL-NEXT:    s_waitcnt vmcnt(0)
978; GFX10GISEL-NEXT:    ; return to shader part epilog
979main_body:
980  %v = call <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f16.f32(i32 6, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
981  ret <2 x float> %v
982}
983
984declare <4 x float> @llvm.amdgcn.image.sample.d.1d.v4f32.f16.f32(i32, half, half, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
985declare <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f16.f32(i32, half, half, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
986declare <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f16.f32(i32, half, half, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
987declare <4 x float> @llvm.amdgcn.image.sample.c.d.1d.v4f32.f16.f32(i32, float, half, half, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
988declare <4 x float> @llvm.amdgcn.image.sample.c.d.2d.v4f32.f16.f32(i32, float, half, half, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
989declare <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f16.f32(i32, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
990declare <4 x float> @llvm.amdgcn.image.sample.d.cl.2d.v4f32.f16.f32(i32, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
991declare <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f16.f32(i32, float, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
992declare <4 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v4f32.f16.f32(i32, float, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
993
994declare <4 x float> @llvm.amdgcn.image.sample.cd.1d.v4f32.f16.f32(i32, half, half, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
995declare <4 x float> @llvm.amdgcn.image.sample.cd.2d.v4f32.f16.f32(i32, half, half, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
996declare <4 x float> @llvm.amdgcn.image.sample.c.cd.1d.v4f32.f16.f32(i32, float, half, half, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
997declare <4 x float> @llvm.amdgcn.image.sample.c.cd.2d.v4f32.f16.f32(i32, float, half, half, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
998declare <4 x float> @llvm.amdgcn.image.sample.cd.cl.1d.v4f32.f16.f32(i32, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
999declare <4 x float> @llvm.amdgcn.image.sample.cd.cl.2d.v4f32.f16.f32(i32, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
1000declare <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.1d.v4f32.f16.f32(i32, float, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
1001declare <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.2d.v4f32.f16.f32(i32, float, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
1002
1003declare float @llvm.amdgcn.image.sample.c.d.o.2darray.f32.f16.f32(i32, i32, float, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
1004declare <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f16.f32(i32, i32, float, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
1005
1006attributes #0 = { nounwind }
1007attributes #1 = { nounwind readonly }
1008attributes #2 = { nounwind readnone }
1009