1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10 %s 3; RUN: llc -march=amdgcn -mcpu=gfx1010 -global-isel -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10GISEL %s 4; TODO: global-isel produces more code - there will need to be some more combines in the postregbankselectcombine phase 5; Depends on some other changes to pass this test - those are in review separately 6 7define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dsdv, half %s) { 8; GFX10-LABEL: sample_d_1d: 9; GFX10: ; %bb.0: ; %main_body 10; GFX10-NEXT: image_sample_d v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 11; GFX10-NEXT: s_waitcnt vmcnt(0) 12; GFX10-NEXT: ; return to shader part epilog 13; 14; GFX10GISEL-LABEL: sample_d_1d: 15; GFX10GISEL: ; %bb.0: ; %main_body 16; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16 17; GFX10GISEL-NEXT: v_and_or_b32 v2, 0xffff, v2, s12 18; GFX10GISEL-NEXT: image_sample_d v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 19; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 20; GFX10GISEL-NEXT: ; return to shader part epilog 21main_body: 22 %v = call <4 x float> @llvm.amdgcn.image.sample.d.1d.v4f32.f32.f16(i32 15, float %dsdh, float %dsdv, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 23 ret <4 x float> %v 24} 25 26define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t) { 27; GFX10-LABEL: sample_d_2d: 28; GFX10: ; %bb.0: ; %main_body 29; GFX10-NEXT: v_and_b32_e32 v4, 0xffff, v4 30; GFX10-NEXT: v_lshl_or_b32 v4, v5, 16, v4 31; GFX10-NEXT: image_sample_d v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 32; GFX10-NEXT: s_waitcnt vmcnt(0) 33; GFX10-NEXT: ; return to shader part epilog 34; 35; GFX10GISEL-LABEL: sample_d_2d: 36; GFX10GISEL: ; %bb.0: ; %main_body 37; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v5, 16, v5 38; GFX10GISEL-NEXT: v_and_or_b32 v4, 0xffff, v4, v5 39; GFX10GISEL-NEXT: image_sample_d v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 40; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 41; GFX10GISEL-NEXT: ; return to shader part epilog 42main_body: 43 %v = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32.f16(i32 15, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 44 ret <4 x float> %v 45} 46 47define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dtdh, float %drdh, float %dsdv, float %dtdv, float %drdv, half %s, half %t, half %r) { 48; GFX10-LABEL: sample_d_3d: 49; GFX10: ; %bb.0: ; %main_body 50; GFX10-NEXT: v_mov_b32_e32 v15, v8 51; GFX10-NEXT: v_mov_b32_e32 v8, v0 52; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v6 53; GFX10-NEXT: v_mov_b32_e32 v13, v5 54; GFX10-NEXT: v_mov_b32_e32 v12, v4 55; GFX10-NEXT: v_mov_b32_e32 v11, v3 56; GFX10-NEXT: v_mov_b32_e32 v10, v2 57; GFX10-NEXT: v_mov_b32_e32 v9, v1 58; GFX10-NEXT: v_lshl_or_b32 v14, v7, 16, v0 59; GFX10-NEXT: image_sample_d v[0:3], v[8:15], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16 60; GFX10-NEXT: s_waitcnt vmcnt(0) 61; GFX10-NEXT: ; return to shader part epilog 62; 63; GFX10GISEL-LABEL: sample_d_3d: 64; GFX10GISEL: ; %bb.0: ; %main_body 65; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v7, 16, v7 66; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16 67; GFX10GISEL-NEXT: v_and_or_b32 v6, 0xffff, v6, v7 68; GFX10GISEL-NEXT: v_and_or_b32 v7, 0xffff, v8, s12 69; GFX10GISEL-NEXT: image_sample_d v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16 70; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 71; GFX10GISEL-NEXT: ; return to shader part epilog 72main_body: 73 %v = call <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f32.f16(i32 15, float %dsdh, float %dtdh, float %drdh, float %dsdv, float %dtdv, float %drdv, half %s, half %t, half %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 74 ret <4 x float> %v 75} 76 77define amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dsdv, half %s) { 78; GFX10-LABEL: sample_c_d_1d: 79; GFX10: ; %bb.0: ; %main_body 80; GFX10-NEXT: image_sample_c_d v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 81; GFX10-NEXT: s_waitcnt vmcnt(0) 82; GFX10-NEXT: ; return to shader part epilog 83; 84; GFX10GISEL-LABEL: sample_c_d_1d: 85; GFX10GISEL: ; %bb.0: ; %main_body 86; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16 87; GFX10GISEL-NEXT: v_and_or_b32 v3, 0xffff, v3, s12 88; GFX10GISEL-NEXT: image_sample_c_d v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 89; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 90; GFX10GISEL-NEXT: ; return to shader part epilog 91main_body: 92 %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.1d.v4f32.f32.f16(i32 15, float %zcompare, float %dsdh, float %dsdv, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 93 ret <4 x float> %v 94} 95 96define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t) { 97; GFX10-LABEL: sample_c_d_2d: 98; GFX10: ; %bb.0: ; %main_body 99; GFX10-NEXT: v_and_b32_e32 v5, 0xffff, v5 100; GFX10-NEXT: v_lshl_or_b32 v5, v6, 16, v5 101; GFX10-NEXT: image_sample_c_d v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 102; GFX10-NEXT: s_waitcnt vmcnt(0) 103; GFX10-NEXT: ; return to shader part epilog 104; 105; GFX10GISEL-LABEL: sample_c_d_2d: 106; GFX10GISEL: ; %bb.0: ; %main_body 107; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v6, 16, v6 108; GFX10GISEL-NEXT: v_and_or_b32 v5, 0xffff, v5, v6 109; GFX10GISEL-NEXT: image_sample_c_d v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 110; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 111; GFX10GISEL-NEXT: ; return to shader part epilog 112main_body: 113 %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.2d.v4f32.f32.f16(i32 15, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 114 ret <4 x float> %v 115} 116 117define amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dsdv, half %s, half %clamp) { 118; GFX10-LABEL: sample_d_cl_1d: 119; GFX10: ; %bb.0: ; %main_body 120; GFX10-NEXT: v_and_b32_e32 v2, 0xffff, v2 121; GFX10-NEXT: v_lshl_or_b32 v2, v3, 16, v2 122; GFX10-NEXT: image_sample_d_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 123; GFX10-NEXT: s_waitcnt vmcnt(0) 124; GFX10-NEXT: ; return to shader part epilog 125; 126; GFX10GISEL-LABEL: sample_d_cl_1d: 127; GFX10GISEL: ; %bb.0: ; %main_body 128; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v3, 16, v3 129; GFX10GISEL-NEXT: v_and_or_b32 v2, 0xffff, v2, v3 130; GFX10GISEL-NEXT: image_sample_d_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 131; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 132; GFX10GISEL-NEXT: ; return to shader part epilog 133main_body: 134 %v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f32.f16(i32 15, float %dsdh, float %dsdv, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 135 ret <4 x float> %v 136} 137 138define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %clamp) { 139; GFX10-LABEL: sample_d_cl_2d: 140; GFX10: ; %bb.0: ; %main_body 141; GFX10-NEXT: v_mov_b32_e32 v11, v6 142; GFX10-NEXT: v_mov_b32_e32 v6, v0 143; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v4 144; GFX10-NEXT: v_mov_b32_e32 v9, v3 145; GFX10-NEXT: v_mov_b32_e32 v8, v2 146; GFX10-NEXT: v_mov_b32_e32 v7, v1 147; GFX10-NEXT: v_lshl_or_b32 v10, v5, 16, v0 148; GFX10-NEXT: image_sample_d_cl v[0:3], v[6:11], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 149; GFX10-NEXT: s_waitcnt vmcnt(0) 150; GFX10-NEXT: ; return to shader part epilog 151; 152; GFX10GISEL-LABEL: sample_d_cl_2d: 153; GFX10GISEL: ; %bb.0: ; %main_body 154; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v5, 16, v5 155; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16 156; GFX10GISEL-NEXT: v_and_or_b32 v4, 0xffff, v4, v5 157; GFX10GISEL-NEXT: v_and_or_b32 v5, 0xffff, v6, s12 158; GFX10GISEL-NEXT: image_sample_d_cl v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 159; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 160; GFX10GISEL-NEXT: ; return to shader part epilog 161main_body: 162 %v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.2d.v4f32.f32.f16(i32 15, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 163 ret <4 x float> %v 164} 165 166define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dsdv, half %s, half %clamp) { 167; GFX10-LABEL: sample_c_d_cl_1d: 168; GFX10: ; %bb.0: ; %main_body 169; GFX10-NEXT: v_and_b32_e32 v3, 0xffff, v3 170; GFX10-NEXT: v_lshl_or_b32 v3, v4, 16, v3 171; GFX10-NEXT: image_sample_c_d_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 172; GFX10-NEXT: s_waitcnt vmcnt(0) 173; GFX10-NEXT: ; return to shader part epilog 174; 175; GFX10GISEL-LABEL: sample_c_d_cl_1d: 176; GFX10GISEL: ; %bb.0: ; %main_body 177; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v4, 16, v4 178; GFX10GISEL-NEXT: v_and_or_b32 v3, 0xffff, v3, v4 179; GFX10GISEL-NEXT: image_sample_c_d_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 180; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 181; GFX10GISEL-NEXT: ; return to shader part epilog 182main_body: 183 %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f32.f16(i32 15, float %zcompare, float %dsdh, float %dsdv, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 184 ret <4 x float> %v 185} 186 187define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %clamp) { 188; GFX10-LABEL: sample_c_d_cl_2d: 189; GFX10: ; %bb.0: ; %main_body 190; GFX10-NEXT: v_mov_b32_e32 v13, v7 191; GFX10-NEXT: v_mov_b32_e32 v7, v0 192; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v5 193; GFX10-NEXT: v_mov_b32_e32 v11, v4 194; GFX10-NEXT: v_mov_b32_e32 v10, v3 195; GFX10-NEXT: v_mov_b32_e32 v9, v2 196; GFX10-NEXT: v_mov_b32_e32 v8, v1 197; GFX10-NEXT: v_lshl_or_b32 v12, v6, 16, v0 198; GFX10-NEXT: image_sample_c_d_cl v[0:3], v[7:13], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 199; GFX10-NEXT: s_waitcnt vmcnt(0) 200; GFX10-NEXT: ; return to shader part epilog 201; 202; GFX10GISEL-LABEL: sample_c_d_cl_2d: 203; GFX10GISEL: ; %bb.0: ; %main_body 204; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v6, 16, v6 205; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16 206; GFX10GISEL-NEXT: v_and_or_b32 v5, 0xffff, v5, v6 207; GFX10GISEL-NEXT: v_and_or_b32 v6, 0xffff, v7, s12 208; GFX10GISEL-NEXT: image_sample_c_d_cl v[0:3], v[0:6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 209; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 210; GFX10GISEL-NEXT: ; return to shader part epilog 211main_body: 212 %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v4f32.f32.f16(i32 15, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 213 ret <4 x float> %v 214} 215 216define amdgpu_ps <4 x float> @sample_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dsdv, half %s) { 217; GFX10-LABEL: sample_cd_1d: 218; GFX10: ; %bb.0: ; %main_body 219; GFX10-NEXT: image_sample_cd v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 220; GFX10-NEXT: s_waitcnt vmcnt(0) 221; GFX10-NEXT: ; return to shader part epilog 222; 223; GFX10GISEL-LABEL: sample_cd_1d: 224; GFX10GISEL: ; %bb.0: ; %main_body 225; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16 226; GFX10GISEL-NEXT: v_and_or_b32 v2, 0xffff, v2, s12 227; GFX10GISEL-NEXT: image_sample_cd v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 228; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 229; GFX10GISEL-NEXT: ; return to shader part epilog 230main_body: 231 %v = call <4 x float> @llvm.amdgcn.image.sample.cd.1d.v4f32.f32.f16(i32 15, float %dsdh, float %dsdv, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 232 ret <4 x float> %v 233} 234 235define amdgpu_ps <4 x float> @sample_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t) { 236; GFX10-LABEL: sample_cd_2d: 237; GFX10: ; %bb.0: ; %main_body 238; GFX10-NEXT: v_and_b32_e32 v4, 0xffff, v4 239; GFX10-NEXT: v_lshl_or_b32 v4, v5, 16, v4 240; GFX10-NEXT: image_sample_cd v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 241; GFX10-NEXT: s_waitcnt vmcnt(0) 242; GFX10-NEXT: ; return to shader part epilog 243; 244; GFX10GISEL-LABEL: sample_cd_2d: 245; GFX10GISEL: ; %bb.0: ; %main_body 246; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v5, 16, v5 247; GFX10GISEL-NEXT: v_and_or_b32 v4, 0xffff, v4, v5 248; GFX10GISEL-NEXT: image_sample_cd v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 249; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 250; GFX10GISEL-NEXT: ; return to shader part epilog 251main_body: 252 %v = call <4 x float> @llvm.amdgcn.image.sample.cd.2d.v4f32.f32.f16(i32 15, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 253 ret <4 x float> %v 254} 255 256define amdgpu_ps <4 x float> @sample_c_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dsdv, half %s) { 257; GFX10-LABEL: sample_c_cd_1d: 258; GFX10: ; %bb.0: ; %main_body 259; GFX10-NEXT: image_sample_c_cd v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 260; GFX10-NEXT: s_waitcnt vmcnt(0) 261; GFX10-NEXT: ; return to shader part epilog 262; 263; GFX10GISEL-LABEL: sample_c_cd_1d: 264; GFX10GISEL: ; %bb.0: ; %main_body 265; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16 266; GFX10GISEL-NEXT: v_and_or_b32 v3, 0xffff, v3, s12 267; GFX10GISEL-NEXT: image_sample_c_cd v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 268; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 269; GFX10GISEL-NEXT: ; return to shader part epilog 270main_body: 271 %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.1d.v4f32.f32.f16(i32 15, float %zcompare, float %dsdh, float %dsdv, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 272 ret <4 x float> %v 273} 274 275define amdgpu_ps <4 x float> @sample_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t) { 276; GFX10-LABEL: sample_c_cd_2d: 277; GFX10: ; %bb.0: ; %main_body 278; GFX10-NEXT: v_and_b32_e32 v5, 0xffff, v5 279; GFX10-NEXT: v_lshl_or_b32 v5, v6, 16, v5 280; GFX10-NEXT: image_sample_c_cd v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 281; GFX10-NEXT: s_waitcnt vmcnt(0) 282; GFX10-NEXT: ; return to shader part epilog 283; 284; GFX10GISEL-LABEL: sample_c_cd_2d: 285; GFX10GISEL: ; %bb.0: ; %main_body 286; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v6, 16, v6 287; GFX10GISEL-NEXT: v_and_or_b32 v5, 0xffff, v5, v6 288; GFX10GISEL-NEXT: image_sample_c_cd v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 289; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 290; GFX10GISEL-NEXT: ; return to shader part epilog 291main_body: 292 %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.2d.v4f32.f32.f16(i32 15, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 293 ret <4 x float> %v 294} 295 296define amdgpu_ps <4 x float> @sample_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dsdv, half %s, half %clamp) { 297; GFX10-LABEL: sample_cd_cl_1d: 298; GFX10: ; %bb.0: ; %main_body 299; GFX10-NEXT: v_and_b32_e32 v2, 0xffff, v2 300; GFX10-NEXT: v_lshl_or_b32 v2, v3, 16, v2 301; GFX10-NEXT: image_sample_cd_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 302; GFX10-NEXT: s_waitcnt vmcnt(0) 303; GFX10-NEXT: ; return to shader part epilog 304; 305; GFX10GISEL-LABEL: sample_cd_cl_1d: 306; GFX10GISEL: ; %bb.0: ; %main_body 307; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v3, 16, v3 308; GFX10GISEL-NEXT: v_and_or_b32 v2, 0xffff, v2, v3 309; GFX10GISEL-NEXT: image_sample_cd_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 310; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 311; GFX10GISEL-NEXT: ; return to shader part epilog 312main_body: 313 %v = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.1d.v4f32.f32.f16(i32 15, float %dsdh, float %dsdv, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 314 ret <4 x float> %v 315} 316 317define amdgpu_ps <4 x float> @sample_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %clamp) { 318; GFX10-LABEL: sample_cd_cl_2d: 319; GFX10: ; %bb.0: ; %main_body 320; GFX10-NEXT: v_mov_b32_e32 v11, v6 321; GFX10-NEXT: v_mov_b32_e32 v6, v0 322; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v4 323; GFX10-NEXT: v_mov_b32_e32 v9, v3 324; GFX10-NEXT: v_mov_b32_e32 v8, v2 325; GFX10-NEXT: v_mov_b32_e32 v7, v1 326; GFX10-NEXT: v_lshl_or_b32 v10, v5, 16, v0 327; GFX10-NEXT: image_sample_cd_cl v[0:3], v[6:11], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 328; GFX10-NEXT: s_waitcnt vmcnt(0) 329; GFX10-NEXT: ; return to shader part epilog 330; 331; GFX10GISEL-LABEL: sample_cd_cl_2d: 332; GFX10GISEL: ; %bb.0: ; %main_body 333; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v5, 16, v5 334; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16 335; GFX10GISEL-NEXT: v_and_or_b32 v4, 0xffff, v4, v5 336; GFX10GISEL-NEXT: v_and_or_b32 v5, 0xffff, v6, s12 337; GFX10GISEL-NEXT: image_sample_cd_cl v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 338; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 339; GFX10GISEL-NEXT: ; return to shader part epilog 340main_body: 341 %v = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.2d.v4f32.f32.f16(i32 15, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 342 ret <4 x float> %v 343} 344 345define amdgpu_ps <4 x float> @sample_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dsdv, half %s, half %clamp) { 346; GFX10-LABEL: sample_c_cd_cl_1d: 347; GFX10: ; %bb.0: ; %main_body 348; GFX10-NEXT: v_and_b32_e32 v3, 0xffff, v3 349; GFX10-NEXT: v_lshl_or_b32 v3, v4, 16, v3 350; GFX10-NEXT: image_sample_c_cd_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 351; GFX10-NEXT: s_waitcnt vmcnt(0) 352; GFX10-NEXT: ; return to shader part epilog 353; 354; GFX10GISEL-LABEL: sample_c_cd_cl_1d: 355; GFX10GISEL: ; %bb.0: ; %main_body 356; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v4, 16, v4 357; GFX10GISEL-NEXT: v_and_or_b32 v3, 0xffff, v3, v4 358; GFX10GISEL-NEXT: image_sample_c_cd_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 359; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 360; GFX10GISEL-NEXT: ; return to shader part epilog 361main_body: 362 %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.1d.v4f32.f32.f16(i32 15, float %zcompare, float %dsdh, float %dsdv, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 363 ret <4 x float> %v 364} 365 366define amdgpu_ps <4 x float> @sample_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %clamp) { 367; GFX10-LABEL: sample_c_cd_cl_2d: 368; GFX10: ; %bb.0: ; %main_body 369; GFX10-NEXT: v_mov_b32_e32 v13, v7 370; GFX10-NEXT: v_mov_b32_e32 v7, v0 371; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v5 372; GFX10-NEXT: v_mov_b32_e32 v11, v4 373; GFX10-NEXT: v_mov_b32_e32 v10, v3 374; GFX10-NEXT: v_mov_b32_e32 v9, v2 375; GFX10-NEXT: v_mov_b32_e32 v8, v1 376; GFX10-NEXT: v_lshl_or_b32 v12, v6, 16, v0 377; GFX10-NEXT: image_sample_c_cd_cl v[0:3], v[7:13], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 378; GFX10-NEXT: s_waitcnt vmcnt(0) 379; GFX10-NEXT: ; return to shader part epilog 380; 381; GFX10GISEL-LABEL: sample_c_cd_cl_2d: 382; GFX10GISEL: ; %bb.0: ; %main_body 383; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v6, 16, v6 384; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16 385; GFX10GISEL-NEXT: v_and_or_b32 v5, 0xffff, v5, v6 386; GFX10GISEL-NEXT: v_and_or_b32 v6, 0xffff, v7, s12 387; GFX10GISEL-NEXT: image_sample_c_cd_cl v[0:3], v[0:6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 388; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 389; GFX10GISEL-NEXT: ; return to shader part epilog 390main_body: 391 %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.2d.v4f32.f32.f16(i32 15, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 392 ret <4 x float> %v 393} 394 395define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %slice) { 396; GFX10-LABEL: sample_c_d_o_2darray_V1: 397; GFX10: ; %bb.0: ; %main_body 398; GFX10-NEXT: v_mov_b32_e32 v15, v8 399; GFX10-NEXT: v_mov_b32_e32 v8, v0 400; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v6 401; GFX10-NEXT: v_mov_b32_e32 v13, v5 402; GFX10-NEXT: v_mov_b32_e32 v12, v4 403; GFX10-NEXT: v_mov_b32_e32 v11, v3 404; GFX10-NEXT: v_mov_b32_e32 v10, v2 405; GFX10-NEXT: v_mov_b32_e32 v9, v1 406; GFX10-NEXT: v_lshl_or_b32 v14, v7, 16, v0 407; GFX10-NEXT: image_sample_c_d_o v0, v[8:15], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16 408; GFX10-NEXT: s_waitcnt vmcnt(0) 409; GFX10-NEXT: ; return to shader part epilog 410; 411; GFX10GISEL-LABEL: sample_c_d_o_2darray_V1: 412; GFX10GISEL: ; %bb.0: ; %main_body 413; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v7, 16, v7 414; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16 415; GFX10GISEL-NEXT: v_and_or_b32 v6, 0xffff, v6, v7 416; GFX10GISEL-NEXT: v_and_or_b32 v7, 0xffff, v8, s12 417; GFX10GISEL-NEXT: image_sample_c_d_o v0, v[0:7], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16 418; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 419; GFX10GISEL-NEXT: ; return to shader part epilog 420main_body: 421 %v = call float @llvm.amdgcn.image.sample.c.d.o.2darray.f32.f32.f16(i32 4, i32 %offset, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 422 ret float %v 423} 424 425define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %slice) { 426; GFX10-LABEL: sample_c_d_o_2darray_V2: 427; GFX10: ; %bb.0: ; %main_body 428; GFX10-NEXT: v_mov_b32_e32 v15, v8 429; GFX10-NEXT: v_mov_b32_e32 v8, v0 430; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v6 431; GFX10-NEXT: v_mov_b32_e32 v13, v5 432; GFX10-NEXT: v_mov_b32_e32 v12, v4 433; GFX10-NEXT: v_mov_b32_e32 v11, v3 434; GFX10-NEXT: v_mov_b32_e32 v10, v2 435; GFX10-NEXT: v_mov_b32_e32 v9, v1 436; GFX10-NEXT: v_lshl_or_b32 v14, v7, 16, v0 437; GFX10-NEXT: image_sample_c_d_o v[0:1], v[8:15], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY a16 438; GFX10-NEXT: s_waitcnt vmcnt(0) 439; GFX10-NEXT: ; return to shader part epilog 440; 441; GFX10GISEL-LABEL: sample_c_d_o_2darray_V2: 442; GFX10GISEL: ; %bb.0: ; %main_body 443; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v7, 16, v7 444; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16 445; GFX10GISEL-NEXT: v_and_or_b32 v6, 0xffff, v6, v7 446; GFX10GISEL-NEXT: v_and_or_b32 v7, 0xffff, v8, s12 447; GFX10GISEL-NEXT: image_sample_c_d_o v[0:1], v[0:7], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY a16 448; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 449; GFX10GISEL-NEXT: ; return to shader part epilog 450main_body: 451 %v = call <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f32.f16(i32 6, i32 %offset, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, half %s, half %t, half %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 452 ret <2 x float> %v 453} 454 455declare <4 x float> @llvm.amdgcn.image.sample.d.1d.v4f32.f32.f16(i32, float, float, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1 456declare <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32.f16(i32, float, float, float, float, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1 457declare <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f32.f16(i32, float, float, float, float, float, float, half, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1 458declare <4 x float> @llvm.amdgcn.image.sample.c.d.1d.v4f32.f32.f16(i32, float, float, float, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1 459declare <4 x float> @llvm.amdgcn.image.sample.c.d.2d.v4f32.f32.f16(i32, float, float, float, float, float, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1 460declare <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f32.f16(i32, float, float, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1 461declare <4 x float> @llvm.amdgcn.image.sample.d.cl.2d.v4f32.f32.f16(i32, float, float, float, float, half, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1 462declare <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f32.f16(i32, float, float, float, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1 463declare <4 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v4f32.f32.f16(i32, float, float, float, float, float, half, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1 464 465declare <4 x float> @llvm.amdgcn.image.sample.cd.1d.v4f32.f32.f16(i32, float, float, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1 466declare <4 x float> @llvm.amdgcn.image.sample.cd.2d.v4f32.f32.f16(i32, float, float, float, float, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1 467declare <4 x float> @llvm.amdgcn.image.sample.c.cd.1d.v4f32.f32.f16(i32, float, float, float, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1 468declare <4 x float> @llvm.amdgcn.image.sample.c.cd.2d.v4f32.f32.f16(i32, float, float, float, float, float, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1 469declare <4 x float> @llvm.amdgcn.image.sample.cd.cl.1d.v4f32.f32.f16(i32, float, float, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1 470declare <4 x float> @llvm.amdgcn.image.sample.cd.cl.2d.v4f32.f32.f16(i32, float, float, float, float, half, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1 471declare <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.1d.v4f32.f32.f16(i32, float, float, float, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1 472declare <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.2d.v4f32.f32.f16(i32, float, float, float, float, float, half, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1 473 474declare float @llvm.amdgcn.image.sample.c.d.o.2darray.f32.f32.f16(i32, i32, float, float, float, float, float, half, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1 475declare <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f32.f16(i32, i32, float, float, float, float, float, half, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1 476 477define amdgpu_ps <4 x float> @sample_g16_noa16_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s) { 478; GFX10-LABEL: sample_g16_noa16_d_1d: 479; GFX10: ; %bb.0: ; %main_body 480; GFX10-NEXT: image_sample_d_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D 481; GFX10-NEXT: s_waitcnt vmcnt(0) 482; GFX10-NEXT: ; return to shader part epilog 483; 484; GFX10GISEL-LABEL: sample_g16_noa16_d_1d: 485; GFX10GISEL: ; %bb.0: ; %main_body 486; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16 487; GFX10GISEL-NEXT: v_and_or_b32 v0, 0xffff, v0, s12 488; GFX10GISEL-NEXT: v_and_or_b32 v1, 0xffff, v1, s12 489; GFX10GISEL-NEXT: image_sample_d_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D 490; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 491; GFX10GISEL-NEXT: ; return to shader part epilog 492main_body: 493 %v = call <4 x float> @llvm.amdgcn.image.sample.d.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 494 ret <4 x float> %v 495} 496 497define amdgpu_ps <4 x float> @sample_g16_noa16_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) { 498; GFX10-LABEL: sample_g16_noa16_d_2d: 499; GFX10: ; %bb.0: ; %main_body 500; GFX10-NEXT: v_and_b32_e32 v2, 0xffff, v2 501; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0 502; GFX10-NEXT: v_lshl_or_b32 v2, v3, 16, v2 503; GFX10-NEXT: v_lshl_or_b32 v0, v1, 16, v0 504; GFX10-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D 505; GFX10-NEXT: s_waitcnt vmcnt(0) 506; GFX10-NEXT: ; return to shader part epilog 507; 508; GFX10GISEL-LABEL: sample_g16_noa16_d_2d: 509; GFX10GISEL: ; %bb.0: ; %main_body 510; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1 511; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v3, 16, v3 512; GFX10GISEL-NEXT: v_and_or_b32 v0, 0xffff, v0, v1 513; GFX10GISEL-NEXT: v_and_or_b32 v1, 0xffff, v2, v3 514; GFX10GISEL-NEXT: image_sample_d_g16 v[0:3], [v0, v1, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D 515; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 516; GFX10GISEL-NEXT: ; return to shader part epilog 517main_body: 518 %v = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 519 ret <4 x float> %v 520} 521 522define amdgpu_ps <4 x float> @sample_g16_noa16_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %drdh, half %dsdv, half %dtdv, half %drdv, float %s, float %t, float %r) { 523; GFX10-LABEL: sample_g16_noa16_d_3d: 524; GFX10: ; %bb.0: ; %main_body 525; GFX10-NEXT: v_mov_b32_e32 v9, v3 526; GFX10-NEXT: v_mov_b32_e32 v3, v2 527; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0 528; GFX10-NEXT: v_and_b32_e32 v2, 0xffff, v9 529; GFX10-NEXT: v_lshl_or_b32 v4, v4, 16, v2 530; GFX10-NEXT: v_lshl_or_b32 v2, v1, 16, v0 531; GFX10-NEXT: image_sample_d_g16 v[0:3], v[2:8], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D 532; GFX10-NEXT: s_waitcnt vmcnt(0) 533; GFX10-NEXT: ; return to shader part epilog 534; 535; GFX10GISEL-LABEL: sample_g16_noa16_d_3d: 536; GFX10GISEL: ; %bb.0: ; %main_body 537; GFX10GISEL-NEXT: v_mov_b32_e32 v9, v2 538; GFX10GISEL-NEXT: v_mov_b32_e32 v10, v3 539; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1 540; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v4, 16, v4 541; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16 542; GFX10GISEL-NEXT: v_and_or_b32 v3, 0xffff, v9, s12 543; GFX10GISEL-NEXT: v_and_or_b32 v2, 0xffff, v0, v1 544; GFX10GISEL-NEXT: v_and_or_b32 v4, 0xffff, v10, v4 545; GFX10GISEL-NEXT: v_and_or_b32 v5, 0xffff, v5, s12 546; GFX10GISEL-NEXT: image_sample_d_g16 v[0:3], v[2:8], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D 547; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 548; GFX10GISEL-NEXT: ; return to shader part epilog 549main_body: 550 %v = call <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %drdh, half %dsdv, half %dtdv, half %drdv, float %s, float %t, float %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 551 ret <4 x float> %v 552} 553 554define amdgpu_ps <4 x float> @sample_g16_noa16_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s) { 555; GFX10-LABEL: sample_g16_noa16_c_d_1d: 556; GFX10: ; %bb.0: ; %main_body 557; GFX10-NEXT: image_sample_c_d_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D 558; GFX10-NEXT: s_waitcnt vmcnt(0) 559; GFX10-NEXT: ; return to shader part epilog 560; 561; GFX10GISEL-LABEL: sample_g16_noa16_c_d_1d: 562; GFX10GISEL: ; %bb.0: ; %main_body 563; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16 564; GFX10GISEL-NEXT: v_and_or_b32 v1, 0xffff, v1, s12 565; GFX10GISEL-NEXT: v_and_or_b32 v2, 0xffff, v2, s12 566; GFX10GISEL-NEXT: image_sample_c_d_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D 567; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 568; GFX10GISEL-NEXT: ; return to shader part epilog 569main_body: 570 %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 571 ret <4 x float> %v 572} 573 574define amdgpu_ps <4 x float> @sample_g16_noa16_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) { 575; GFX10-LABEL: sample_g16_noa16_c_d_2d: 576; GFX10: ; %bb.0: ; %main_body 577; GFX10-NEXT: v_and_b32_e32 v3, 0xffff, v3 578; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1 579; GFX10-NEXT: v_lshl_or_b32 v3, v4, 16, v3 580; GFX10-NEXT: v_lshl_or_b32 v1, v2, 16, v1 581; GFX10-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v3, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D 582; GFX10-NEXT: s_waitcnt vmcnt(0) 583; GFX10-NEXT: ; return to shader part epilog 584; 585; GFX10GISEL-LABEL: sample_g16_noa16_c_d_2d: 586; GFX10GISEL: ; %bb.0: ; %main_body 587; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v2, 16, v2 588; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v4, 16, v4 589; GFX10GISEL-NEXT: v_and_or_b32 v1, 0xffff, v1, v2 590; GFX10GISEL-NEXT: v_and_or_b32 v2, 0xffff, v3, v4 591; GFX10GISEL-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v2, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D 592; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 593; GFX10GISEL-NEXT: ; return to shader part epilog 594main_body: 595 %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 596 ret <4 x float> %v 597} 598 599define amdgpu_ps <4 x float> @sample_g16_noa16_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s, float %clamp) { 600; GFX10-LABEL: sample_g16_noa16_d_cl_1d: 601; GFX10: ; %bb.0: ; %main_body 602; GFX10-NEXT: image_sample_d_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D 603; GFX10-NEXT: s_waitcnt vmcnt(0) 604; GFX10-NEXT: ; return to shader part epilog 605; 606; GFX10GISEL-LABEL: sample_g16_noa16_d_cl_1d: 607; GFX10GISEL: ; %bb.0: ; %main_body 608; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16 609; GFX10GISEL-NEXT: v_and_or_b32 v0, 0xffff, v0, s12 610; GFX10GISEL-NEXT: v_and_or_b32 v1, 0xffff, v1, s12 611; GFX10GISEL-NEXT: image_sample_d_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D 612; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 613; GFX10GISEL-NEXT: ; return to shader part epilog 614main_body: 615 %v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 616 ret <4 x float> %v 617} 618 619define amdgpu_ps <4 x float> @sample_g16_noa16_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) { 620; GFX10-LABEL: sample_g16_noa16_d_cl_2d: 621; GFX10: ; %bb.0: ; %main_body 622; GFX10-NEXT: v_and_b32_e32 v2, 0xffff, v2 623; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0 624; GFX10-NEXT: v_lshl_or_b32 v2, v3, 16, v2 625; GFX10-NEXT: v_lshl_or_b32 v0, v1, 16, v0 626; GFX10-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D 627; GFX10-NEXT: s_waitcnt vmcnt(0) 628; GFX10-NEXT: ; return to shader part epilog 629; 630; GFX10GISEL-LABEL: sample_g16_noa16_d_cl_2d: 631; GFX10GISEL: ; %bb.0: ; %main_body 632; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1 633; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v3, 16, v3 634; GFX10GISEL-NEXT: v_and_or_b32 v0, 0xffff, v0, v1 635; GFX10GISEL-NEXT: v_and_or_b32 v1, 0xffff, v2, v3 636; GFX10GISEL-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v1, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D 637; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 638; GFX10GISEL-NEXT: ; return to shader part epilog 639main_body: 640 %v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 641 ret <4 x float> %v 642} 643 644define amdgpu_ps <4 x float> @sample_g16_noa16_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp) { 645; GFX10-LABEL: sample_g16_noa16_c_d_cl_1d: 646; GFX10: ; %bb.0: ; %main_body 647; GFX10-NEXT: image_sample_c_d_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D 648; GFX10-NEXT: s_waitcnt vmcnt(0) 649; GFX10-NEXT: ; return to shader part epilog 650; 651; GFX10GISEL-LABEL: sample_g16_noa16_c_d_cl_1d: 652; GFX10GISEL: ; %bb.0: ; %main_body 653; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16 654; GFX10GISEL-NEXT: v_and_or_b32 v1, 0xffff, v1, s12 655; GFX10GISEL-NEXT: v_and_or_b32 v2, 0xffff, v2, s12 656; GFX10GISEL-NEXT: image_sample_c_d_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D 657; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 658; GFX10GISEL-NEXT: ; return to shader part epilog 659main_body: 660 %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 661 ret <4 x float> %v 662} 663 664define amdgpu_ps <4 x float> @sample_g16_noa16_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) { 665; GFX10-LABEL: sample_g16_noa16_c_d_cl_2d: 666; GFX10: ; %bb.0: ; %main_body 667; GFX10-NEXT: v_mov_b32_e32 v8, v2 668; GFX10-NEXT: v_mov_b32_e32 v2, v0 669; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v3 670; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1 671; GFX10-NEXT: v_lshl_or_b32 v4, v4, 16, v0 672; GFX10-NEXT: v_lshl_or_b32 v3, v8, 16, v1 673; GFX10-NEXT: image_sample_c_d_cl_g16 v[0:3], v[2:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D 674; GFX10-NEXT: s_waitcnt vmcnt(0) 675; GFX10-NEXT: ; return to shader part epilog 676; 677; GFX10GISEL-LABEL: sample_g16_noa16_c_d_cl_2d: 678; GFX10GISEL: ; %bb.0: ; %main_body 679; GFX10GISEL-NEXT: v_mov_b32_e32 v8, v2 680; GFX10GISEL-NEXT: v_mov_b32_e32 v9, v3 681; GFX10GISEL-NEXT: v_mov_b32_e32 v2, v0 682; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v4, 16, v4 683; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v0, 16, v8 684; GFX10GISEL-NEXT: v_and_or_b32 v4, 0xffff, v9, v4 685; GFX10GISEL-NEXT: v_and_or_b32 v3, 0xffff, v1, v0 686; GFX10GISEL-NEXT: image_sample_c_d_cl_g16 v[0:3], v[2:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D 687; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 688; GFX10GISEL-NEXT: ; return to shader part epilog 689main_body: 690 %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 691 ret <4 x float> %v 692} 693 694define amdgpu_ps <4 x float> @sample_g16_noa16_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s) { 695; GFX10-LABEL: sample_g16_noa16_cd_1d: 696; GFX10: ; %bb.0: ; %main_body 697; GFX10-NEXT: image_sample_cd_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D 698; GFX10-NEXT: s_waitcnt vmcnt(0) 699; GFX10-NEXT: ; return to shader part epilog 700; 701; GFX10GISEL-LABEL: sample_g16_noa16_cd_1d: 702; GFX10GISEL: ; %bb.0: ; %main_body 703; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16 704; GFX10GISEL-NEXT: v_and_or_b32 v0, 0xffff, v0, s12 705; GFX10GISEL-NEXT: v_and_or_b32 v1, 0xffff, v1, s12 706; GFX10GISEL-NEXT: image_sample_cd_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D 707; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 708; GFX10GISEL-NEXT: ; return to shader part epilog 709main_body: 710 %v = call <4 x float> @llvm.amdgcn.image.sample.cd.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 711 ret <4 x float> %v 712} 713 714define amdgpu_ps <4 x float> @sample_g16_noa16_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) { 715; GFX10-LABEL: sample_g16_noa16_cd_2d: 716; GFX10: ; %bb.0: ; %main_body 717; GFX10-NEXT: v_and_b32_e32 v2, 0xffff, v2 718; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0 719; GFX10-NEXT: v_lshl_or_b32 v2, v3, 16, v2 720; GFX10-NEXT: v_lshl_or_b32 v0, v1, 16, v0 721; GFX10-NEXT: image_sample_cd_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D 722; GFX10-NEXT: s_waitcnt vmcnt(0) 723; GFX10-NEXT: ; return to shader part epilog 724; 725; GFX10GISEL-LABEL: sample_g16_noa16_cd_2d: 726; GFX10GISEL: ; %bb.0: ; %main_body 727; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1 728; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v3, 16, v3 729; GFX10GISEL-NEXT: v_and_or_b32 v0, 0xffff, v0, v1 730; GFX10GISEL-NEXT: v_and_or_b32 v1, 0xffff, v2, v3 731; GFX10GISEL-NEXT: image_sample_cd_g16 v[0:3], [v0, v1, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D 732; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 733; GFX10GISEL-NEXT: ; return to shader part epilog 734main_body: 735 %v = call <4 x float> @llvm.amdgcn.image.sample.cd.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 736 ret <4 x float> %v 737} 738 739define amdgpu_ps <4 x float> @sample_g16_noa16_c_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s) { 740; GFX10-LABEL: sample_g16_noa16_c_cd_1d: 741; GFX10: ; %bb.0: ; %main_body 742; GFX10-NEXT: image_sample_c_cd_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D 743; GFX10-NEXT: s_waitcnt vmcnt(0) 744; GFX10-NEXT: ; return to shader part epilog 745; 746; GFX10GISEL-LABEL: sample_g16_noa16_c_cd_1d: 747; GFX10GISEL: ; %bb.0: ; %main_body 748; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16 749; GFX10GISEL-NEXT: v_and_or_b32 v1, 0xffff, v1, s12 750; GFX10GISEL-NEXT: v_and_or_b32 v2, 0xffff, v2, s12 751; GFX10GISEL-NEXT: image_sample_c_cd_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D 752; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 753; GFX10GISEL-NEXT: ; return to shader part epilog 754main_body: 755 %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 756 ret <4 x float> %v 757} 758 759define amdgpu_ps <4 x float> @sample_g16_noa16_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) { 760; GFX10-LABEL: sample_g16_noa16_c_cd_2d: 761; GFX10: ; %bb.0: ; %main_body 762; GFX10-NEXT: v_and_b32_e32 v3, 0xffff, v3 763; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1 764; GFX10-NEXT: v_lshl_or_b32 v3, v4, 16, v3 765; GFX10-NEXT: v_lshl_or_b32 v1, v2, 16, v1 766; GFX10-NEXT: image_sample_c_cd_g16 v[0:3], [v0, v1, v3, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D 767; GFX10-NEXT: s_waitcnt vmcnt(0) 768; GFX10-NEXT: ; return to shader part epilog 769; 770; GFX10GISEL-LABEL: sample_g16_noa16_c_cd_2d: 771; GFX10GISEL: ; %bb.0: ; %main_body 772; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v2, 16, v2 773; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v4, 16, v4 774; GFX10GISEL-NEXT: v_and_or_b32 v1, 0xffff, v1, v2 775; GFX10GISEL-NEXT: v_and_or_b32 v2, 0xffff, v3, v4 776; GFX10GISEL-NEXT: image_sample_c_cd_g16 v[0:3], [v0, v1, v2, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D 777; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 778; GFX10GISEL-NEXT: ; return to shader part epilog 779main_body: 780 %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 781 ret <4 x float> %v 782} 783 784define amdgpu_ps <4 x float> @sample_g16_noa16_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s, float %clamp) { 785; GFX10-LABEL: sample_g16_noa16_cd_cl_1d: 786; GFX10: ; %bb.0: ; %main_body 787; GFX10-NEXT: image_sample_cd_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D 788; GFX10-NEXT: s_waitcnt vmcnt(0) 789; GFX10-NEXT: ; return to shader part epilog 790; 791; GFX10GISEL-LABEL: sample_g16_noa16_cd_cl_1d: 792; GFX10GISEL: ; %bb.0: ; %main_body 793; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16 794; GFX10GISEL-NEXT: v_and_or_b32 v0, 0xffff, v0, s12 795; GFX10GISEL-NEXT: v_and_or_b32 v1, 0xffff, v1, s12 796; GFX10GISEL-NEXT: image_sample_cd_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D 797; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 798; GFX10GISEL-NEXT: ; return to shader part epilog 799main_body: 800 %v = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 801 ret <4 x float> %v 802} 803 804define amdgpu_ps <4 x float> @sample_g16_noa16_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) { 805; GFX10-LABEL: sample_g16_noa16_cd_cl_2d: 806; GFX10: ; %bb.0: ; %main_body 807; GFX10-NEXT: v_and_b32_e32 v2, 0xffff, v2 808; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0 809; GFX10-NEXT: v_lshl_or_b32 v2, v3, 16, v2 810; GFX10-NEXT: v_lshl_or_b32 v0, v1, 16, v0 811; GFX10-NEXT: image_sample_cd_cl_g16 v[0:3], [v0, v2, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D 812; GFX10-NEXT: s_waitcnt vmcnt(0) 813; GFX10-NEXT: ; return to shader part epilog 814; 815; GFX10GISEL-LABEL: sample_g16_noa16_cd_cl_2d: 816; GFX10GISEL: ; %bb.0: ; %main_body 817; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1 818; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v3, 16, v3 819; GFX10GISEL-NEXT: v_and_or_b32 v0, 0xffff, v0, v1 820; GFX10GISEL-NEXT: v_and_or_b32 v1, 0xffff, v2, v3 821; GFX10GISEL-NEXT: image_sample_cd_cl_g16 v[0:3], [v0, v1, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D 822; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 823; GFX10GISEL-NEXT: ; return to shader part epilog 824main_body: 825 %v = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 826 ret <4 x float> %v 827} 828 829define amdgpu_ps <4 x float> @sample_g16_noa16_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp) { 830; GFX10-LABEL: sample_g16_noa16_c_cd_cl_1d: 831; GFX10: ; %bb.0: ; %main_body 832; GFX10-NEXT: image_sample_c_cd_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D 833; GFX10-NEXT: s_waitcnt vmcnt(0) 834; GFX10-NEXT: ; return to shader part epilog 835; 836; GFX10GISEL-LABEL: sample_g16_noa16_c_cd_cl_1d: 837; GFX10GISEL: ; %bb.0: ; %main_body 838; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16 839; GFX10GISEL-NEXT: v_and_or_b32 v1, 0xffff, v1, s12 840; GFX10GISEL-NEXT: v_and_or_b32 v2, 0xffff, v2, s12 841; GFX10GISEL-NEXT: image_sample_c_cd_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D 842; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 843; GFX10GISEL-NEXT: ; return to shader part epilog 844main_body: 845 %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 846 ret <4 x float> %v 847} 848 849define amdgpu_ps <4 x float> @sample_g16_noa16_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) { 850; GFX10-LABEL: sample_g16_noa16_c_cd_cl_2d: 851; GFX10: ; %bb.0: ; %main_body 852; GFX10-NEXT: v_mov_b32_e32 v8, v2 853; GFX10-NEXT: v_mov_b32_e32 v2, v0 854; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v3 855; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1 856; GFX10-NEXT: v_lshl_or_b32 v4, v4, 16, v0 857; GFX10-NEXT: v_lshl_or_b32 v3, v8, 16, v1 858; GFX10-NEXT: image_sample_c_cd_cl_g16 v[0:3], v[2:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D 859; GFX10-NEXT: s_waitcnt vmcnt(0) 860; GFX10-NEXT: ; return to shader part epilog 861; 862; GFX10GISEL-LABEL: sample_g16_noa16_c_cd_cl_2d: 863; GFX10GISEL: ; %bb.0: ; %main_body 864; GFX10GISEL-NEXT: v_mov_b32_e32 v8, v2 865; GFX10GISEL-NEXT: v_mov_b32_e32 v9, v3 866; GFX10GISEL-NEXT: v_mov_b32_e32 v2, v0 867; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v4, 16, v4 868; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v0, 16, v8 869; GFX10GISEL-NEXT: v_and_or_b32 v4, 0xffff, v9, v4 870; GFX10GISEL-NEXT: v_and_or_b32 v3, 0xffff, v1, v0 871; GFX10GISEL-NEXT: image_sample_c_cd_cl_g16 v[0:3], v[2:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D 872; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 873; GFX10GISEL-NEXT: ; return to shader part epilog 874main_body: 875 %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 876 ret <4 x float> %v 877} 878 879define amdgpu_ps float @sample_g16_noa16_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice) { 880; GFX10-LABEL: sample_g16_noa16_c_d_o_2darray_V1: 881; GFX10: ; %bb.0: ; %main_body 882; GFX10-NEXT: v_mov_b32_e32 v9, v2 883; GFX10-NEXT: v_mov_b32_e32 v10, v3 884; GFX10-NEXT: v_mov_b32_e32 v3, v1 885; GFX10-NEXT: v_mov_b32_e32 v2, v0 886; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v4 887; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v9 888; GFX10-NEXT: v_lshl_or_b32 v5, v5, 16, v0 889; GFX10-NEXT: v_lshl_or_b32 v4, v10, 16, v1 890; GFX10-NEXT: image_sample_c_d_o_g16 v0, v[2:8], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY 891; GFX10-NEXT: s_waitcnt vmcnt(0) 892; GFX10-NEXT: ; return to shader part epilog 893; 894; GFX10GISEL-LABEL: sample_g16_noa16_c_d_o_2darray_V1: 895; GFX10GISEL: ; %bb.0: ; %main_body 896; GFX10GISEL-NEXT: v_mov_b32_e32 v9, v3 897; GFX10GISEL-NEXT: v_mov_b32_e32 v10, v2 898; GFX10GISEL-NEXT: v_mov_b32_e32 v11, v4 899; GFX10GISEL-NEXT: v_mov_b32_e32 v2, v0 900; GFX10GISEL-NEXT: v_mov_b32_e32 v3, v1 901; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v0, 16, v9 902; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v5 903; GFX10GISEL-NEXT: v_and_or_b32 v4, 0xffff, v10, v0 904; GFX10GISEL-NEXT: v_and_or_b32 v5, 0xffff, v11, v1 905; GFX10GISEL-NEXT: image_sample_c_d_o_g16 v0, v[2:8], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY 906; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 907; GFX10GISEL-NEXT: ; return to shader part epilog 908main_body: 909 %v = call float @llvm.amdgcn.image.sample.c.d.o.2darray.f32.f16.f32(i32 4, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 910 ret float %v 911} 912 913define amdgpu_ps <2 x float> @sample_g16_noa16_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice) { 914; GFX10-LABEL: sample_g16_noa16_c_d_o_2darray_V2: 915; GFX10: ; %bb.0: ; %main_body 916; GFX10-NEXT: v_mov_b32_e32 v9, v2 917; GFX10-NEXT: v_mov_b32_e32 v10, v3 918; GFX10-NEXT: v_mov_b32_e32 v3, v1 919; GFX10-NEXT: v_mov_b32_e32 v2, v0 920; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v4 921; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v9 922; GFX10-NEXT: v_lshl_or_b32 v5, v5, 16, v0 923; GFX10-NEXT: v_lshl_or_b32 v4, v10, 16, v1 924; GFX10-NEXT: image_sample_c_d_o_g16 v[0:1], v[2:8], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY 925; GFX10-NEXT: s_waitcnt vmcnt(0) 926; GFX10-NEXT: ; return to shader part epilog 927; 928; GFX10GISEL-LABEL: sample_g16_noa16_c_d_o_2darray_V2: 929; GFX10GISEL: ; %bb.0: ; %main_body 930; GFX10GISEL-NEXT: v_mov_b32_e32 v9, v3 931; GFX10GISEL-NEXT: v_mov_b32_e32 v10, v2 932; GFX10GISEL-NEXT: v_mov_b32_e32 v11, v4 933; GFX10GISEL-NEXT: v_mov_b32_e32 v2, v0 934; GFX10GISEL-NEXT: v_mov_b32_e32 v3, v1 935; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v0, 16, v9 936; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v5 937; GFX10GISEL-NEXT: v_and_or_b32 v4, 0xffff, v10, v0 938; GFX10GISEL-NEXT: v_and_or_b32 v5, 0xffff, v11, v1 939; GFX10GISEL-NEXT: image_sample_c_d_o_g16 v[0:1], v[2:8], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY 940; GFX10GISEL-NEXT: s_waitcnt vmcnt(0) 941; GFX10GISEL-NEXT: ; return to shader part epilog 942main_body: 943 %v = call <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f16.f32(i32 6, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) 944 ret <2 x float> %v 945} 946 947declare <4 x float> @llvm.amdgcn.image.sample.d.1d.v4f32.f16.f32(i32, half, half, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 948declare <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f16.f32(i32, half, half, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 949declare <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f16.f32(i32, half, half, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 950declare <4 x float> @llvm.amdgcn.image.sample.c.d.1d.v4f32.f16.f32(i32, float, half, half, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 951declare <4 x float> @llvm.amdgcn.image.sample.c.d.2d.v4f32.f16.f32(i32, float, half, half, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 952declare <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f16.f32(i32, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 953declare <4 x float> @llvm.amdgcn.image.sample.d.cl.2d.v4f32.f16.f32(i32, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 954declare <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f16.f32(i32, float, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 955declare <4 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v4f32.f16.f32(i32, float, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 956 957declare <4 x float> @llvm.amdgcn.image.sample.cd.1d.v4f32.f16.f32(i32, half, half, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 958declare <4 x float> @llvm.amdgcn.image.sample.cd.2d.v4f32.f16.f32(i32, half, half, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 959declare <4 x float> @llvm.amdgcn.image.sample.c.cd.1d.v4f32.f16.f32(i32, float, half, half, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 960declare <4 x float> @llvm.amdgcn.image.sample.c.cd.2d.v4f32.f16.f32(i32, float, half, half, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 961declare <4 x float> @llvm.amdgcn.image.sample.cd.cl.1d.v4f32.f16.f32(i32, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 962declare <4 x float> @llvm.amdgcn.image.sample.cd.cl.2d.v4f32.f16.f32(i32, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 963declare <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.1d.v4f32.f16.f32(i32, float, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 964declare <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.2d.v4f32.f16.f32(i32, float, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 965 966declare float @llvm.amdgcn.image.sample.c.d.o.2darray.f32.f16.f32(i32, i32, float, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 967declare <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f16.f32(i32, i32, float, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 968 969attributes #0 = { nounwind } 970attributes #1 = { nounwind readonly } 971attributes #2 = { nounwind readnone } 972