1; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-nsa-encoding -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=GCN,NONSA %s
2; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=GCN,NSA %s
3
4; GCN-LABEL: {{^}}sample_2d:
5;
6; TODO: use NSA here
7; GCN: v_mov_b32_e32 v2, v0
8;
9; GCN: image_sample v[0:3], v[1:2],
10define amdgpu_ps <4 x float> @sample_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %t, float %s) {
11main_body:
12  %v = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
13  ret <4 x float> %v
14}
15
16; GCN-LABEL: {{^}}sample_3d:
17; NONSA: v_mov_b32_e32 v3, v0
18; NONSA: image_sample v[0:3], v[1:3],
19; NSA: image_sample v[0:3], [v1, v2, v0],
20define amdgpu_ps <4 x float> @sample_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %r, float %s, float %t) {
21main_body:
22  %v = call <4 x float> @llvm.amdgcn.image.sample.3d.v4f32.f32(i32 15, float %s, float %t, float %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
23  ret <4 x float> %v
24}
25
26; GCN-LABEL: {{^}}sample_d_3d:
27; NSA: image_sample_d v[0:3], [v3, v8, v7, v5, v4, v6, v0, v2, v1],
28define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %r, float %t, float %dsdh, float %dtdv, float %dsdv, float %drdv, float %drdh, float %dtdh) {
29main_body:
30  %v = call <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f32(i32 15, float %dsdh, float %dtdh, float %drdh, float %dsdv, float %dtdv, float %drdv, float %s, float %t, float %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
31  ret <4 x float> %v
32}
33
34; GCN-LABEL: {{^}}sample_contig_nsa:
35; NONSA: image_sample_c_l v5, v[0:4],
36; NSA: image_sample_c_l v8, v[0:4],
37; NSA: image_sample v9, [v6, v7, v5],
38define amdgpu_ps <2 x float> @sample_contig_nsa(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s1, float %t1, float %r1, float %lod, float %r2, float %s2, float %t2) {
39main_body:
40  %v1 = call float @llvm.amdgcn.image.sample.c.l.3d.f32.f32(i32 1, float %zcompare, float %s1, float %t1, float %r1, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
41  %v2 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2, float %t2, float %r2, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
42  %r.0 = insertelement <2 x float> undef, float %v1, i32 0
43  %r = insertelement <2 x float> %r.0, float %v2, i32 1
44  ret <2 x float> %r
45}
46
47; GCN-LABEL: {{^}}sample_nsa_nsa:
48; NSA: image_sample_c_l v8, [v1, v2, v3, v4, v0],
49; NSA: image_sample v9, [v6, v7, v5],
50define amdgpu_ps <2 x float> @sample_nsa_nsa(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %lod, float %zcompare, float %s1, float %t1, float %r1, float %r2, float %s2, float %t2) {
51main_body:
52  %v1 = call float @llvm.amdgcn.image.sample.c.l.3d.f32.f32(i32 1, float %zcompare, float %s1, float %t1, float %r1, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
53  %v2 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2, float %t2, float %r2, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
54  %r.0 = insertelement <2 x float> undef, float %v1, i32 0
55  %r = insertelement <2 x float> %r.0, float %v2, i32 1
56  ret <2 x float> %r
57}
58
59; GCN-LABEL: {{^}}sample_nsa_contig:
60; NSA: image_sample_c_l v8, [v1, v2, v3, v4, v0],
61; NSA: image_sample v9, v[5:7],
62define amdgpu_ps <2 x float> @sample_nsa_contig(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %lod, float %zcompare, float %s1, float %t1, float %r1, float %s2, float %t2, float %r2) {
63main_body:
64  %v1 = call float @llvm.amdgcn.image.sample.c.l.3d.f32.f32(i32 1, float %zcompare, float %s1, float %t1, float %r1, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
65  %v2 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2, float %t2, float %r2, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
66  %r.0 = insertelement <2 x float> undef, float %v1, i32 0
67  %r = insertelement <2 x float> %r.0, float %v2, i32 1
68  ret <2 x float> %r
69}
70
71; GCN-LABEL: {{^}}sample_contig_contig:
72; NSA: image_sample_c_l v8, v[0:4],
73; NSA: image_sample v9, v[5:7],
74; NONSA: image_sample_c_l v8, v[0:4],
75; NONSA: image_sample v9, v[5:7],
76define amdgpu_ps <2 x float> @sample_contig_contig(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s1, float %t1, float %r1, float %lod, float %s2, float %t2, float %r2) {
77main_body:
78  %v1 = call float @llvm.amdgcn.image.sample.c.l.3d.f32.f32(i32 1, float %zcompare, float %s1, float %t1, float %r1, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
79  %v2 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2, float %t2, float %r2, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
80  %r.0 = insertelement <2 x float> undef, float %v1, i32 0
81  %r = insertelement <2 x float> %r.0, float %v2, i32 1
82  ret <2 x float> %r
83}
84
85; Test that undef inputs with NSA are handled safely; these tests used to crash.
86
87; GCN-LABEL: {{^}}sample_undef_undef_undef_undef:
88; GCN: image_sample_c_b v0, v[0:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY
89define amdgpu_ps float @sample_undef_undef_undef_undef(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp) {
90  %r = call float @llvm.amdgcn.image.sample.c.b.1darray.f32.f32.f32(i32 1, float undef, float undef, float undef, float undef, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
91  ret float %r
92}
93
94; GCN-LABEL: {{^}}sample_undef_undef_undef_def:
95; NONSA: v_mov_b32_e32 v3, v0
96; NONSA: image_sample_c_b v0, v[0:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY
97; NSA: image_sample_c_b v0, [v0, v0, v0, v0], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY
98define amdgpu_ps float @sample_undef_undef_undef_def(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %layer) {
99  %r = call float @llvm.amdgcn.image.sample.c.b.1darray.f32.f32.f32(i32 1, float undef, float undef, float undef, float %layer, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
100  ret float %r
101}
102
103; GCN-LABEL: {{^}}sample_undef_undef_undef_def_rnd:
104; GCN: v_rndne_f32_e32 v3, v0
105; GCN: image_sample_c_b v0, v[0:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY
106define amdgpu_ps float @sample_undef_undef_undef_def_rnd(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %layer) {
107  %layer_rnd = call float @llvm.rint.f32(float %layer)
108  %r = call float @llvm.amdgcn.image.sample.c.b.1darray.f32.f32.f32(i32 1, float undef, float undef, float undef, float %layer_rnd, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
109  ret float %r
110}
111
112; GCN-LABEL: {{^}}sample_def_undef_undef_undef:
113; GCN: v_add_f32_e32 v0, 1.0, v0
114; GCN: image_sample_c_b v0, v[0:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY
115define amdgpu_ps float @sample_def_undef_undef_undef(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %z0) {
116  ; The NSA reassign pass is conservative (quite reasonably!) when one of the operands
117  ; comes directly from a function argument (via COPY). To test that NSA can be
118  ; eliminated in the presence of undef, just add an arbitrary intermediate
119  ; computation.
120  %c0 = fadd float %z0, 1.0
121  %r = call float @llvm.amdgcn.image.sample.c.b.1darray.f32.f32.f32(i32 1, float %c0, float undef, float undef, float undef, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
122  ret float %r
123}
124
125declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
126declare <4 x float> @llvm.amdgcn.image.sample.3d.v4f32.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
127declare <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f32(i32, float, float, float, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
128
129declare float @llvm.amdgcn.image.sample.3d.f32.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
130declare float @llvm.amdgcn.image.sample.c.l.3d.f32.f32(i32, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
131
132declare float @llvm.rint.f32(float) #2
133declare float @llvm.amdgcn.image.sample.c.b.1darray.f32.f32.f32(i32 immarg, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1
134
135attributes #1 = { nounwind readonly }
136attributes #2 = { nounwind readnone speculatable willreturn }
137