1; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-nsa-encoding -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NONSA,GFX10-NONSA %s
2; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NSA,GFX1010-NSA %s
3; RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NSA,GFX1030-NSA %s
4; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=-nsa-encoding -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NONSA,GFX11-NONSA %s
5; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NSA,GFX11-NSA %s
6
7; GCN-LABEL: {{^}}sample_2d:
8;
9; TODO: use NSA here
10; GCN: v_mov_b32_e32 v2, v0
11;
12; GCN: image_sample v[0:3], v[1:2],
13define amdgpu_ps <4 x float> @sample_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %t, float %s) {
14main_body:
15  %v = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
16  ret <4 x float> %v
17}
18
19; GCN-LABEL: {{^}}sample_3d:
20; NONSA: v_mov_b32_e32 v3, v0
21; NONSA: image_sample v[0:3], v[1:3],
22; NSA: image_sample v[0:3], [v1, v2, v0],
23define amdgpu_ps <4 x float> @sample_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %r, float %s, float %t) {
24main_body:
25  %v = call <4 x float> @llvm.amdgcn.image.sample.3d.v4f32.f32(i32 15, float %s, float %t, float %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
26  ret <4 x float> %v
27}
28
29; GCN-LABEL: {{^}}sample_d_3d:
30; GFX1010-NSA: image_sample_d v[0:3], v[7:22],
31; GFX1030-NSA: image_sample_d v[0:3], [v3, v8, v7, v5, v4, v6, v0, v2, v1],
32; GFX11-NSA: image_sample_d v[0:3], v[7:22],
33define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %r, float %t, float %dsdh, float %dtdv, float %dsdv, float %drdv, float %drdh, float %dtdh) {
34main_body:
35  %v = call <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f32(i32 15, float %dsdh, float %dtdh, float %drdh, float %dsdv, float %dtdv, float %drdv, float %s, float %t, float %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
36  ret <4 x float> %v
37}
38
39; GCN-LABEL: {{^}}sample_contig_nsa:
40; GFX10-NONSA: image_sample_c_l v5, v[0:4],
41; GFX11-NONSA: image_sample_c_l v0, v[0:4],
42; GFX1010-NSA: image_sample_c_l v8, v[0:4],
43; GFX1010-NSA: image_sample v9, [v6, v7, v5],
44; GFX1030-NSA: image_sample_c_l v0, v[0:4],
45; GFX1030-NSA: image_sample v1, [v6, v7, v5],
46; GFX11-NSA: image_sample_c_l v0, v[0:4],
47; GFX11-NSA: image_sample v1, [v6, v7, v5],
48define amdgpu_ps <2 x float> @sample_contig_nsa(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s1, float %t1, float %r1, float %lod, float %r2, float %s2, float %t2) {
49main_body:
50  %v1 = call float @llvm.amdgcn.image.sample.c.l.3d.f32.f32(i32 1, float %zcompare, float %s1, float %t1, float %r1, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
51  %v2 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2, float %t2, float %r2, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
52  %r.0 = insertelement <2 x float> undef, float %v1, i32 0
53  %r = insertelement <2 x float> %r.0, float %v2, i32 1
54  ret <2 x float> %r
55}
56
57; GCN-LABEL: {{^}}sample_nsa_nsa:
58; GFX1010-NSA: image_sample_c_l v8, [v1, v2, v3, v4, v0],
59; GFX1010-NSA: image_sample v9, [v6, v7, v5],
60; GFX1030-NSA: image_sample_c_l v0, [v1, v2, v3, v4, v0],
61; GFX1030-NSA: image_sample v1, [v6, v7, v5],
62; GFX11-NSA: image_sample_c_l v0, [v1, v2, v3, v4, v0],
63; GFX11-NSA: image_sample v1, [v6, v7, v5],
64define amdgpu_ps <2 x float> @sample_nsa_nsa(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %lod, float %zcompare, float %s1, float %t1, float %r1, float %r2, float %s2, float %t2) {
65main_body:
66  %v1 = call float @llvm.amdgcn.image.sample.c.l.3d.f32.f32(i32 1, float %zcompare, float %s1, float %t1, float %r1, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
67  %v2 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2, float %t2, float %r2, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
68  %r.0 = insertelement <2 x float> undef, float %v1, i32 0
69  %r = insertelement <2 x float> %r.0, float %v2, i32 1
70  ret <2 x float> %r
71}
72
73; GCN-LABEL: {{^}}sample_nsa_contig:
74; GFX1010-NSA: image_sample_c_l v8, [v1, v2, v3, v4, v0],
75; GFX1010-NSA: image_sample v9, v[5:7],
76; GFX1030-NSA: image_sample_c_l v0, [v1, v2, v3, v4, v0],
77; GFX1030-NSA: image_sample v1, v[5:7],
78; GFX11-NSA: image_sample_c_l v0, [v1, v2, v3, v4, v0],
79; GFX11-NSA: image_sample v1, v[5:7],
80define amdgpu_ps <2 x float> @sample_nsa_contig(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %lod, float %zcompare, float %s1, float %t1, float %r1, float %s2, float %t2, float %r2) {
81main_body:
82  %v1 = call float @llvm.amdgcn.image.sample.c.l.3d.f32.f32(i32 1, float %zcompare, float %s1, float %t1, float %r1, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
83  %v2 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2, float %t2, float %r2, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
84  %r.0 = insertelement <2 x float> undef, float %v1, i32 0
85  %r = insertelement <2 x float> %r.0, float %v2, i32 1
86  ret <2 x float> %r
87}
88
89; GCN-LABEL: {{^}}sample_contig_contig:
90; GFX1010-NSA: image_sample_c_l v8, v[0:4],
91; GFX1010-NSA: image_sample v9, v[5:7],
92; GFX1030-NSA: image_sample_c_l v0, v[0:4],
93; GFX1030-NSA: image_sample v1, v[5:7],
94; GFX11-NSA: image_sample_c_l v0, v[0:4],
95; GFX11-NSA: image_sample v1, v[5:7],
96; GFX10-NONSA: image_sample_c_l v8, v[0:4],
97; GFX10-NONSA: image_sample v9, v[5:7],
98; GFX11-NONSA: image_sample_c_l v0, v[0:4],
99; GFX11-NONSA: image_sample v1, v[5:7],
100define amdgpu_ps <2 x float> @sample_contig_contig(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s1, float %t1, float %r1, float %lod, float %s2, float %t2, float %r2) {
101main_body:
102  %v1 = call float @llvm.amdgcn.image.sample.c.l.3d.f32.f32(i32 1, float %zcompare, float %s1, float %t1, float %r1, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
103  %v2 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2, float %t2, float %r2, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
104  %r.0 = insertelement <2 x float> undef, float %v1, i32 0
105  %r = insertelement <2 x float> %r.0, float %v2, i32 1
106  ret <2 x float> %r
107}
108
109; Test that undef inputs with NSA are handled safely; these tests used to crash.
110
111; GCN-LABEL: {{^}}sample_undef_undef_undef_undef:
112; GCN: image_sample_c_b v0, v[0:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY
113define amdgpu_ps float @sample_undef_undef_undef_undef(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp) {
114  %r = call float @llvm.amdgcn.image.sample.c.b.1darray.f32.f32.f32(i32 1, float undef, float undef, float undef, float undef, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
115  ret float %r
116}
117
118; GCN-LABEL: {{^}}sample_undef_undef_undef_def:
119; NONSA: v_mov_b32_e32 v3, v0
120; NONSA: image_sample_c_b v0, v[0:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY
121; NSA: image_sample_c_b v0, [v0, v0, v0, v0], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY
122define amdgpu_ps float @sample_undef_undef_undef_def(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %layer) {
123  %r = call float @llvm.amdgcn.image.sample.c.b.1darray.f32.f32.f32(i32 1, float undef, float undef, float undef, float %layer, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
124  ret float %r
125}
126
127; GCN-LABEL: {{^}}sample_undef_undef_undef_def_rnd:
128; GCN: v_rndne_f32_e32 v3, v0
129; GCN: image_sample_c_b v0, v[0:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY
130define amdgpu_ps float @sample_undef_undef_undef_def_rnd(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %layer) {
131  %layer_rnd = call float @llvm.rint.f32(float %layer)
132  %r = call float @llvm.amdgcn.image.sample.c.b.1darray.f32.f32.f32(i32 1, float undef, float undef, float undef, float %layer_rnd, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
133  ret float %r
134}
135
136; GCN-LABEL: {{^}}sample_def_undef_undef_undef:
137; GCN: v_add_f32_e32 v0, 1.0, v0
138; GCN: image_sample_c_b v0, v[0:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY
139define amdgpu_ps float @sample_def_undef_undef_undef(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %z0) {
140  ; The NSA reassign pass is conservative (quite reasonably!) when one of the operands
141  ; comes directly from a function argument (via COPY). To test that NSA can be
142  ; eliminated in the presence of undef, just add an arbitrary intermediate
143  ; computation.
144  %c0 = fadd float %z0, 1.0
145  %r = call float @llvm.amdgcn.image.sample.c.b.1darray.f32.f32.f32(i32 1, float %c0, float undef, float undef, float undef, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
146  ret float %r
147}
148
149declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
150declare <4 x float> @llvm.amdgcn.image.sample.3d.v4f32.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
151declare <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f32(i32, float, float, float, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
152
153declare float @llvm.amdgcn.image.sample.3d.f32.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
154declare float @llvm.amdgcn.image.sample.c.l.3d.f32.f32(i32, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
155
156declare float @llvm.rint.f32(float) #2
157declare float @llvm.amdgcn.image.sample.c.b.1darray.f32.f32.f32(i32 immarg, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1
158
159attributes #1 = { nounwind readonly }
160attributes #2 = { nounwind readnone speculatable willreturn }
161