1; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
2; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3
4; GCN-LABEL: {{^}}atomic_swap_1d:
5; GCN: image_atomic_swap v0, v1, s[0:7] dmask:0x1 unorm glc{{$}}
6define amdgpu_ps float @atomic_swap_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
7main_body:
8  %v = call i32 @llvm.amdgcn.image.atomic.swap.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
9  %out = bitcast i32 %v to float
10  ret float %out
11}
12
13; GCN-LABEL: {{^}}atomic_add_1d:
14; GCN: image_atomic_add v0, v1, s[0:7] dmask:0x1 unorm glc{{$}}
15define amdgpu_ps float @atomic_add_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
16main_body:
17  %v = call i32 @llvm.amdgcn.image.atomic.add.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
18  %out = bitcast i32 %v to float
19  ret float %out
20}
21
22; GCN-LABEL: {{^}}atomic_sub_1d:
23; GCN: image_atomic_sub v0, v1, s[0:7] dmask:0x1 unorm glc{{$}}
24define amdgpu_ps float @atomic_sub_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
25main_body:
26  %v = call i32 @llvm.amdgcn.image.atomic.sub.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
27  %out = bitcast i32 %v to float
28  ret float %out
29}
30
31; GCN-LABEL: {{^}}atomic_smin_1d:
32; GCN: image_atomic_smin v0, v1, s[0:7] dmask:0x1 unorm glc{{$}}
33define amdgpu_ps float @atomic_smin_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
34main_body:
35  %v = call i32 @llvm.amdgcn.image.atomic.smin.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
36  %out = bitcast i32 %v to float
37  ret float %out
38}
39
40; GCN-LABEL: {{^}}atomic_umin_1d:
41; GCN: image_atomic_umin v0, v1, s[0:7] dmask:0x1 unorm glc{{$}}
42define amdgpu_ps float @atomic_umin_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
43main_body:
44  %v = call i32 @llvm.amdgcn.image.atomic.umin.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
45  %out = bitcast i32 %v to float
46  ret float %out
47}
48
49; GCN-LABEL: {{^}}atomic_smax_1d:
50; GCN: image_atomic_smax v0, v1, s[0:7] dmask:0x1 unorm glc{{$}}
51define amdgpu_ps float @atomic_smax_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
52main_body:
53  %v = call i32 @llvm.amdgcn.image.atomic.smax.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
54  %out = bitcast i32 %v to float
55  ret float %out
56}
57
58; GCN-LABEL: {{^}}atomic_umax_1d:
59; GCN: image_atomic_umax v0, v1, s[0:7] dmask:0x1 unorm glc{{$}}
60define amdgpu_ps float @atomic_umax_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
61main_body:
62  %v = call i32 @llvm.amdgcn.image.atomic.umax.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
63  %out = bitcast i32 %v to float
64  ret float %out
65}
66
67; GCN-LABEL: {{^}}atomic_and_1d:
68; GCN: image_atomic_and v0, v1, s[0:7] dmask:0x1 unorm glc{{$}}
69define amdgpu_ps float @atomic_and_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
70main_body:
71  %v = call i32 @llvm.amdgcn.image.atomic.and.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
72  %out = bitcast i32 %v to float
73  ret float %out
74}
75
76; GCN-LABEL: {{^}}atomic_or_1d:
77; GCN: image_atomic_or v0, v1, s[0:7] dmask:0x1 unorm glc{{$}}
78define amdgpu_ps float @atomic_or_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
79main_body:
80  %v = call i32 @llvm.amdgcn.image.atomic.or.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
81  %out = bitcast i32 %v to float
82  ret float %out
83}
84
85; GCN-LABEL: {{^}}atomic_xor_1d:
86; GCN: image_atomic_xor v0, v1, s[0:7] dmask:0x1 unorm glc{{$}}
87define amdgpu_ps float @atomic_xor_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
88main_body:
89  %v = call i32 @llvm.amdgcn.image.atomic.xor.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
90  %out = bitcast i32 %v to float
91  ret float %out
92}
93
94; GCN-LABEL: {{^}}atomic_inc_1d:
95; GCN: image_atomic_inc v0, v1, s[0:7] dmask:0x1 unorm glc{{$}}
96define amdgpu_ps float @atomic_inc_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
97main_body:
98  %v = call i32 @llvm.amdgcn.image.atomic.inc.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
99  %out = bitcast i32 %v to float
100  ret float %out
101}
102
103; GCN-LABEL: {{^}}atomic_dec_1d:
104; GCN: image_atomic_dec v0, v1, s[0:7] dmask:0x1 unorm glc{{$}}
105define amdgpu_ps float @atomic_dec_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
106main_body:
107  %v = call i32 @llvm.amdgcn.image.atomic.dec.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
108  %out = bitcast i32 %v to float
109  ret float %out
110}
111
112; GCN-LABEL: {{^}}atomic_cmpswap_1d:
113; GCN: image_atomic_cmpswap v[0:1], v2, s[0:7] dmask:0x3 unorm glc{{$}}
114define amdgpu_ps float @atomic_cmpswap_1d(<8 x i32> inreg %rsrc, i32 %cmp, i32 %swap, i32 %s) {
115main_body:
116  %v = call i32 @llvm.amdgcn.image.atomic.cmpswap.1d.i32.i32(i32 %cmp, i32 %swap, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
117  %out = bitcast i32 %v to float
118  ret float %out
119}
120
121; GCN-LABEL: {{^}}atomic_add_2d:
122; GCN: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 unorm glc{{$}}
123define amdgpu_ps float @atomic_add_2d(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %t) {
124main_body:
125  %v = call i32 @llvm.amdgcn.image.atomic.add.2d.i32.i32(i32 %data, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
126  %out = bitcast i32 %v to float
127  ret float %out
128}
129
130; GCN-LABEL: {{^}}atomic_add_3d:
131; GCN: image_atomic_add v0, v[1:4], s[0:7] dmask:0x1 unorm glc{{$}}
132define amdgpu_ps float @atomic_add_3d(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %t, i32 %r) {
133main_body:
134  %v = call i32 @llvm.amdgcn.image.atomic.add.3d.i32.i32(i32 %data, i32 %s, i32 %t, i32 %r, <8 x i32> %rsrc, i32 0, i32 0)
135  %out = bitcast i32 %v to float
136  ret float %out
137}
138
139; GCN-LABEL: {{^}}atomic_add_cube:
140; GCN: image_atomic_add v0, v[1:4], s[0:7] dmask:0x1 unorm glc da{{$}}
141define amdgpu_ps float @atomic_add_cube(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %t, i32 %face) {
142main_body:
143  %v = call i32 @llvm.amdgcn.image.atomic.add.cube.i32.i32(i32 %data, i32 %s, i32 %t, i32 %face, <8 x i32> %rsrc, i32 0, i32 0)
144  %out = bitcast i32 %v to float
145  ret float %out
146}
147
148; GCN-LABEL: {{^}}atomic_add_1darray:
149; GCN: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 unorm glc da{{$}}
150define amdgpu_ps float @atomic_add_1darray(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %slice) {
151main_body:
152  %v = call i32 @llvm.amdgcn.image.atomic.add.1darray.i32.i32(i32 %data, i32 %s, i32 %slice, <8 x i32> %rsrc, i32 0, i32 0)
153  %out = bitcast i32 %v to float
154  ret float %out
155}
156
157; GCN-LABEL: {{^}}atomic_add_2darray:
158; GCN: image_atomic_add v0, v[1:4], s[0:7] dmask:0x1 unorm glc da{{$}}
159define amdgpu_ps float @atomic_add_2darray(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %t, i32 %slice) {
160main_body:
161  %v = call i32 @llvm.amdgcn.image.atomic.add.2darray.i32.i32(i32 %data, i32 %s, i32 %t, i32 %slice, <8 x i32> %rsrc, i32 0, i32 0)
162  %out = bitcast i32 %v to float
163  ret float %out
164}
165
166; GCN-LABEL: {{^}}atomic_add_2dmsaa:
167; GCN: image_atomic_add v0, v[1:4], s[0:7] dmask:0x1 unorm glc{{$}}
168define amdgpu_ps float @atomic_add_2dmsaa(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %t, i32 %fragid) {
169main_body:
170  %v = call i32 @llvm.amdgcn.image.atomic.add.2dmsaa.i32.i32(i32 %data, i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
171  %out = bitcast i32 %v to float
172  ret float %out
173}
174
175; GCN-LABEL: {{^}}atomic_add_2darraymsaa:
176; GCN: image_atomic_add v0, v[1:4], s[0:7] dmask:0x1 unorm glc da{{$}}
177define amdgpu_ps float @atomic_add_2darraymsaa(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %t, i32 %slice, i32 %fragid) {
178main_body:
179  %v = call i32 @llvm.amdgcn.image.atomic.add.2darraymsaa.i32.i32(i32 %data, i32 %s, i32 %t, i32 %slice, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
180  %out = bitcast i32 %v to float
181  ret float %out
182}
183
184; GCN-LABEL: {{^}}atomic_add_1d_slc:
185; GCN: image_atomic_add v0, v1, s[0:7] dmask:0x1 unorm glc slc{{$}}
186define amdgpu_ps float @atomic_add_1d_slc(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
187main_body:
188  %v = call i32 @llvm.amdgcn.image.atomic.add.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 2)
189  %out = bitcast i32 %v to float
190  ret float %out
191}
192
193declare i32 @llvm.amdgcn.image.atomic.swap.1d.i32.i32(i32, i32, <8 x i32>, i32, i32) #0
194declare i32 @llvm.amdgcn.image.atomic.add.1d.i32.i32(i32, i32, <8 x i32>, i32, i32) #0
195declare i32 @llvm.amdgcn.image.atomic.sub.1d.i32.i32(i32, i32, <8 x i32>, i32, i32) #0
196declare i32 @llvm.amdgcn.image.atomic.smin.1d.i32.i32(i32, i32, <8 x i32>, i32, i32) #0
197declare i32 @llvm.amdgcn.image.atomic.umin.1d.i32.i32(i32, i32, <8 x i32>, i32, i32) #0
198declare i32 @llvm.amdgcn.image.atomic.smax.1d.i32.i32(i32, i32, <8 x i32>, i32, i32) #0
199declare i32 @llvm.amdgcn.image.atomic.umax.1d.i32.i32(i32, i32, <8 x i32>, i32, i32) #0
200declare i32 @llvm.amdgcn.image.atomic.and.1d.i32.i32(i32, i32, <8 x i32>, i32, i32) #0
201declare i32 @llvm.amdgcn.image.atomic.or.1d.i32.i32(i32, i32, <8 x i32>, i32, i32) #0
202declare i32 @llvm.amdgcn.image.atomic.xor.1d.i32.i32(i32, i32, <8 x i32>, i32, i32) #0
203declare i32 @llvm.amdgcn.image.atomic.inc.1d.i32.i32(i32, i32, <8 x i32>, i32, i32) #0
204declare i32 @llvm.amdgcn.image.atomic.dec.1d.i32.i32(i32, i32, <8 x i32>, i32, i32) #0
205declare i32 @llvm.amdgcn.image.atomic.cmpswap.1d.i32.i32(i32, i32, i32, <8 x i32>, i32, i32) #0
206
207declare i32 @llvm.amdgcn.image.atomic.add.2d.i32.i32(i32, i32, i32, <8 x i32>, i32, i32) #0
208declare i32 @llvm.amdgcn.image.atomic.add.3d.i32.i32(i32, i32, i32, i32, <8 x i32>, i32, i32) #0
209declare i32 @llvm.amdgcn.image.atomic.add.cube.i32.i32(i32, i32, i32, i32, <8 x i32>, i32, i32) #0
210declare i32 @llvm.amdgcn.image.atomic.add.1darray.i32.i32(i32, i32, i32, <8 x i32>, i32, i32) #0
211declare i32 @llvm.amdgcn.image.atomic.add.2darray.i32.i32(i32, i32, i32, i32, <8 x i32>, i32, i32) #0
212declare i32 @llvm.amdgcn.image.atomic.add.2dmsaa.i32.i32(i32, i32, i32, i32, <8 x i32>, i32, i32) #0
213declare i32 @llvm.amdgcn.image.atomic.add.2darraymsaa.i32.i32(i32, i32, i32, i32, i32, <8 x i32>, i32, i32) #0
214
215attributes #0 = { nounwind }
216attributes #1 = { nounwind readonly }
217attributes #2 = { nounwind readnone }
218