1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GFX11,SDAG-GFX11
3; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GFX11,GISEL-GFX11
4
5declare i16 @llvm.amdgcn.fdot2.bf16.bf16(<2 x i16> %a, <2 x i16> %b, i16 %c)
6
7define amdgpu_kernel void @test_llvm_amdgcn_fdot2_bf16_bf16(
8; GFX11-LABEL: test_llvm_amdgcn_fdot2_bf16_bf16:
9; GFX11:       ; %bb.0: ; %entry
10; GFX11-NEXT:    s_load_b256 s[0:7], s[0:1], 0x24
11; GFX11-NEXT:    v_mov_b32_e32 v0, 0
12; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
13; GFX11-NEXT:    global_load_u16 v1, v0, s[6:7]
14; GFX11-NEXT:    s_load_b32 s2, s[2:3], 0x0
15; GFX11-NEXT:    s_load_b32 s3, s[4:5], 0x0
16; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
17; GFX11-NEXT:    v_dot2_bf16_bf16 v1, s2, s3, v1
18; GFX11-NEXT:    global_store_b16 v0, v1, s[0:1]
19; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
20; GFX11-NEXT:    s_endpgm
21    i16 addrspace(1)* %r,
22    <2 x i16> addrspace(1)* %a,
23    <2 x i16> addrspace(1)* %b,
24    i16 addrspace(1)* %c) {
25entry:
26  %a.val = load <2 x i16>, <2 x i16> addrspace(1)* %a
27  %b.val = load <2 x i16>, <2 x i16> addrspace(1)* %b
28  %c.val = load i16, i16 addrspace(1)* %c
29  %r.val = call i16 @llvm.amdgcn.fdot2.bf16.bf16(<2 x i16> %a.val, <2 x i16> %b.val, i16 %c.val)
30  store i16 %r.val, i16 addrspace(1)* %r
31  ret void
32}
33
34define amdgpu_kernel void @test_llvm_amdgcn_fdot2_bf16_bf16_dpp(
35; SDAG-GFX11-LABEL: test_llvm_amdgcn_fdot2_bf16_bf16_dpp:
36; SDAG-GFX11:       ; %bb.0: ; %entry
37; SDAG-GFX11-NEXT:    s_load_b128 s[0:3], s[0:1], 0x24
38; SDAG-GFX11-NEXT:    s_waitcnt lgkmcnt(0)
39; SDAG-GFX11-NEXT:    scratch_load_b32 v0, off, s2
40; SDAG-GFX11-NEXT:    scratch_load_u16 v1, off, s3
41; SDAG-GFX11-NEXT:    scratch_load_b32 v2, off, s1
42; SDAG-GFX11-NEXT:    s_waitcnt vmcnt(0)
43; SDAG-GFX11-NEXT:    v_dot2_bf16_bf16_e64_dpp v0, v2, v0, v1 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
44; SDAG-GFX11-NEXT:    scratch_store_b16 off, v0, s0
45; SDAG-GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
46; SDAG-GFX11-NEXT:    s_endpgm
47;
48; GISEL-GFX11-LABEL: test_llvm_amdgcn_fdot2_bf16_bf16_dpp:
49; GISEL-GFX11:       ; %bb.0: ; %entry
50; GISEL-GFX11-NEXT:    s_load_b128 s[0:3], s[0:1], 0x24
51; GISEL-GFX11-NEXT:    s_waitcnt lgkmcnt(0)
52; GISEL-GFX11-NEXT:    scratch_load_b32 v0, off, s1
53; GISEL-GFX11-NEXT:    scratch_load_b32 v1, off, s2
54; GISEL-GFX11-NEXT:    scratch_load_u16 v2, off, s3
55; GISEL-GFX11-NEXT:    s_waitcnt vmcnt(0)
56; GISEL-GFX11-NEXT:    v_dot2_bf16_bf16_e64_dpp v0, v0, v1, v2 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
57; GISEL-GFX11-NEXT:    scratch_store_b16 off, v0, s0
58; GISEL-GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
59; GISEL-GFX11-NEXT:    s_endpgm
60    i16 addrspace(5)* %r,
61    <2 x i16> addrspace(5)* %a,
62    <2 x i16> addrspace(5)* %b,
63    i16 addrspace(5)* %c) {
64entry:
65  %a.val = load <2 x i16>, <2 x i16> addrspace(5)* %a
66  %b.val = load <2 x i16>, <2 x i16> addrspace(5)* %b
67  %c.val = load i16, i16 addrspace(5)* %c
68  %a.val.i32 = bitcast <2 x i16> %a.val to i32
69  %dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 %a.val.i32, i32 %a.val.i32, i32 1, i32 15, i32 15, i1 1)
70  %a.val.dpp.v2i16 = bitcast i32 %dpp to <2 x i16>
71  %r.val = call i16 @llvm.amdgcn.fdot2.bf16.bf16(<2 x i16> %a.val.dpp.v2i16, <2 x i16> %b.val, i16 %c.val)
72  store i16 %r.val, i16 addrspace(5)* %r
73  ret void
74}
75
76declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32, i32, i32, i1)
77