1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GFX11,GFX11-SDAG
3; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GFX11,GFX11-GISEL
4
5declare void @llvm.amdgcn.exp.row.i32(i32, i32, i32, i32, i32, i32, i1, i32)
6declare void @llvm.amdgcn.exp.row.f32(i32, i32, float, float, float, float, i1, i32)
7declare i32 @llvm.amdgcn.workitem.id.x()
8
9define amdgpu_kernel void @undef_i32() #0 {
10; GFX11-LABEL: undef_i32:
11; GFX11:       ; %bb.0:
12; GFX11-NEXT:    s_mov_b32 m0, 0
13; GFX11-NEXT:    exp pos0 off, off, off, off row_en
14; GFX11-NEXT:    exp pos1 off, off, off, off done row_en
15; GFX11-NEXT:    s_endpgm
16  call void @llvm.amdgcn.exp.row.i32(i32 12, i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i1 false, i32 0)
17  call void @llvm.amdgcn.exp.row.i32(i32 13, i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i1 true, i32 0)
18  ret void
19}
20
21define amdgpu_kernel void @undef_f32() #0 {
22; GFX11-LABEL: undef_f32:
23; GFX11:       ; %bb.0:
24; GFX11-NEXT:    s_mov_b32 m0, 0
25; GFX11-NEXT:    exp pos0 off, off, off, off row_en
26; GFX11-NEXT:    exp pos1 off, off, off, off done row_en
27; GFX11-NEXT:    s_endpgm
28  call void @llvm.amdgcn.exp.row.f32(i32 12, i32 0, float undef, float undef, float undef, float undef, i1 false, i32 0)
29  call void @llvm.amdgcn.exp.row.f32(i32 13, i32 0, float undef, float undef, float undef, float undef, i1 true, i32 0)
30  ret void
31}
32
33define amdgpu_kernel void @zero_i32() #0 {
34; GFX11-LABEL: zero_i32:
35; GFX11:       ; %bb.0:
36; GFX11-NEXT:    v_mov_b32_e32 v0, 0
37; GFX11-NEXT:    s_mov_b32 m0, 0
38; GFX11-NEXT:    exp pos0 v0, v0, v0, off row_en
39; GFX11-NEXT:    exp pos1 v0, v0, v0, off done row_en
40; GFX11-NEXT:    s_endpgm
41  call void @llvm.amdgcn.exp.row.i32(i32 12, i32 7, i32 0, i32 0, i32 0, i32 undef, i1 false, i32 0)
42  call void @llvm.amdgcn.exp.row.i32(i32 13, i32 7, i32 0, i32 0, i32 0, i32 undef, i1 true, i32 0)
43  ret void
44}
45
46define amdgpu_kernel void @one_f32() #0 {
47; GFX11-LABEL: one_f32:
48; GFX11:       ; %bb.0:
49; GFX11-NEXT:    v_mov_b32_e32 v0, 1.0
50; GFX11-NEXT:    s_mov_b32 m0, 0
51; GFX11-NEXT:    exp pos0 v0, v0, v0, off row_en
52; GFX11-NEXT:    exp pos1 v0, v0, v0, off done row_en
53; GFX11-NEXT:    s_endpgm
54  call void @llvm.amdgcn.exp.row.f32(i32 12, i32 7, float 1.0, float 1.0, float 1.0, float undef, i1 false, i32 0)
55  call void @llvm.amdgcn.exp.row.f32(i32 13, i32 7, float 1.0, float 1.0, float 1.0, float undef, i1 true, i32 0)
56  ret void
57}
58
59define amdgpu_kernel void @id_i32() #0 {
60; GFX11-LABEL: id_i32:
61; GFX11:       ; %bb.0:
62; GFX11-NEXT:    s_mov_b32 m0, 0
63; GFX11-NEXT:    exp pos0 v0, off, off, off done row_en
64; GFX11-NEXT:    s_endpgm
65  %id = call i32 @llvm.amdgcn.workitem.id.x()
66  call void @llvm.amdgcn.exp.row.i32(i32 12, i32 1, i32 %id, i32 undef, i32 undef, i32 undef, i1 true, i32 0)
67  ret void
68}
69
70define amdgpu_kernel void @id_arg_i32(i32 %row) #0 {
71; GFX11-LABEL: id_arg_i32:
72; GFX11:       ; %bb.0:
73; GFX11-NEXT:    s_load_b32 s0, s[0:1], 0x24
74; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
75; GFX11-NEXT:    s_mov_b32 m0, s0
76; GFX11-NEXT:    exp pos0 v0, off, off, off done row_en
77; GFX11-NEXT:    s_endpgm
78  %id = call i32 @llvm.amdgcn.workitem.id.x()
79  call void @llvm.amdgcn.exp.row.i32(i32 12, i32 1, i32 %id, i32 undef, i32 undef, i32 undef, i1 true, i32 %row)
80  ret void
81}
82
83; Divergent row number just causes a readfirstlane for now.
84define amdgpu_kernel void @id_row_i32() #0 {
85; GFX11-SDAG-LABEL: id_row_i32:
86; GFX11-SDAG:       ; %bb.0:
87; GFX11-SDAG-NEXT:    v_readfirstlane_b32 s0, v0
88; GFX11-SDAG-NEXT:    v_mov_b32_e32 v0, 0x63
89; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2)
90; GFX11-SDAG-NEXT:    s_mov_b32 m0, s0
91; GFX11-SDAG-NEXT:    exp pos0 v0, off, off, off done row_en
92; GFX11-SDAG-NEXT:    s_endpgm
93;
94; GFX11-GISEL-LABEL: id_row_i32:
95; GFX11-GISEL:       ; %bb.0:
96; GFX11-GISEL-NEXT:    v_mov_b32_e32 v1, 0x63
97; GFX11-GISEL-NEXT:    v_readfirstlane_b32 m0, v0
98; GFX11-GISEL-NEXT:    exp pos0 v1, off, off, off done row_en
99; GFX11-GISEL-NEXT:    s_endpgm
100  %id = call i32 @llvm.amdgcn.workitem.id.x()
101  call void @llvm.amdgcn.exp.row.i32(i32 12, i32 1, i32 99, i32 undef, i32 undef, i32 undef, i1 true, i32 %id)
102  ret void
103}
104