1; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s
2; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s
3
4; FUNC-LABEL: {{^}}ds_ordered_add:
5; GCN-DAG: v_mov_b32_e32 v[[INCR:[0-9]+]], 31
6; GCN-DAG: s_mov_b32 m0,
7; GCN: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:772 gds
8define amdgpu_kernel void @ds_ordered_add(i32 addrspace(2)* inreg %gds, i32 addrspace(1)* %out) {
9  %val = call [email protected](i32 addrspace(2)* %gds, i32 31, i32 0, i32 0, i1 false, i32 16777217, i1 true, i1 true)
10  store i32 %val, i32 addrspace(1)* %out
11  ret void
12}
13
14; FUNC-LABEL: {{^}}ds_ordered_add_cs:
15; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 31
16; GCN: s_mov_b32 m0, s0
17; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:772 gds
18; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0)
19define amdgpu_cs float @ds_ordered_add_cs(i32 addrspace(2)* inreg %gds) {
20  %val = call [email protected](i32 addrspace(2)* %gds, i32 31, i32 0, i32 0, i1 false, i32 16777217, i1 true, i1 true)
21  %r = bitcast i32 %val to float
22  ret float %r
23}
24
25; FUNC-LABEL: {{^}}ds_ordered_add_ps:
26; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 31
27; GCN: s_mov_b32 m0, s0
28; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:772 gds
29; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0)
30define amdgpu_ps float @ds_ordered_add_ps(i32 addrspace(2)* inreg %gds) {
31  %val = call [email protected](i32 addrspace(2)* %gds, i32 31, i32 0, i32 0, i1 false, i32 16777217, i1 true, i1 true)
32  %r = bitcast i32 %val to float
33  ret float %r
34}
35
36; FUNC-LABEL: {{^}}ds_ordered_add_vs:
37; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 31
38; GCN: s_mov_b32 m0, s0
39; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:772 gds
40; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0)
41define amdgpu_vs float @ds_ordered_add_vs(i32 addrspace(2)* inreg %gds) {
42  %val = call [email protected](i32 addrspace(2)* %gds, i32 31, i32 0, i32 0, i1 false, i32 16777217, i1 true, i1 true)
43  %r = bitcast i32 %val to float
44  ret float %r
45}
46
47; FUNC-LABEL: {{^}}ds_ordered_add_gs:
48; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 31
49; GCN: s_mov_b32 m0, s0
50; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:772 gds
51; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0)
52define amdgpu_gs float @ds_ordered_add_gs(i32 addrspace(2)* inreg %gds) {
53  %val = call [email protected](i32 addrspace(2)* %gds, i32 31, i32 0, i32 0, i1 false, i32 16777217, i1 true, i1 true)
54  %r = bitcast i32 %val to float
55  ret float %r
56}
57
58declare i32 @llvm.amdgcn.ds.ordered.add(i32 addrspace(2)* nocapture, i32, i32, i32, i1, i32, i1, i1)
59