1; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s 2; XUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s 3 4; FIXME: Enable for VI. 5 6declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 7declare float @llvm.amdgcn.div.fmas.f32(float, float, float, i1) nounwind readnone 8declare double @llvm.amdgcn.div.fmas.f64(double, double, double, i1) nounwind readnone 9 10; GCN-LABEL: {{^}}test_div_fmas_f32: 11; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x13 12; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x1c 13; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x25 14 15; VI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x4c 16; VI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x70 17; VI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x94 18 19; GCN-DAG: s_bitcmp1_b32 s{{[0-9]+}}, 0 20 21; GCN-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]] 22; GCN-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] 23; GCN-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]] 24; GCN: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VA]], [[VB]], [[VC]] 25; GCN: buffer_store_dword [[RESULT]], 26define amdgpu_kernel void @test_div_fmas_f32(float addrspace(1)* %out, [8 x i32], float %a, [8 x i32], float %b, [8 x i32], float %c, [8 x i32], i1 %d) nounwind { 27 %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %d) nounwind readnone 28 store float %result, float addrspace(1)* %out, align 4 29 ret void 30} 31 32; GCN-LABEL: {{^}}test_div_fmas_f32_inline_imm_0: 33; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x1c 34; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x25 35; SI-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]] 36; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] 37; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], 1.0, [[VB]], [[VC]] 38; SI: buffer_store_dword [[RESULT]], 39define amdgpu_kernel void @test_div_fmas_f32_inline_imm_0(float addrspace(1)* %out, [8 x i32], float %a, [8 x i32], float %b, [8 x i32], float %c, [8 x i32], i1 %d) nounwind { 40 %result = call float @llvm.amdgcn.div.fmas.f32(float 1.0, float %b, float %c, i1 %d) nounwind readnone 41 store float %result, float addrspace(1)* %out, align 4 42 ret void 43} 44 45; GCN-LABEL: {{^}}test_div_fmas_f32_inline_imm_1: 46; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb 47; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd 48 49; VI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x4c 50; VI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x94 51 52; GCN-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]] 53; GCN-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]] 54; GCN: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VA]], 1.0, [[VC]] 55; GCN: buffer_store_dword [[RESULT]], 56define amdgpu_kernel void @test_div_fmas_f32_inline_imm_1(float addrspace(1)* %out, float %a, float %b, float %c, [8 x i32], i1 %d) nounwind { 57 %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float 1.0, float %c, i1 %d) nounwind readnone 58 store float %result, float addrspace(1)* %out, align 4 59 ret void 60} 61 62; GCN-LABEL: {{^}}test_div_fmas_f32_inline_imm_2: 63; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x13 64; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x1c 65 66; VI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x4c 67; VI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x70 68 69; GCN-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]] 70; GCN-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] 71; GCN: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VA]], [[VB]], 1.0 72; GCN: buffer_store_dword [[RESULT]], 73define amdgpu_kernel void @test_div_fmas_f32_inline_imm_2(float addrspace(1)* %out, [8 x i32], float %a, [8 x i32], float %b, [8 x i32], float %c, [8 x i32], i1 %d) nounwind { 74 %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float 1.0, i1 %d) nounwind readnone 75 store float %result, float addrspace(1)* %out, align 4 76 ret void 77} 78 79; GCN-LABEL: {{^}}test_div_fmas_f64: 80; GCN: v_div_fmas_f64 81define amdgpu_kernel void @test_div_fmas_f64(double addrspace(1)* %out, double %a, double %b, double %c, i1 %d) nounwind { 82 %result = call double @llvm.amdgcn.div.fmas.f64(double %a, double %b, double %c, i1 %d) nounwind readnone 83 store double %result, double addrspace(1)* %out, align 8 84 ret void 85} 86 87; GCN-LABEL: {{^}}test_div_fmas_f32_cond_to_vcc: 88; GCN: s_cmp_eq_u32 s{{[0-9]+}}, 0{{$}} 89; GCN: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} 90define amdgpu_kernel void @test_div_fmas_f32_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c, i32 %i) nounwind { 91 %cmp = icmp eq i32 %i, 0 92 %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %cmp) nounwind readnone 93 store float %result, float addrspace(1)* %out, align 4 94 ret void 95} 96 97; GCN-LABEL: {{^}}test_div_fmas_f32_imm_false_cond_to_vcc: 98; GCN: s_mov_b64 vcc, 0 99; GCN: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} 100define amdgpu_kernel void @test_div_fmas_f32_imm_false_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c) nounwind { 101 %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 false) nounwind readnone 102 store float %result, float addrspace(1)* %out, align 4 103 ret void 104} 105 106; GCN-LABEL: {{^}}test_div_fmas_f32_imm_true_cond_to_vcc: 107; GCN: s_mov_b64 vcc, -1 108; GCN: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} 109define amdgpu_kernel void @test_div_fmas_f32_imm_true_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c) nounwind { 110 %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 true) nounwind readnone 111 store float %result, float addrspace(1)* %out, align 4 112 ret void 113} 114 115; GCN-LABEL: {{^}}test_div_fmas_f32_logical_cond_to_vcc: 116; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}} 117; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 glc{{$}} 118; SI-DAG: buffer_load_dword [[C:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 glc{{$}} 119 120; SI-DAG: v_cmp_eq_u32_e32 [[CMP0:vcc]], 0, v{{[0-9]+}} 121; SI-DAG: s_cmp_lg_u32 s{{[0-9]+}}, 0{{$}} 122; SI-DAG: s_cselect_b64 [[CMP1:s\[[0-9]+:[0-9]+\]]], -1, 0 123; SI: s_and_b64 vcc, [[CMP0]], [[CMP1]] 124; SI: v_div_fmas_f32 {{v[0-9]+}}, [[A]], [[B]], [[C]] 125; SI: s_endpgm 126define amdgpu_kernel void @test_div_fmas_f32_logical_cond_to_vcc(float addrspace(1)* %out, float addrspace(1)* %in, i32 %d) nounwind { 127 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 128 %gep.a = getelementptr float, float addrspace(1)* %in, i32 %tid 129 %gep.b = getelementptr float, float addrspace(1)* %gep.a, i32 1 130 %gep.c = getelementptr float, float addrspace(1)* %gep.a, i32 2 131 %gep.out = getelementptr float, float addrspace(1)* %out, i32 2 132 133 %a = load volatile float, float addrspace(1)* %gep.a 134 %b = load volatile float, float addrspace(1)* %gep.b 135 %c = load volatile float, float addrspace(1)* %gep.c 136 137 %cmp0 = icmp eq i32 %tid, 0 138 %cmp1 = icmp ne i32 %d, 0 139 %and = and i1 %cmp0, %cmp1 140 141 %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %and) nounwind readnone 142 store float %result, float addrspace(1)* %gep.out, align 4 143 ret void 144} 145 146; GCN-LABEL: {{^}}test_div_fmas_f32_i1_phi_vcc: 147 148; SI: ; %entry 149; SI: v_cmp_eq_u32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], 0, {{v[0-9]+}} 150; SI: s_mov_b64 vcc, 0 151; SI: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[CMP]] 152 153; SI: ; %bb 154; SI: buffer_load_dword [[LOAD:v[0-9]+]], 155; SI: v_cmp_ne_u32_e32 vcc, 0, [[LOAD]] 156; SI: s_and_b64 vcc, vcc, exec 157 158; SI: ; %exit 159; SI: s_or_b64 exec, exec, [[SAVE]] 160; SI-NOT: vcc 161; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} 162; SI: buffer_store_dword 163; SI: s_endpgm 164 165define amdgpu_kernel void @test_div_fmas_f32_i1_phi_vcc(float addrspace(1)* %out, float addrspace(1)* %in, i32 addrspace(1)* %dummy) nounwind { 166entry: 167 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 168 %gep.out = getelementptr float, float addrspace(1)* %out, i32 2 169 %gep.a = getelementptr float, float addrspace(1)* %in, i32 %tid 170 %gep.b = getelementptr float, float addrspace(1)* %gep.a, i32 1 171 %gep.c = getelementptr float, float addrspace(1)* %gep.a, i32 2 172 173 %a = load float, float addrspace(1)* %gep.a 174 %b = load float, float addrspace(1)* %gep.b 175 %c = load float, float addrspace(1)* %gep.c 176 177 %cmp0 = icmp eq i32 %tid, 0 178 br i1 %cmp0, label %bb, label %exit 179 180bb: 181 %val = load i32, i32 addrspace(1)* %dummy 182 %cmp1 = icmp ne i32 %val, 0 183 br label %exit 184 185exit: 186 %cond = phi i1 [false, %entry], [%cmp1, %bb] 187 %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %cond) nounwind readnone 188 store float %result, float addrspace(1)* %gep.out, align 4 189 ret void 190} 191