1;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s
2;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
3
4;CHECK-LABEL: {{^}}buffer_store:
5;CHECK: buffer_store_format_xyzw v[0:3], s[0:3], 0
6;CHECK: buffer_store_format_xyzw v[4:7], s[0:3], 0 glc
7;CHECK: buffer_store_format_xyzw v[8:11], s[0:3], 0 slc
8define void @buffer_store(<4 x i32> inreg, <4 x float>, <4 x float>, <4 x float>) #0 {
9main_body:
10  call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 0, i1 0, i1 0)
11  call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %2, <4 x i32> %0, i32 0, i32 0, i1 1, i1 0)
12  call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %3, <4 x i32> %0, i32 0, i32 0, i1 0, i1 1)
13  ret void
14}
15
16;CHECK-LABEL: {{^}}buffer_store_immoffs:
17;CHECK: buffer_store_format_xyzw v[0:3], s[0:3], 0 offset:42
18define void @buffer_store_immoffs(<4 x i32> inreg, <4 x float>) #0 {
19main_body:
20  call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 42, i1 0, i1 0)
21  ret void
22}
23
24;CHECK-LABEL: {{^}}buffer_store_idx:
25;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen
26define void @buffer_store_idx(<4 x i32> inreg, <4 x float>, i32) #0 {
27main_body:
28  call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i1 0, i1 0)
29  ret void
30}
31
32;CHECK-LABEL: {{^}}buffer_store_ofs:
33;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 offen
34define void @buffer_store_ofs(<4 x i32> inreg, <4 x float>, i32) #0 {
35main_body:
36  call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 %2, i1 0, i1 0)
37  ret void
38}
39
40;CHECK-LABEL: {{^}}buffer_store_both:
41;CHECK: buffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 idxen offen
42define void @buffer_store_both(<4 x i32> inreg, <4 x float>, i32, i32) #0 {
43main_body:
44  call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 %3, i1 0, i1 0)
45  ret void
46}
47
48;CHECK-LABEL: {{^}}buffer_store_both_reversed:
49;CHECK: v_mov_b32_e32 v6, v4
50;CHECK: buffer_store_format_xyzw v[0:3], v[5:6], s[0:3], 0 idxen offen
51define void @buffer_store_both_reversed(<4 x i32> inreg, <4 x float>, i32, i32) #0 {
52main_body:
53  call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %3, i32 %2, i1 0, i1 0)
54  ret void
55}
56
57; Ideally, the register allocator would avoid the wait here
58;
59;CHECK-LABEL: {{^}}buffer_store_wait:
60;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen
61;CHECK: s_waitcnt vmcnt(0) expcnt(0)
62;CHECK: buffer_load_format_xyzw v[0:3], v5, s[0:3], 0 idxen
63;CHECK: s_waitcnt vmcnt(0)
64;CHECK: buffer_store_format_xyzw v[0:3], v6, s[0:3], 0 idxen
65define void @buffer_store_wait(<4 x i32> inreg, <4 x float>, i32, i32, i32) #0 {
66main_body:
67  call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i1 0, i1 0)
68  %data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 %3, i32 0, i1 0, i1 0)
69  call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %data, <4 x i32> %0, i32 %4, i32 0, i1 0, i1 0)
70  ret void
71}
72
73declare void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float>, <4 x i32>, i32, i32, i1, i1) #1
74declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #2
75
76attributes #0 = { "ShaderType"="0" }
77attributes #1 = { nounwind }
78attributes #2 = { nounwind readonly }
79