1;RUN: llc < %s -march=amdgcn -mcpu=gfx600 -verify-machineinstrs | FileCheck %s -check-prefixes=CHECK,SI
2;RUN: llc < %s -march=amdgcn -mcpu=gfx700 -verify-machineinstrs | FileCheck %s -check-prefixes=CHECK,GCNX3
3
4;CHECK-LABEL: {{^}}buffer_load_format_immoffs_x3:
5;SI: buffer_load_format_xyzw v[0:3], off, s[0:3], 0 offset:42
6;GCNX3: buffer_load_format_xyz v[0:2], off, s[0:3], 0 offset:42
7define amdgpu_ps <3 x float> @buffer_load_format_immoffs_x3(<4 x i32> inreg) {
8main_body:
9  %data = call <3 x float> @llvm.amdgcn.buffer.load.format.v3f32(<4 x i32> %0, i32 0, i32 42, i1 0, i1 0)
10  ret <3 x float> %data
11}
12
13;CHECK-LABEL: {{^}}buffer_load_immoffs_x3:
14;SI: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:40
15;GCNX3: buffer_load_dwordx3 v[0:2], off, s[0:3], 0 offset:40
16define amdgpu_ps <3 x float> @buffer_load_immoffs_x3(<4 x i32> inreg) {
17main_body:
18  %data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %0, i32 0, i32 40, i1 0, i1 0)
19  ret <3 x float> %data
20}
21
22;CHECK-LABEL: {{^}}buffer_raw_load_immoffs_x3:
23;SI: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:40
24;GCNX3: buffer_load_dwordx3 v[0:2], off, s[0:3], 0 offset:40
25define amdgpu_ps <3 x float> @buffer_raw_load_immoffs_x3(<4 x i32> inreg) {
26main_body:
27  %data = call <3 x float> @llvm.amdgcn.raw.buffer.load.v3f32(<4 x i32> %0, i32 40, i32 0, i32 0)
28  ret <3 x float> %data
29}
30
31;CHECK-LABEL: {{^}}buffer_struct_load_format_immoffs_x3:
32;SI: buffer_load_format_xyzw v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen offset:42
33;GCNX3: buffer_load_format_xyz v[0:2], {{v[0-9]+}}, s[0:3], 0 idxen offset:42
34define amdgpu_ps <3 x float> @buffer_struct_load_format_immoffs_x3(<4 x i32> inreg) {
35main_body:
36  %data = call <3 x float> @llvm.amdgcn.struct.buffer.load.format.v3f32(<4 x i32> %0, i32 0, i32 42, i32 0, i32 0)
37  ret <3 x float> %data
38}
39
40;CHECK-LABEL: {{^}}struct_buffer_load_immoffs_x3:
41;SI: buffer_load_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen offset:40
42;GCNX3: buffer_load_dwordx3 v[0:2], {{v[0-9]+}}, s[0:3], 0 idxen offset:40
43define amdgpu_ps <3 x float> @struct_buffer_load_immoffs_x3(<4 x i32> inreg) {
44main_body:
45  %data = call <3 x float> @llvm.amdgcn.struct.buffer.load.v3f32(<4 x i32> %0, i32 0, i32 40, i32 0, i32 0)
46  ret <3 x float> %data
47}
48
49declare <3 x float> @llvm.amdgcn.buffer.load.format.v3f32(<4 x i32>, i32, i32, i1, i1) #0
50declare <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32>, i32, i32, i1, i1) #0
51declare <3 x float> @llvm.amdgcn.raw.buffer.load.format.v3f32(<4 x i32>, i32, i32, i32) #0
52declare <3 x float> @llvm.amdgcn.raw.buffer.load.v3f32(<4 x i32>, i32, i32, i32) #0
53declare <3 x float> @llvm.amdgcn.struct.buffer.load.format.v3f32(<4 x i32>, i32, i32, i32, i32) #0
54declare <3 x float> @llvm.amdgcn.struct.buffer.load.v3f32(<4 x i32>, i32, i32, i32, i32) #0
55