1; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI,CIVI %s
2; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,CIVI %s
3; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
4; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -stop-before=machine-scheduler < %s | FileCheck -enable-var-scope -check-prefixes=MIR %s
5
6declare i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* nocapture, i32, i32, i32, i1) #2
7declare i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* nocapture, i32, i32, i32, i1) #2
8declare i32 @llvm.amdgcn.atomic.inc.i32.p0i32(i32* nocapture, i32, i32, i32, i1) #2
9
10declare i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* nocapture, i64, i32, i32, i1) #2
11declare i64 @llvm.amdgcn.atomic.inc.i64.p3i64(i64 addrspace(3)* nocapture, i64, i32, i32, i1) #2
12declare i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* nocapture, i64, i32, i32, i1) #2
13
14declare i32 @llvm.amdgcn.workitem.id.x() #1
15
16; GCN-LABEL: {{^}}lds_atomic_inc_ret_i32:
17; CIVI-DAG: s_mov_b32 m0
18; GFX9-NOT: m0
19
20; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 42
21; GCN: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[K]]
22; MIR-LABEL: @lds_atomic_inc_ret_i32
23; MIR: DS_INC_RTN_U32 {{.*}} :: (load store (s32) on %{{.*}}, !noalias !{{[0-9]+}}, addrspace 3)
24define amdgpu_kernel void @lds_atomic_inc_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) #0 {
25  %result = call i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* %ptr, i32 42, i32 0, i32 0, i1 false), !noalias !0
26  store i32 %result, i32 addrspace(1)* %out
27  ret void
28}
29
30!0 = !{!1}
31!1 = distinct !{!1, !2}
32!2 = distinct !{!2}
33
34; GCN-LABEL: {{^}}lds_atomic_inc_ret_i32_offset:
35; CIVI-DAG: s_mov_b32 m0
36; GFX9-NOT: m0
37
38; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 42
39; GCN: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[K]] offset:16
40define amdgpu_kernel void @lds_atomic_inc_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) #0 {
41  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
42  %result = call i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* %gep, i32 42, i32 0, i32 0, i1 false)
43  store i32 %result, i32 addrspace(1)* %out
44  ret void
45}
46
47; GCN-LABEL: {{^}}lds_atomic_inc_noret_i32:
48; CIVI-DAG: s_mov_b32 m0
49; GFX9-NOT: m0
50
51; GCN-DAG: s_load_dword [[SPTR:s[0-9]+]],
52; GCN-DAG: v_mov_b32_e32 [[DATA:v[0-9]+]], 4
53; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
54; GCN: ds_inc_u32 [[VPTR]], [[DATA]]
55define amdgpu_kernel void @lds_atomic_inc_noret_i32(i32 addrspace(3)* %ptr) nounwind {
56  %result = call i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* %ptr, i32 42, i32 0, i32 0, i1 false)
57  ret void
58}
59
60; GCN-LABEL: {{^}}lds_atomic_inc_noret_i32_offset:
61; CIVI-DAG: s_mov_b32 m0
62; GFX9-NOT: m0
63
64; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 42
65; GCN: ds_inc_u32 v{{[0-9]+}}, [[K]] offset:16
66define amdgpu_kernel void @lds_atomic_inc_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind {
67  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
68  %result = call i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* %gep, i32 42, i32 0, i32 0, i1 false)
69  ret void
70}
71
72; GCN-LABEL: {{^}}global_atomic_inc_ret_i32:
73; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
74; CIVI: buffer_atomic_inc [[K]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 glc{{$}}
75; GFX9: global_atomic_inc v{{[0-9]+}}, v{{[0-9]+}}, [[K]], s{{\[[0-9]+:[0-9]+\]}} glc{{$}}
76define amdgpu_kernel void @global_atomic_inc_ret_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 {
77  %result = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %ptr, i32 42, i32 0, i32 0, i1 false)
78  store i32 %result, i32 addrspace(1)* %out
79  ret void
80}
81
82; GCN-LABEL: {{^}}global_atomic_inc_ret_i32_offset:
83; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
84; CIVI: buffer_atomic_inc [[K]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:16 glc{{$}}
85; GFX9: global_atomic_inc v{{[0-9]+}}, v{{[0-9]+}}, [[K]], s{{\[[0-9]+:[0-9]+\]}} offset:16 glc{{$}}
86define amdgpu_kernel void @global_atomic_inc_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 {
87  %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
88  %result = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %gep, i32 42, i32 0, i32 0, i1 false)
89  store i32 %result, i32 addrspace(1)* %out
90  ret void
91}
92
93; GCN-LABEL: {{^}}global_atomic_inc_noret_i32:
94; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
95; CIVI: buffer_atomic_inc [[K]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
96; GFX9: global_atomic_inc v{{[0-9]+}}, [[K]], s{{\[[0-9]+:[0-9]+\]$}}
97define amdgpu_kernel void @global_atomic_inc_noret_i32(i32 addrspace(1)* %ptr) nounwind {
98  %result = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %ptr, i32 42, i32 0, i32 0, i1 false)
99  ret void
100}
101
102; GCN-LABEL: {{^}}global_atomic_inc_noret_i32_offset:
103; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
104; CIVI: buffer_atomic_inc [[K]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:16{{$}}
105; GFX9: global_atomic_inc v{{[0-9]+}}, [[K]], s{{\[[0-9]+:[0-9]+\]}} offset:16{{$}}
106define amdgpu_kernel void @global_atomic_inc_noret_i32_offset(i32 addrspace(1)* %ptr) nounwind {
107  %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
108  %result = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %gep, i32 42, i32 0, i32 0, i1 false)
109  ret void
110}
111
112; GCN-LABEL: {{^}}global_atomic_inc_ret_i32_offset_addr64:
113; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
114; CI: buffer_atomic_inc [[K]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:20 glc{{$}}
115; VI: flat_atomic_inc v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}}
116define amdgpu_kernel void @global_atomic_inc_ret_i32_offset_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 {
117  %id = call i32 @llvm.amdgcn.workitem.id.x()
118  %gep.tid = getelementptr i32, i32 addrspace(1)* %ptr, i32 %id
119  %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id
120  %gep = getelementptr i32, i32 addrspace(1)* %gep.tid, i32 5
121  %result = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %gep, i32 42, i32 0, i32 0, i1 false)
122  store i32 %result, i32 addrspace(1)* %out.gep
123  ret void
124}
125
126; GCN-LABEL: {{^}}global_atomic_inc_noret_i32_offset_addr64:
127; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
128; CI: buffer_atomic_inc [[K]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:20{{$}}
129; VI: flat_atomic_inc v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}}
130define amdgpu_kernel void @global_atomic_inc_noret_i32_offset_addr64(i32 addrspace(1)* %ptr) #0 {
131  %id = call i32 @llvm.amdgcn.workitem.id.x()
132  %gep.tid = getelementptr i32, i32 addrspace(1)* %ptr, i32 %id
133  %gep = getelementptr i32, i32 addrspace(1)* %gep.tid, i32 5
134  %result = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %gep, i32 42, i32 0, i32 0, i1 false)
135  ret void
136}
137
138@lds0 = addrspace(3) global [512 x i32] undef, align 4
139
140; GCN-LABEL: {{^}}atomic_inc_shl_base_lds_0_i32:
141; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
142; GCN: ds_inc_rtn_u32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8
143define amdgpu_kernel void @atomic_inc_shl_base_lds_0_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
144  %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1
145  %idx.0 = add nsw i32 %tid.x, 2
146  %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds0, i32 0, i32 %idx.0
147  %val0 = call i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* %arrayidx0, i32 9, i32 0, i32 0, i1 false)
148  store i32 %idx.0, i32 addrspace(1)* %add_use
149  store i32 %val0, i32 addrspace(1)* %out
150  ret void
151}
152
153; GCN-LABEL: {{^}}lds_atomic_inc_ret_i64:
154; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
155; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
156; GCN: ds_inc_rtn_u64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}}{{$}}
157define amdgpu_kernel void @lds_atomic_inc_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) #0 {
158  %result = call i64 @llvm.amdgcn.atomic.inc.i64.p3i64(i64 addrspace(3)* %ptr, i64 42, i32 0, i32 0, i1 false)
159  store i64 %result, i64 addrspace(1)* %out
160  ret void
161}
162
163; GCN-LABEL: {{^}}lds_atomic_inc_ret_i64_offset:
164; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
165; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
166; GCN: ds_inc_rtn_u64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:32
167define amdgpu_kernel void @lds_atomic_inc_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) #0 {
168  %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
169  %result = call i64 @llvm.amdgcn.atomic.inc.i64.p3i64(i64 addrspace(3)* %gep, i64 42, i32 0, i32 0, i1 false)
170  store i64 %result, i64 addrspace(1)* %out
171  ret void
172}
173
174; GCN-LABEL: {{^}}lds_atomic_inc_noret_i64:
175; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
176; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
177; GCN: ds_inc_u64 v{{[0-9]+}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}}{{$}}
178define amdgpu_kernel void @lds_atomic_inc_noret_i64(i64 addrspace(3)* %ptr) nounwind {
179  %result = call i64 @llvm.amdgcn.atomic.inc.i64.p3i64(i64 addrspace(3)* %ptr, i64 42, i32 0, i32 0, i1 false)
180  ret void
181}
182
183; GCN-LABEL: {{^}}lds_atomic_inc_noret_i64_offset:
184; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
185; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
186; GCN: ds_inc_u64 v{{[0-9]+}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:32{{$}}
187define amdgpu_kernel void @lds_atomic_inc_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind {
188  %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
189  %result = call i64 @llvm.amdgcn.atomic.inc.i64.p3i64(i64 addrspace(3)* %gep, i64 42, i32 0, i32 0, i1 false)
190  ret void
191}
192
193; GCN-LABEL: {{^}}global_atomic_inc_ret_i64:
194; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
195; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
196; GFX9: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
197; CIVI: buffer_atomic_inc_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 glc{{$}}
198; GFX9: global_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v[[ZERO]], v{{\[}}[[KLO]]:[[KHI]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}} glc{{$}}
199define amdgpu_kernel void @global_atomic_inc_ret_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 {
200  %result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %ptr, i64 42, i32 0, i32 0, i1 false)
201  store i64 %result, i64 addrspace(1)* %out
202  ret void
203}
204
205; GCN-LABEL: {{^}}global_atomic_inc_ret_i64_offset:
206; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
207; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
208; GFX9: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
209; CIVI: buffer_atomic_inc_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:32 glc{{$}}
210; GFX9: global_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v[[ZERO]], v{{\[}}[[KLO]]:[[KHI]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}} offset:32 glc{{$}}
211define amdgpu_kernel void @global_atomic_inc_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 {
212  %gep = getelementptr i64, i64 addrspace(1)* %ptr, i32 4
213  %result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false)
214  store i64 %result, i64 addrspace(1)* %out
215  ret void
216}
217
218; GCN-LABEL: {{^}}global_atomic_inc_noret_i64:
219; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
220; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
221; GFX9: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
222; CIVI: buffer_atomic_inc_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
223
224; GFX9: global_atomic_inc_x2 v[[ZERO]], v{{\[}}[[KLO]]:[[KHI]]{{\]}}, s{{\[[0-9]+:[0-9]+\]$}}
225define amdgpu_kernel void @global_atomic_inc_noret_i64(i64 addrspace(1)* %ptr) nounwind {
226  %result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %ptr, i64 42, i32 0, i32 0, i1 false)
227  ret void
228}
229
230; GCN-LABEL: {{^}}global_atomic_inc_noret_i64_offset:
231; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
232; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
233; GFX9: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
234; CIVI: buffer_atomic_inc_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:32{{$}}
235; GFX9: global_atomic_inc_x2 v[[ZERO]], v{{\[}}[[KLO]]:[[KHI]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}} offset:32{{$}}
236define amdgpu_kernel void @global_atomic_inc_noret_i64_offset(i64 addrspace(1)* %ptr) nounwind {
237  %gep = getelementptr i64, i64 addrspace(1)* %ptr, i32 4
238  %result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false)
239  ret void
240}
241
242; GCN-LABEL: {{^}}global_atomic_inc_ret_i64_offset_addr64:
243; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
244; CI: v_mov_b32_e32 v{{[0-9]+}}, 0{{$}}
245; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
246; CI: buffer_atomic_inc_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:40 glc{{$}}
247; VI: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}}
248define amdgpu_kernel void @global_atomic_inc_ret_i64_offset_addr64(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 {
249  %id = call i32 @llvm.amdgcn.workitem.id.x()
250  %gep.tid = getelementptr i64, i64 addrspace(1)* %ptr, i32 %id
251  %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id
252  %gep = getelementptr i64, i64 addrspace(1)* %gep.tid, i32 5
253  %result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false)
254  store i64 %result, i64 addrspace(1)* %out.gep
255  ret void
256}
257
258; GCN-LABEL: {{^}}global_atomic_inc_noret_i64_offset_addr64:
259; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
260; CI: v_mov_b32_e32 v{{[0-9]+}}, 0{{$}}
261; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
262; CI: buffer_atomic_inc_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:40{{$}}
263; VI: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}}{{$}}
264define amdgpu_kernel void @global_atomic_inc_noret_i64_offset_addr64(i64 addrspace(1)* %ptr) #0 {
265  %id = call i32 @llvm.amdgcn.workitem.id.x()
266  %gep.tid = getelementptr i64, i64 addrspace(1)* %ptr, i32 %id
267  %gep = getelementptr i64, i64 addrspace(1)* %gep.tid, i32 5
268  %result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false)
269  ret void
270}
271
272; GCN-LABEL: {{^}}flat_atomic_inc_ret_i32:
273; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
274; GCN: flat_atomic_inc v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}}
275define amdgpu_kernel void @flat_atomic_inc_ret_i32(i32* %out, i32* %ptr) #0 {
276  %result = call i32 @llvm.amdgcn.atomic.inc.i32.p0i32(i32* %ptr, i32 42, i32 0, i32 0, i1 false)
277  store i32 %result, i32* %out
278  ret void
279}
280
281; GCN-LABEL: {{^}}flat_atomic_inc_ret_i32_offset:
282; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
283; CIVI: flat_atomic_inc v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}}
284; GFX9: flat_atomic_inc v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] offset:16 glc{{$}}
285define amdgpu_kernel void @flat_atomic_inc_ret_i32_offset(i32* %out, i32* %ptr) #0 {
286  %gep = getelementptr i32, i32* %ptr, i32 4
287  %result = call i32 @llvm.amdgcn.atomic.inc.i32.p0i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
288  store i32 %result, i32* %out
289  ret void
290}
291
292; GCN-LABEL: {{^}}flat_atomic_inc_noret_i32:
293; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
294; GCN: flat_atomic_inc v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}}
295define amdgpu_kernel void @flat_atomic_inc_noret_i32(i32* %ptr) nounwind {
296  %result = call i32 @llvm.amdgcn.atomic.inc.i32.p0i32(i32* %ptr, i32 42, i32 0, i32 0, i1 false)
297  ret void
298}
299
300; GCN-LABEL: {{^}}flat_atomic_inc_noret_i32_offset:
301; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
302; CIVI: flat_atomic_inc v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}}
303; GFX9: flat_atomic_inc v{{\[[0-9]+:[0-9]+\]}}, [[K]] offset:16{{$}}
304define amdgpu_kernel void @flat_atomic_inc_noret_i32_offset(i32* %ptr) nounwind {
305  %gep = getelementptr i32, i32* %ptr, i32 4
306  %result = call i32 @llvm.amdgcn.atomic.inc.i32.p0i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
307  ret void
308}
309
310; GCN-LABEL: {{^}}flat_atomic_inc_ret_i32_offset_addr64:
311; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
312; CIVI: flat_atomic_inc v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}}
313; GFX9: flat_atomic_inc v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] offset:20 glc{{$}}
314define amdgpu_kernel void @flat_atomic_inc_ret_i32_offset_addr64(i32* %out, i32* %ptr) #0 {
315  %id = call i32 @llvm.amdgcn.workitem.id.x()
316  %gep.tid = getelementptr i32, i32* %ptr, i32 %id
317  %out.gep = getelementptr i32, i32* %out, i32 %id
318  %gep = getelementptr i32, i32* %gep.tid, i32 5
319  %result = call i32 @llvm.amdgcn.atomic.inc.i32.p0i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
320  store i32 %result, i32* %out.gep
321  ret void
322}
323
324; GCN-LABEL: {{^}}flat_atomic_inc_noret_i32_offset_addr64:
325; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
326; CIVI: flat_atomic_inc v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}}
327; GFX9: flat_atomic_inc v{{\[[0-9]+:[0-9]+\]}}, [[K]] offset:20{{$}}
328define amdgpu_kernel void @flat_atomic_inc_noret_i32_offset_addr64(i32* %ptr) #0 {
329  %id = call i32 @llvm.amdgcn.workitem.id.x()
330  %gep.tid = getelementptr i32, i32* %ptr, i32 %id
331  %gep = getelementptr i32, i32* %gep.tid, i32 5
332  %result = call i32 @llvm.amdgcn.atomic.inc.i32.p0i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
333  ret void
334}
335
336@lds1 = addrspace(3) global [512 x i64] undef, align 8
337
338; GCN-LABEL: {{^}}atomic_inc_shl_base_lds_0_i64:
339; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 3, {{v[0-9]+}}
340; GCN: ds_inc_rtn_u64 v{{\[[0-9]+:[0-9]+\]}}, [[PTR]], v{{\[[0-9]+:[0-9]+\]}} offset:16
341define amdgpu_kernel void @atomic_inc_shl_base_lds_0_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
342  %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1
343  %idx.0 = add nsw i32 %tid.x, 2
344  %arrayidx0 = getelementptr inbounds [512 x i64], [512 x i64] addrspace(3)* @lds1, i32 0, i32 %idx.0
345  %val0 = call i64 @llvm.amdgcn.atomic.inc.i64.p3i64(i64 addrspace(3)* %arrayidx0, i64 9, i32 0, i32 0, i1 false)
346  store i32 %idx.0, i32 addrspace(1)* %add_use
347  store i64 %val0, i64 addrspace(1)* %out
348  ret void
349}
350
351; GCN-LABEL: {{^}}flat_atomic_inc_ret_i64:
352; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
353; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
354; GCN: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}}
355define amdgpu_kernel void @flat_atomic_inc_ret_i64(i64* %out, i64* %ptr) #0 {
356  %result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %ptr, i64 42, i32 0, i32 0, i1 false)
357  store i64 %result, i64* %out
358  ret void
359}
360
361; GCN-LABEL: {{^}}flat_atomic_inc_ret_i64_offset:
362; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
363; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
364; CIVI: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}}
365; GFX9: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:32 glc{{$}}
366define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset(i64* %out, i64* %ptr) #0 {
367  %gep = getelementptr i64, i64* %ptr, i32 4
368  %result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
369  store i64 %result, i64* %out
370  ret void
371}
372
373; GCN-LABEL: {{^}}flat_atomic_inc_noret_i64:
374; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
375; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
376; GCN: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}}
377define amdgpu_kernel void @flat_atomic_inc_noret_i64(i64* %ptr) nounwind {
378  %result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %ptr, i64 42, i32 0, i32 0, i1 false)
379  ret void
380}
381
382; GCN-LABEL: {{^}}flat_atomic_inc_noret_i64_offset:
383; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
384; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
385; CIVI: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}}
386; GFX9: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:32{{$}}
387define amdgpu_kernel void @flat_atomic_inc_noret_i64_offset(i64* %ptr) nounwind {
388  %gep = getelementptr i64, i64* %ptr, i32 4
389  %result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
390  ret void
391}
392
393; GCN-LABEL: {{^}}flat_atomic_inc_ret_i64_offset_addr64:
394; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
395; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
396; CIVI: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}}
397; GFX9: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:40 glc{{$}}
398define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset_addr64(i64* %out, i64* %ptr) #0 {
399  %id = call i32 @llvm.amdgcn.workitem.id.x()
400  %gep.tid = getelementptr i64, i64* %ptr, i32 %id
401  %out.gep = getelementptr i64, i64* %out, i32 %id
402  %gep = getelementptr i64, i64* %gep.tid, i32 5
403  %result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
404  store i64 %result, i64* %out.gep
405  ret void
406}
407
408; GCN-LABEL: {{^}}flat_atomic_inc_noret_i64_offset_addr64:
409; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
410; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
411; CIVI: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}}
412; GFX9: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:40{{$}}
413define amdgpu_kernel void @flat_atomic_inc_noret_i64_offset_addr64(i64* %ptr) #0 {
414  %id = call i32 @llvm.amdgcn.workitem.id.x()
415  %gep.tid = getelementptr i64, i64* %ptr, i32 %id
416  %gep = getelementptr i64, i64* %gep.tid, i32 5
417  %result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
418  ret void
419}
420
421; GCN-LABEL: {{^}}nocse_lds_atomic_inc_ret_i32:
422; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
423; GCN: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[K]]
424; GCN: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[K]]
425define amdgpu_kernel void @nocse_lds_atomic_inc_ret_i32(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 addrspace(3)* %ptr) #0 {
426  %result0 = call i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* %ptr, i32 42, i32 0, i32 0, i1 false)
427  %result1 = call i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* %ptr, i32 42, i32 0, i32 0, i1 false)
428
429  store i32 %result0, i32 addrspace(1)* %out0
430  store i32 %result1, i32 addrspace(1)* %out1
431  ret void
432}
433
434attributes #0 = { nounwind }
435attributes #1 = { nounwind readnone }
436attributes #2 = { nounwind argmemonly }
437