1; RUN: llc < %s -march=amdgcn -mcpu=gfx908 -verify-machineinstrs | FileCheck %s -check-prefix=GCN
2
3declare void @llvm.amdgcn.buffer.atomic.fadd.f32(float, <4 x i32>, i32, i32, i1)
4declare void @llvm.amdgcn.buffer.atomic.fadd.v2f16(<2 x half>, <4 x i32>, i32, i32, i1)
5declare void @llvm.amdgcn.global.atomic.fadd.p1f32.f32(float addrspace(1)*, float)
6declare void @llvm.amdgcn.global.atomic.fadd.p1v2f16.v2f16(<2 x half> addrspace(1)*, <2 x half>)
7
8; GCN-LABEL: {{^}}buffer_atomic_add_f32:
9; GCN: buffer_atomic_add_f32 v0, v1, s[0:3], 0 idxen
10define amdgpu_ps void @buffer_atomic_add_f32(<4 x i32> inreg %rsrc, float %data, i32 %vindex) {
11main_body:
12  call void @llvm.amdgcn.buffer.atomic.fadd.f32(float %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
13  ret void
14}
15
16; GCN-LABEL: {{^}}buffer_atomic_add_f32_off4_slc:
17; GCN: buffer_atomic_add_f32 v0, v1, s[0:3], 0 idxen offset:4 slc
18define amdgpu_ps void @buffer_atomic_add_f32_off4_slc(<4 x i32> inreg %rsrc, float %data, i32 %vindex) {
19main_body:
20  call void @llvm.amdgcn.buffer.atomic.fadd.f32(float %data, <4 x i32> %rsrc, i32 %vindex, i32 4, i1 1)
21  ret void
22}
23
24; GCN-LABEL: {{^}}buffer_atomic_pk_add_v2f16:
25; GCN: buffer_atomic_pk_add_f16 v0, v1, s[0:3], 0 idxen
26define amdgpu_ps void @buffer_atomic_pk_add_v2f16(<4 x i32> inreg %rsrc, <2 x half> %data, i32 %vindex) {
27main_body:
28  call void @llvm.amdgcn.buffer.atomic.fadd.v2f16(<2 x half> %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
29  ret void
30}
31
32; GCN-LABEL: {{^}}buffer_atomic_pk_add_v2f16_off4_slc:
33; GCN: buffer_atomic_pk_add_f16 v0, v1, s[0:3], 0 idxen offset:4 slc
34define amdgpu_ps void @buffer_atomic_pk_add_v2f16_off4_slc(<4 x i32> inreg %rsrc, <2 x half> %data, i32 %vindex) {
35main_body:
36  call void @llvm.amdgcn.buffer.atomic.fadd.v2f16(<2 x half> %data, <4 x i32> %rsrc, i32 %vindex, i32 4, i1 1)
37  ret void
38}
39
40; GCN-LABEL: {{^}}global_atomic_add_f32:
41; GCN: global_atomic_add_f32 v[{{[0-9:]+}}], v{{[0-9]+}}, off
42define amdgpu_kernel void @global_atomic_add_f32(float addrspace(1)* %ptr, float %data) {
43main_body:
44  call void @llvm.amdgcn.global.atomic.fadd.p1f32.f32(float addrspace(1)* %ptr, float %data)
45  ret void
46}
47
48; GCN-LABEL: {{^}}global_atomic_add_f32_off4:
49; GCN: global_atomic_add_f32 v[{{[0-9:]+}}], v{{[0-9]+}}, off offset:4
50define amdgpu_kernel void @global_atomic_add_f32_off4(float addrspace(1)* %ptr, float %data) {
51main_body:
52  %p = getelementptr float, float addrspace(1)* %ptr, i64 1
53  call void @llvm.amdgcn.global.atomic.fadd.p1f32.f32(float addrspace(1)* %p, float %data)
54  ret void
55}
56
57; GCN-LABEL: {{^}}global_atomic_pk_add_v2f16:
58; GCN: global_atomic_pk_add_f16 v[{{[0-9:]+}}], v{{[0-9]+}}, off
59define amdgpu_kernel void @global_atomic_pk_add_v2f16(<2 x half> addrspace(1)* %ptr, <2 x half> %data) {
60main_body:
61  call void @llvm.amdgcn.global.atomic.fadd.p1v2f16.v2f16(<2 x half> addrspace(1)* %ptr, <2 x half> %data)
62  ret void
63}
64
65; GCN-LABEL: {{^}}global_atomic_pk_add_v2f16_off4:
66; GCN: global_atomic_pk_add_f16 v[{{[0-9:]+}}], v{{[0-9]+}}, off offset:4
67define amdgpu_kernel void @global_atomic_pk_add_v2f16_off4(<2 x half> addrspace(1)* %ptr, <2 x half> %data) {
68main_body:
69  %p = getelementptr <2 x half>, <2 x half> addrspace(1)* %ptr, i64 1
70  call void @llvm.amdgcn.global.atomic.fadd.p1v2f16.v2f16(<2 x half> addrspace(1)* %p, <2 x half> %data)
71  ret void
72}
73
74; Make sure this artificially selects with an incorrect subtarget, but
75; the feature set.
76; GCN-LABEL: {{^}}global_atomic_fadd_f32_wrong_subtarget:
77; GCN: global_atomic_add_f32 v[{{[0-9:]+}}], v{{[0-9]+}}, off
78define amdgpu_kernel void @global_atomic_fadd_f32_wrong_subtarget(float addrspace(1)* %ptr, float %data) #0 {
79  call void @llvm.amdgcn.global.atomic.fadd.p1f32.f32(float addrspace(1)* %ptr, float %data)
80  ret void
81}
82
83attributes #0 = { "target-cpu"="gfx803" "target-features"="+atomic-fadd-insts" }
84