1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=machinelicm -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
3
4---
5name: hoist_move
6tracksRegLiveness: true
7body:             |
8  ; GCN-LABEL: name: hoist_move
9  ; GCN: bb.0:
10  ; GCN-NEXT:   successors: %bb.1(0x80000000)
11  ; GCN-NEXT: {{  $}}
12  ; GCN-NEXT:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
13  ; GCN-NEXT:   S_BRANCH %bb.1
14  ; GCN-NEXT: {{  $}}
15  ; GCN-NEXT: bb.1:
16  ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
17  ; GCN-NEXT: {{  $}}
18  ; GCN-NEXT:   $exec = S_OR_B64 $exec, 1, implicit-def $scc
19  ; GCN-NEXT:   S_CBRANCH_EXECNZ %bb.1, implicit $exec
20  ; GCN-NEXT:   S_BRANCH %bb.2
21  ; GCN-NEXT: {{  $}}
22  ; GCN-NEXT: bb.2:
23  ; GCN-NEXT:   S_ENDPGM 0
24  bb.0:
25    S_BRANCH %bb.1
26
27  bb.1:
28    %0:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
29    $exec = S_OR_B64 $exec, 1, implicit-def $scc
30    S_CBRANCH_EXECNZ %bb.1, implicit $exec
31    S_BRANCH %bb.2
32
33  bb.2:
34    S_ENDPGM 0
35...
36---
37name: no_hoist_cmp
38tracksRegLiveness: true
39body:             |
40  ; GCN-LABEL: name: no_hoist_cmp
41  ; GCN: bb.0:
42  ; GCN-NEXT:   successors: %bb.1(0x80000000)
43  ; GCN-NEXT: {{  $}}
44  ; GCN-NEXT:   S_BRANCH %bb.1
45  ; GCN-NEXT: {{  $}}
46  ; GCN-NEXT: bb.1:
47  ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
48  ; GCN-NEXT: {{  $}}
49  ; GCN-NEXT:   [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 1, 2, implicit $exec
50  ; GCN-NEXT:   $exec = S_OR_B64 $exec, 1, implicit-def $scc
51  ; GCN-NEXT:   S_CBRANCH_EXECNZ %bb.1, implicit $exec
52  ; GCN-NEXT:   S_BRANCH %bb.2
53  ; GCN-NEXT: {{  $}}
54  ; GCN-NEXT: bb.2:
55  ; GCN-NEXT:   S_ENDPGM 0
56  bb.0:
57    S_BRANCH %bb.1
58
59  bb.1:
60    %0:sreg_64 = V_CMP_EQ_U32_e64 1, 2, implicit $exec
61    $exec = S_OR_B64 $exec, 1, implicit-def $scc
62    S_CBRANCH_EXECNZ %bb.1, implicit $exec
63    S_BRANCH %bb.2
64
65  bb.2:
66    S_ENDPGM 0
67...
68---
69name: no_hoist_readfirstlane
70tracksRegLiveness: true
71body:             |
72  ; GCN-LABEL: name: no_hoist_readfirstlane
73  ; GCN: bb.0:
74  ; GCN-NEXT:   successors: %bb.1(0x80000000)
75  ; GCN-NEXT: {{  $}}
76  ; GCN-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
77  ; GCN-NEXT:   S_BRANCH %bb.1
78  ; GCN-NEXT: {{  $}}
79  ; GCN-NEXT: bb.1:
80  ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
81  ; GCN-NEXT: {{  $}}
82  ; GCN-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[DEF]], implicit $exec
83  ; GCN-NEXT:   $exec = S_OR_B64 $exec, 1, implicit-def $scc
84  ; GCN-NEXT:   S_CBRANCH_EXECNZ %bb.1, implicit $exec
85  ; GCN-NEXT:   S_BRANCH %bb.2
86  ; GCN-NEXT: {{  $}}
87  ; GCN-NEXT: bb.2:
88  ; GCN-NEXT:   S_ENDPGM 0
89  bb.0:
90    %0:vgpr_32 = IMPLICIT_DEF
91    S_BRANCH %bb.1
92
93  bb.1:
94    %1:sgpr_32 = V_READFIRSTLANE_B32 %0:vgpr_32, implicit $exec
95    $exec = S_OR_B64 $exec, 1, implicit-def $scc
96    S_CBRANCH_EXECNZ %bb.1, implicit $exec
97    S_BRANCH %bb.2
98
99  bb.2:
100    S_ENDPGM 0
101...
102---
103name: no_hoist_cndmask_e64
104tracksRegLiveness: true
105body:             |
106  ; GCN-LABEL: name: no_hoist_cndmask_e64
107  ; GCN: bb.0:
108  ; GCN-NEXT:   successors: %bb.1(0x80000000)
109  ; GCN-NEXT: {{  $}}
110  ; GCN-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
111  ; GCN-NEXT:   [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
112  ; GCN-NEXT:   S_BRANCH %bb.1
113  ; GCN-NEXT: {{  $}}
114  ; GCN-NEXT: bb.1:
115  ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
116  ; GCN-NEXT: {{  $}}
117  ; GCN-NEXT:   [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[DEF]], 0, [[DEF]], [[DEF1]], implicit $exec
118  ; GCN-NEXT:   $exec = S_OR_B64 $exec, 1, implicit-def $scc
119  ; GCN-NEXT:   S_CBRANCH_EXECNZ %bb.1, implicit $exec
120  ; GCN-NEXT:   S_BRANCH %bb.2
121  ; GCN-NEXT: {{  $}}
122  ; GCN-NEXT: bb.2:
123  ; GCN-NEXT:   S_ENDPGM 0
124  bb.0:
125    %0:vgpr_32 = IMPLICIT_DEF
126    %1:sreg_64_xexec = IMPLICIT_DEF
127    S_BRANCH %bb.1
128
129  bb.1:
130    %2:vgpr_32 = V_CNDMASK_B32_e64 0, %0, 0, %0, %1, implicit $exec
131    $exec = S_OR_B64 $exec, 1, implicit-def $scc
132    S_CBRANCH_EXECNZ %bb.1, implicit $exec
133    S_BRANCH %bb.2
134
135  bb.2:
136    S_ENDPGM 0
137...
138---
139name: no_hoist_cndmask_e32
140tracksRegLiveness: true
141body:             |
142  ; GCN-LABEL: name: no_hoist_cndmask_e32
143  ; GCN: bb.0:
144  ; GCN-NEXT:   successors: %bb.1(0x80000000)
145  ; GCN-NEXT: {{  $}}
146  ; GCN-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
147  ; GCN-NEXT:   [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
148  ; GCN-NEXT:   S_BRANCH %bb.1
149  ; GCN-NEXT: {{  $}}
150  ; GCN-NEXT: bb.1:
151  ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
152  ; GCN-NEXT: {{  $}}
153  ; GCN-NEXT:   [[V_CNDMASK_B32_e32_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e32 [[DEF]], [[DEF]], implicit undef $vcc, implicit $exec
154  ; GCN-NEXT:   $exec = S_OR_B64 $exec, 1, implicit-def $scc
155  ; GCN-NEXT:   S_CBRANCH_EXECNZ %bb.1, implicit $exec
156  ; GCN-NEXT:   S_BRANCH %bb.2
157  ; GCN-NEXT: {{  $}}
158  ; GCN-NEXT: bb.2:
159  ; GCN-NEXT:   S_ENDPGM 0
160  bb.0:
161    %0:vgpr_32 = IMPLICIT_DEF
162    %1:sreg_64_xexec = IMPLICIT_DEF
163    S_BRANCH %bb.1
164
165  bb.1:
166    %2:vgpr_32 = V_CNDMASK_B32_e32 %0, %0, implicit undef $vcc, implicit $exec
167    $exec = S_OR_B64 $exec, 1, implicit-def $scc
168    S_CBRANCH_EXECNZ %bb.1, implicit $exec
169    S_BRANCH %bb.2
170
171  bb.2:
172    S_ENDPGM 0
173...
174---
175name: no_hoist_cndmask_dpp
176tracksRegLiveness: true
177body:             |
178  ; GCN-LABEL: name: no_hoist_cndmask_dpp
179  ; GCN: bb.0:
180  ; GCN-NEXT:   successors: %bb.1(0x80000000)
181  ; GCN-NEXT: {{  $}}
182  ; GCN-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
183  ; GCN-NEXT:   [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
184  ; GCN-NEXT:   S_BRANCH %bb.1
185  ; GCN-NEXT: {{  $}}
186  ; GCN-NEXT: bb.1:
187  ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
188  ; GCN-NEXT: {{  $}}
189  ; GCN-NEXT:   [[V_CNDMASK_B32_dpp:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_dpp [[DEF]], 0, [[DEF]], 0, [[DEF]], 1, 15, 15, 10, implicit $exec, implicit undef $vcc
190  ; GCN-NEXT:   $exec = S_OR_B64 $exec, 1, implicit-def $scc
191  ; GCN-NEXT:   S_CBRANCH_EXECNZ %bb.1, implicit $exec
192  ; GCN-NEXT:   S_BRANCH %bb.2
193  ; GCN-NEXT: {{  $}}
194  ; GCN-NEXT: bb.2:
195  ; GCN-NEXT:   S_ENDPGM 0
196  bb.0:
197    %0:vgpr_32 = IMPLICIT_DEF
198    %1:sreg_64_xexec = IMPLICIT_DEF
199    S_BRANCH %bb.1
200
201  bb.1:
202    %2:vgpr_32 = V_CNDMASK_B32_dpp %0:vgpr_32, 0, %0:vgpr_32, 0, %0:vgpr_32, 1, 15, 15, 10, implicit $exec, implicit undef $vcc
203    $exec = S_OR_B64 $exec, 1, implicit-def $scc
204    S_CBRANCH_EXECNZ %bb.1, implicit $exec
205    S_BRANCH %bb.2
206
207  bb.2:
208    S_ENDPGM 0
209...
210---
211name: no_hoist_cndmask_sdwa
212tracksRegLiveness: true
213body:             |
214  ; GCN-LABEL: name: no_hoist_cndmask_sdwa
215  ; GCN: bb.0:
216  ; GCN-NEXT:   successors: %bb.1(0x80000000)
217  ; GCN-NEXT: {{  $}}
218  ; GCN-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
219  ; GCN-NEXT:   [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
220  ; GCN-NEXT:   S_BRANCH %bb.1
221  ; GCN-NEXT: {{  $}}
222  ; GCN-NEXT: bb.1:
223  ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
224  ; GCN-NEXT: {{  $}}
225  ; GCN-NEXT:   [[V_CNDMASK_B32_sdwa:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_sdwa 0, [[DEF]], 0, [[DEF]], 0, 0, 0, 0, 0, implicit $exec, implicit undef $vcc
226  ; GCN-NEXT:   $exec = S_OR_B64 $exec, 1, implicit-def $scc
227  ; GCN-NEXT:   S_CBRANCH_EXECNZ %bb.1, implicit $exec
228  ; GCN-NEXT:   S_BRANCH %bb.2
229  ; GCN-NEXT: {{  $}}
230  ; GCN-NEXT: bb.2:
231  ; GCN-NEXT:   S_ENDPGM 0
232  bb.0:
233    %0:vgpr_32 = IMPLICIT_DEF
234    %1:sreg_64_xexec = IMPLICIT_DEF
235    S_BRANCH %bb.1
236
237  bb.1:
238    %2:vgpr_32 = V_CNDMASK_B32_sdwa 0, %0:vgpr_32, 0, %0:vgpr_32, 0, 0, 0, 0, 0, implicit $exec, implicit undef $vcc
239    $exec = S_OR_B64 $exec, 1, implicit-def $scc
240    S_CBRANCH_EXECNZ %bb.1, implicit $exec
241    S_BRANCH %bb.2
242
243  bb.2:
244    S_ENDPGM 0
245...
246