1; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,ALIGNED,SPLIT %s 2; RUN: llc -march=amdgcn -mcpu=gfx1011 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,ALIGNED,SPLIT %s 3; RUN: llc -march=amdgcn -mcpu=gfx1012 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,ALIGNED,SPLIT %s 4; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -mattr=+cumode < %s | FileCheck -check-prefixes=GCN,ALIGNED,VECT %s 5; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -mattr=+cumode,+unaligned-access-mode < %s | FileCheck -check-prefixes=GCN,UNALIGNED,VECT %s 6 7; GCN-LABEL: test_local_misaligned_v2: 8; GCN-DAG: ds_read2_b32 9; GCN-DAG: ds_write2_b32 10define amdgpu_kernel void @test_local_misaligned_v2(i32 addrspace(3)* %arg) { 11bb: 12 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 13 %gep = getelementptr inbounds i32, i32 addrspace(3)* %arg, i32 %lid 14 %ptr = bitcast i32 addrspace(3)* %gep to <2 x i32> addrspace(3)* 15 %load = load <2 x i32>, <2 x i32> addrspace(3)* %ptr, align 4 16 %v1 = extractelement <2 x i32> %load, i32 0 17 %v2 = extractelement <2 x i32> %load, i32 1 18 %v3 = insertelement <2 x i32> undef, i32 %v2, i32 0 19 %v4 = insertelement <2 x i32> %v3, i32 %v1, i32 1 20 store <2 x i32> %v4, <2 x i32> addrspace(3)* %ptr, align 4 21 ret void 22} 23 24; GCN-LABEL: test_local_misaligned_v4: 25; ALIGNED-DAG: ds_read2_b32 26; ALIGNED-DAG: ds_read2_b32 27; ALIGNED-DAG: ds_write2_b32 28; ALIGNED-DAG: ds_write2_b32 29; UNALIGNED-DAG: ds_read2_b64 30; UNALIGNED-DAG: ds_write2_b64 31define amdgpu_kernel void @test_local_misaligned_v4(i32 addrspace(3)* %arg) { 32bb: 33 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 34 %gep = getelementptr inbounds i32, i32 addrspace(3)* %arg, i32 %lid 35 %ptr = bitcast i32 addrspace(3)* %gep to <4 x i32> addrspace(3)* 36 %load = load <4 x i32>, <4 x i32> addrspace(3)* %ptr, align 4 37 %v1 = extractelement <4 x i32> %load, i32 0 38 %v2 = extractelement <4 x i32> %load, i32 1 39 %v3 = extractelement <4 x i32> %load, i32 2 40 %v4 = extractelement <4 x i32> %load, i32 3 41 %v5 = insertelement <4 x i32> undef, i32 %v4, i32 0 42 %v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1 43 %v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2 44 %v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3 45 store <4 x i32> %v8, <4 x i32> addrspace(3)* %ptr, align 4 46 ret void 47} 48 49; GCN-LABEL: test_local_misaligned_v3: 50; GCN-DAG: ds_read2_b32 51; GCN-DAG: ds_read_b32 52; GCN-DAG: ds_write2_b32 53; GCN-DAG: ds_write_b32 54define amdgpu_kernel void @test_local_misaligned_v3(i32 addrspace(3)* %arg) { 55bb: 56 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 57 %gep = getelementptr inbounds i32, i32 addrspace(3)* %arg, i32 %lid 58 %ptr = bitcast i32 addrspace(3)* %gep to <3 x i32> addrspace(3)* 59 %load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr, align 4 60 %v1 = extractelement <3 x i32> %load, i32 0 61 %v2 = extractelement <3 x i32> %load, i32 1 62 %v3 = extractelement <3 x i32> %load, i32 2 63 %v5 = insertelement <3 x i32> undef, i32 %v3, i32 0 64 %v6 = insertelement <3 x i32> %v5, i32 %v1, i32 1 65 %v7 = insertelement <3 x i32> %v6, i32 %v2, i32 2 66 store <3 x i32> %v7, <3 x i32> addrspace(3)* %ptr, align 4 67 ret void 68} 69 70; GCN-LABEL: test_flat_misaligned_v2: 71; VECT-DAG: flat_load_dwordx2 v 72; VECT-DAG: flat_store_dwordx2 v 73; SPLIT-DAG: flat_load_dword v 74; SPLIT-DAG: flat_load_dword v 75; SPLIT-DAG: flat_store_dword v 76; SPLIT-DAG: flat_store_dword v 77define amdgpu_kernel void @test_flat_misaligned_v2(i32* %arg) { 78bb: 79 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 80 %gep = getelementptr inbounds i32, i32* %arg, i32 %lid 81 %ptr = bitcast i32* %gep to <2 x i32>* 82 %load = load <2 x i32>, <2 x i32>* %ptr, align 4 83 %v1 = extractelement <2 x i32> %load, i32 0 84 %v2 = extractelement <2 x i32> %load, i32 1 85 %v3 = insertelement <2 x i32> undef, i32 %v2, i32 0 86 %v4 = insertelement <2 x i32> %v3, i32 %v1, i32 1 87 store <2 x i32> %v4, <2 x i32>* %ptr, align 4 88 ret void 89} 90 91; GCN-LABEL: test_flat_misaligned_v4: 92; VECT-DAG: flat_load_dwordx4 v 93; VECT-DAG: flat_store_dwordx4 v 94; SPLIT-DAG: flat_load_dword v 95; SPLIT-DAG: flat_load_dword v 96; SPLIT-DAG: flat_load_dword v 97; SPLIT-DAG: flat_load_dword v 98; SPLIT-DAG: flat_store_dword v 99; SPLIT-DAG: flat_store_dword v 100; SPLIT-DAG: flat_store_dword v 101; SPLIT-DAG: flat_store_dword v 102define amdgpu_kernel void @test_flat_misaligned_v4(i32* %arg) { 103bb: 104 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 105 %gep = getelementptr inbounds i32, i32* %arg, i32 %lid 106 %ptr = bitcast i32* %gep to <4 x i32>* 107 %load = load <4 x i32>, <4 x i32>* %ptr, align 4 108 %v1 = extractelement <4 x i32> %load, i32 0 109 %v2 = extractelement <4 x i32> %load, i32 1 110 %v3 = extractelement <4 x i32> %load, i32 2 111 %v4 = extractelement <4 x i32> %load, i32 3 112 %v5 = insertelement <4 x i32> undef, i32 %v4, i32 0 113 %v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1 114 %v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2 115 %v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3 116 store <4 x i32> %v8, <4 x i32>* %ptr, align 4 117 ret void 118} 119 120; TODO: Reinstate the test below once v3i32/v3f32 is reinstated. 121 122; GCN-LABEL: test_flat_misaligned_v3: 123; xVECT-DAG: flat_load_dwordx3 v 124; xVECT-DAG: flat_store_dwordx3 v 125; xSPLIT-DAG: flat_load_dword v 126; xSPLIT-DAG: flat_load_dword v 127; xSPLIT-DAG: flat_load_dword v 128; xSPLIT-DAG: flat_store_dword v 129; xSPLIT-DAG: flat_store_dword v 130; xSPLIT-DAG: flat_store_dword v 131define amdgpu_kernel void @test_flat_misaligned_v3(i32* %arg) { 132bb: 133 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 134 %gep = getelementptr inbounds i32, i32* %arg, i32 %lid 135 %ptr = bitcast i32* %gep to <3 x i32>* 136 %load = load <3 x i32>, <3 x i32>* %ptr, align 4 137 %v1 = extractelement <3 x i32> %load, i32 0 138 %v2 = extractelement <3 x i32> %load, i32 1 139 %v3 = extractelement <3 x i32> %load, i32 2 140 %v5 = insertelement <3 x i32> undef, i32 %v3, i32 0 141 %v6 = insertelement <3 x i32> %v5, i32 %v1, i32 1 142 %v7 = insertelement <3 x i32> %v6, i32 %v2, i32 2 143 store <3 x i32> %v7, <3 x i32>* %ptr, align 4 144 ret void 145} 146 147; GCN-LABEL: test_local_aligned_v2: 148; GCN-DAG: ds_read_b64 149; GCN-DAG: ds_write_b64 150define amdgpu_kernel void @test_local_aligned_v2(i32 addrspace(3)* %arg) { 151bb: 152 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 153 %gep = getelementptr inbounds i32, i32 addrspace(3)* %arg, i32 %lid 154 %ptr = bitcast i32 addrspace(3)* %gep to <2 x i32> addrspace(3)* 155 %load = load <2 x i32>, <2 x i32> addrspace(3)* %ptr, align 8 156 %v1 = extractelement <2 x i32> %load, i32 0 157 %v2 = extractelement <2 x i32> %load, i32 1 158 %v3 = insertelement <2 x i32> undef, i32 %v2, i32 0 159 %v4 = insertelement <2 x i32> %v3, i32 %v1, i32 1 160 store <2 x i32> %v4, <2 x i32> addrspace(3)* %ptr, align 8 161 ret void 162} 163 164; GCN-LABEL: test_local_aligned_v3: 165; GCN-DAG: ds_read_b96 166; GCN-DAG: ds_write_b96 167define amdgpu_kernel void @test_local_aligned_v3(i32 addrspace(3)* %arg) { 168bb: 169 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 170 %gep = getelementptr inbounds i32, i32 addrspace(3)* %arg, i32 %lid 171 %ptr = bitcast i32 addrspace(3)* %gep to <3 x i32> addrspace(3)* 172 %load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr, align 16 173 %v1 = extractelement <3 x i32> %load, i32 0 174 %v2 = extractelement <3 x i32> %load, i32 1 175 %v3 = extractelement <3 x i32> %load, i32 2 176 %v5 = insertelement <3 x i32> undef, i32 %v3, i32 0 177 %v6 = insertelement <3 x i32> %v5, i32 %v1, i32 1 178 %v7 = insertelement <3 x i32> %v6, i32 %v2, i32 2 179 store <3 x i32> %v7, <3 x i32> addrspace(3)* %ptr, align 16 180 ret void 181} 182 183; GCN-LABEL: test_flat_aligned_v2: 184; GCN-DAG: flat_load_dwordx2 v 185; GCN-DAG: flat_store_dwordx2 v 186define amdgpu_kernel void @test_flat_aligned_v2(i32* %arg) { 187bb: 188 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 189 %gep = getelementptr inbounds i32, i32* %arg, i32 %lid 190 %ptr = bitcast i32* %gep to <2 x i32>* 191 %load = load <2 x i32>, <2 x i32>* %ptr, align 8 192 %v1 = extractelement <2 x i32> %load, i32 0 193 %v2 = extractelement <2 x i32> %load, i32 1 194 %v3 = insertelement <2 x i32> undef, i32 %v2, i32 0 195 %v4 = insertelement <2 x i32> %v3, i32 %v1, i32 1 196 store <2 x i32> %v4, <2 x i32>* %ptr, align 8 197 ret void 198} 199 200; GCN-LABEL: test_flat_aligned_v4: 201; GCN-DAG: flat_load_dwordx4 v 202; GCN-DAG: flat_store_dwordx4 v 203define amdgpu_kernel void @test_flat_aligned_v4(i32* %arg) { 204bb: 205 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 206 %gep = getelementptr inbounds i32, i32* %arg, i32 %lid 207 %ptr = bitcast i32* %gep to <4 x i32>* 208 %load = load <4 x i32>, <4 x i32>* %ptr, align 16 209 %v1 = extractelement <4 x i32> %load, i32 0 210 %v2 = extractelement <4 x i32> %load, i32 1 211 %v3 = extractelement <4 x i32> %load, i32 2 212 %v4 = extractelement <4 x i32> %load, i32 3 213 %v5 = insertelement <4 x i32> undef, i32 %v4, i32 0 214 %v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1 215 %v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2 216 %v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3 217 store <4 x i32> %v8, <4 x i32>* %ptr, align 16 218 ret void 219} 220 221; GCN-LABEL: test_local_v4_aligned8: 222; ALIGNED-DAG: ds_read2_b64 223; ALIGNED-DAG: ds_write2_b64 224; UNALIGNED-DAG: ds_read2_b64 225; UNALIGNED-DAG: ds_write2_b64 226define amdgpu_kernel void @test_local_v4_aligned8(i32 addrspace(3)* %arg) { 227bb: 228 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 229 %gep = getelementptr inbounds i32, i32 addrspace(3)* %arg, i32 %lid 230 %ptr = bitcast i32 addrspace(3)* %gep to <4 x i32> addrspace(3)* 231 %load = load <4 x i32>, <4 x i32> addrspace(3)* %ptr, align 8 232 %v1 = extractelement <4 x i32> %load, i32 0 233 %v2 = extractelement <4 x i32> %load, i32 1 234 %v3 = extractelement <4 x i32> %load, i32 2 235 %v4 = extractelement <4 x i32> %load, i32 3 236 %v5 = insertelement <4 x i32> undef, i32 %v4, i32 0 237 %v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1 238 %v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2 239 %v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3 240 store <4 x i32> %v8, <4 x i32> addrspace(3)* %ptr, align 8 241 ret void 242} 243 244; GCN-LABEL: test_flat_v4_aligned8: 245; VECT-DAG: flat_load_dwordx4 v 246; VECT-DAG: flat_store_dwordx4 v 247; SPLIT-DAG: flat_load_dwordx2 v 248; SPLIT-DAG: flat_load_dwordx2 v 249; SPLIT-DAG: flat_store_dwordx2 v 250; SPLIT-DAG: flat_store_dwordx2 v 251define amdgpu_kernel void @test_flat_v4_aligned8(i32* %arg) { 252bb: 253 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 254 %gep = getelementptr inbounds i32, i32* %arg, i32 %lid 255 %ptr = bitcast i32* %gep to <4 x i32>* 256 %load = load <4 x i32>, <4 x i32>* %ptr, align 8 257 %v1 = extractelement <4 x i32> %load, i32 0 258 %v2 = extractelement <4 x i32> %load, i32 1 259 %v3 = extractelement <4 x i32> %load, i32 2 260 %v4 = extractelement <4 x i32> %load, i32 3 261 %v5 = insertelement <4 x i32> undef, i32 %v4, i32 0 262 %v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1 263 %v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2 264 %v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3 265 store <4 x i32> %v8, <4 x i32>* %ptr, align 8 266 ret void 267} 268 269declare i32 @llvm.amdgcn.workitem.id.x() 270