1; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SPLIT %s 2; RUN: llc -march=amdgcn -mcpu=gfx1011 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VECT %s 3; RUN: llc -march=amdgcn -mcpu=gfx1012 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SPLIT %s 4; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -mattr=+cumode < %s | FileCheck -check-prefixes=GCN,VECT %s 5 6; GCN-LABEL: test_local_misaligned_v2: 7; GCN-DAG: ds_read2_b32 8; GCN-DAG: ds_write2_b32 9define amdgpu_kernel void @test_local_misaligned_v2(i32 addrspace(3)* %arg) { 10bb: 11 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 12 %gep = getelementptr inbounds i32, i32 addrspace(3)* %arg, i32 %lid 13 %ptr = bitcast i32 addrspace(3)* %gep to <2 x i32> addrspace(3)* 14 %load = load <2 x i32>, <2 x i32> addrspace(3)* %ptr, align 4 15 %v1 = extractelement <2 x i32> %load, i32 0 16 %v2 = extractelement <2 x i32> %load, i32 1 17 %v3 = insertelement <2 x i32> undef, i32 %v2, i32 0 18 %v4 = insertelement <2 x i32> %v3, i32 %v1, i32 1 19 store <2 x i32> %v4, <2 x i32> addrspace(3)* %ptr, align 4 20 ret void 21} 22 23; GCN-LABEL: test_local_misaligned_v4: 24; GCN-DAG: ds_read_b128 25; GCN-DAG: ds_write_b128 26define amdgpu_kernel void @test_local_misaligned_v4(i32 addrspace(3)* %arg) { 27bb: 28 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 29 %gep = getelementptr inbounds i32, i32 addrspace(3)* %arg, i32 %lid 30 %ptr = bitcast i32 addrspace(3)* %gep to <4 x i32> addrspace(3)* 31 %load = load <4 x i32>, <4 x i32> addrspace(3)* %ptr, align 4 32 %v1 = extractelement <4 x i32> %load, i32 0 33 %v2 = extractelement <4 x i32> %load, i32 1 34 %v3 = extractelement <4 x i32> %load, i32 2 35 %v4 = extractelement <4 x i32> %load, i32 3 36 %v5 = insertelement <4 x i32> undef, i32 %v4, i32 0 37 %v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1 38 %v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2 39 %v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3 40 store <4 x i32> %v8, <4 x i32> addrspace(3)* %ptr, align 4 41 ret void 42} 43 44; GCN-LABEL: test_local_misaligned_v3: 45; GCN-DAG: ds_read_b96 46; GCN-DAG: ds_write_b96 47define amdgpu_kernel void @test_local_misaligned_v3(i32 addrspace(3)* %arg) { 48bb: 49 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 50 %gep = getelementptr inbounds i32, i32 addrspace(3)* %arg, i32 %lid 51 %ptr = bitcast i32 addrspace(3)* %gep to <3 x i32> addrspace(3)* 52 %load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr, align 4 53 %v1 = extractelement <3 x i32> %load, i32 0 54 %v2 = extractelement <3 x i32> %load, i32 1 55 %v3 = extractelement <3 x i32> %load, i32 2 56 %v5 = insertelement <3 x i32> undef, i32 %v3, i32 0 57 %v6 = insertelement <3 x i32> %v5, i32 %v1, i32 1 58 %v7 = insertelement <3 x i32> %v6, i32 %v2, i32 2 59 store <3 x i32> %v7, <3 x i32> addrspace(3)* %ptr, align 4 60 ret void 61} 62 63; GCN-LABEL: test_flat_misaligned_v2: 64; VECT-DAG: flat_load_dwordx2 v 65; VECT-DAG: flat_store_dwordx2 v 66; SPLIT-DAG: flat_load_dword v 67; SPLIT-DAG: flat_load_dword v 68; SPLIT-DAG: flat_store_dword v 69; SPLIT-DAG: flat_store_dword v 70define amdgpu_kernel void @test_flat_misaligned_v2(i32* %arg) { 71bb: 72 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 73 %gep = getelementptr inbounds i32, i32* %arg, i32 %lid 74 %ptr = bitcast i32* %gep to <2 x i32>* 75 %load = load <2 x i32>, <2 x i32>* %ptr, align 4 76 %v1 = extractelement <2 x i32> %load, i32 0 77 %v2 = extractelement <2 x i32> %load, i32 1 78 %v3 = insertelement <2 x i32> undef, i32 %v2, i32 0 79 %v4 = insertelement <2 x i32> %v3, i32 %v1, i32 1 80 store <2 x i32> %v4, <2 x i32>* %ptr, align 4 81 ret void 82} 83 84; GCN-LABEL: test_flat_misaligned_v4: 85; VECT-DAG: flat_load_dwordx4 v 86; VECT-DAG: flat_store_dwordx4 v 87; SPLIT-DAG: flat_load_dword v 88; SPLIT-DAG: flat_load_dword v 89; SPLIT-DAG: flat_load_dword v 90; SPLIT-DAG: flat_load_dword v 91; SPLIT-DAG: flat_store_dword v 92; SPLIT-DAG: flat_store_dword v 93; SPLIT-DAG: flat_store_dword v 94; SPLIT-DAG: flat_store_dword v 95define amdgpu_kernel void @test_flat_misaligned_v4(i32* %arg) { 96bb: 97 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 98 %gep = getelementptr inbounds i32, i32* %arg, i32 %lid 99 %ptr = bitcast i32* %gep to <4 x i32>* 100 %load = load <4 x i32>, <4 x i32>* %ptr, align 4 101 %v1 = extractelement <4 x i32> %load, i32 0 102 %v2 = extractelement <4 x i32> %load, i32 1 103 %v3 = extractelement <4 x i32> %load, i32 2 104 %v4 = extractelement <4 x i32> %load, i32 3 105 %v5 = insertelement <4 x i32> undef, i32 %v4, i32 0 106 %v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1 107 %v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2 108 %v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3 109 store <4 x i32> %v8, <4 x i32>* %ptr, align 4 110 ret void 111} 112 113; TODO: Reinstate the test below once v3i32/v3f32 is reinstated. 114 115; GCN-LABEL: test_flat_misaligned_v3: 116; xVECT-DAG: flat_load_dwordx3 v 117; xVECT-DAG: flat_store_dwordx3 v 118; xSPLIT-DAG: flat_load_dword v 119; xSPLIT-DAG: flat_load_dword v 120; xSPLIT-DAG: flat_load_dword v 121; xSPLIT-DAG: flat_store_dword v 122; xSPLIT-DAG: flat_store_dword v 123; xSPLIT-DAG: flat_store_dword v 124define amdgpu_kernel void @test_flat_misaligned_v3(i32* %arg) { 125bb: 126 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 127 %gep = getelementptr inbounds i32, i32* %arg, i32 %lid 128 %ptr = bitcast i32* %gep to <3 x i32>* 129 %load = load <3 x i32>, <3 x i32>* %ptr, align 4 130 %v1 = extractelement <3 x i32> %load, i32 0 131 %v2 = extractelement <3 x i32> %load, i32 1 132 %v3 = extractelement <3 x i32> %load, i32 2 133 %v5 = insertelement <3 x i32> undef, i32 %v3, i32 0 134 %v6 = insertelement <3 x i32> %v5, i32 %v1, i32 1 135 %v7 = insertelement <3 x i32> %v6, i32 %v2, i32 2 136 store <3 x i32> %v7, <3 x i32>* %ptr, align 4 137 ret void 138} 139 140; GCN-LABEL: test_local_aligned_v2: 141; GCN-DAG: ds_read_b64 142; GCN-DAG: ds_write_b64 143define amdgpu_kernel void @test_local_aligned_v2(i32 addrspace(3)* %arg) { 144bb: 145 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 146 %gep = getelementptr inbounds i32, i32 addrspace(3)* %arg, i32 %lid 147 %ptr = bitcast i32 addrspace(3)* %gep to <2 x i32> addrspace(3)* 148 %load = load <2 x i32>, <2 x i32> addrspace(3)* %ptr, align 8 149 %v1 = extractelement <2 x i32> %load, i32 0 150 %v2 = extractelement <2 x i32> %load, i32 1 151 %v3 = insertelement <2 x i32> undef, i32 %v2, i32 0 152 %v4 = insertelement <2 x i32> %v3, i32 %v1, i32 1 153 store <2 x i32> %v4, <2 x i32> addrspace(3)* %ptr, align 8 154 ret void 155} 156 157; GCN-LABEL: test_local_aligned_v3: 158; GCN-DAG: ds_read_b96 159; GCN-DAG: ds_write_b96 160define amdgpu_kernel void @test_local_aligned_v3(i32 addrspace(3)* %arg) { 161bb: 162 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 163 %gep = getelementptr inbounds i32, i32 addrspace(3)* %arg, i32 %lid 164 %ptr = bitcast i32 addrspace(3)* %gep to <3 x i32> addrspace(3)* 165 %load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr, align 16 166 %v1 = extractelement <3 x i32> %load, i32 0 167 %v2 = extractelement <3 x i32> %load, i32 1 168 %v3 = extractelement <3 x i32> %load, i32 2 169 %v5 = insertelement <3 x i32> undef, i32 %v3, i32 0 170 %v6 = insertelement <3 x i32> %v5, i32 %v1, i32 1 171 %v7 = insertelement <3 x i32> %v6, i32 %v2, i32 2 172 store <3 x i32> %v7, <3 x i32> addrspace(3)* %ptr, align 16 173 ret void 174} 175 176; GCN-LABEL: test_flat_aligned_v2: 177; GCN-DAG: flat_load_dwordx2 v 178; GCN-DAG: flat_store_dwordx2 v 179define amdgpu_kernel void @test_flat_aligned_v2(i32* %arg) { 180bb: 181 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 182 %gep = getelementptr inbounds i32, i32* %arg, i32 %lid 183 %ptr = bitcast i32* %gep to <2 x i32>* 184 %load = load <2 x i32>, <2 x i32>* %ptr, align 8 185 %v1 = extractelement <2 x i32> %load, i32 0 186 %v2 = extractelement <2 x i32> %load, i32 1 187 %v3 = insertelement <2 x i32> undef, i32 %v2, i32 0 188 %v4 = insertelement <2 x i32> %v3, i32 %v1, i32 1 189 store <2 x i32> %v4, <2 x i32>* %ptr, align 8 190 ret void 191} 192 193; GCN-LABEL: test_flat_aligned_v4: 194; GCN-DAG: flat_load_dwordx4 v 195; GCN-DAG: flat_store_dwordx4 v 196define amdgpu_kernel void @test_flat_aligned_v4(i32* %arg) { 197bb: 198 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 199 %gep = getelementptr inbounds i32, i32* %arg, i32 %lid 200 %ptr = bitcast i32* %gep to <4 x i32>* 201 %load = load <4 x i32>, <4 x i32>* %ptr, align 16 202 %v1 = extractelement <4 x i32> %load, i32 0 203 %v2 = extractelement <4 x i32> %load, i32 1 204 %v3 = extractelement <4 x i32> %load, i32 2 205 %v4 = extractelement <4 x i32> %load, i32 3 206 %v5 = insertelement <4 x i32> undef, i32 %v4, i32 0 207 %v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1 208 %v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2 209 %v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3 210 store <4 x i32> %v8, <4 x i32>* %ptr, align 16 211 ret void 212} 213 214; GCN-LABEL: test_local_v4_aligned8: 215; GCN-DAG: ds_read_b128 216; GCN-DAG: ds_write_b128 217define amdgpu_kernel void @test_local_v4_aligned8(i32 addrspace(3)* %arg) { 218bb: 219 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 220 %gep = getelementptr inbounds i32, i32 addrspace(3)* %arg, i32 %lid 221 %ptr = bitcast i32 addrspace(3)* %gep to <4 x i32> addrspace(3)* 222 %load = load <4 x i32>, <4 x i32> addrspace(3)* %ptr, align 8 223 %v1 = extractelement <4 x i32> %load, i32 0 224 %v2 = extractelement <4 x i32> %load, i32 1 225 %v3 = extractelement <4 x i32> %load, i32 2 226 %v4 = extractelement <4 x i32> %load, i32 3 227 %v5 = insertelement <4 x i32> undef, i32 %v4, i32 0 228 %v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1 229 %v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2 230 %v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3 231 store <4 x i32> %v8, <4 x i32> addrspace(3)* %ptr, align 8 232 ret void 233} 234 235; GCN-LABEL: test_flat_v4_aligned8: 236; VECT-DAG: flat_load_dwordx4 v 237; VECT-DAG: flat_store_dwordx4 v 238; SPLIT-DAG: flat_load_dwordx2 v 239; SPLIT-DAG: flat_load_dwordx2 v 240; SPLIT-DAG: flat_store_dwordx2 v 241; SPLIT-DAG: flat_store_dwordx2 v 242define amdgpu_kernel void @test_flat_v4_aligned8(i32* %arg) { 243bb: 244 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 245 %gep = getelementptr inbounds i32, i32* %arg, i32 %lid 246 %ptr = bitcast i32* %gep to <4 x i32>* 247 %load = load <4 x i32>, <4 x i32>* %ptr, align 8 248 %v1 = extractelement <4 x i32> %load, i32 0 249 %v2 = extractelement <4 x i32> %load, i32 1 250 %v3 = extractelement <4 x i32> %load, i32 2 251 %v4 = extractelement <4 x i32> %load, i32 3 252 %v5 = insertelement <4 x i32> undef, i32 %v4, i32 0 253 %v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1 254 %v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2 255 %v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3 256 store <4 x i32> %v8, <4 x i32>* %ptr, align 8 257 ret void 258} 259 260declare i32 @llvm.amdgcn.workitem.id.x() 261