1; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SPLIT %s 2; RUN: llc -march=amdgcn -mcpu=gfx1011 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SPLIT %s 3; RUN: llc -march=amdgcn -mcpu=gfx1012 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SPLIT %s 4; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -mattr=+cumode < %s | FileCheck -check-prefixes=GCN,VECT %s 5 6; GCN-LABEL: test_local_misaligned_v2: 7; GCN-DAG: ds_read2_b32 8; GCN-DAG: ds_write2_b32 9define amdgpu_kernel void @test_local_misaligned_v2(i32 addrspace(3)* %arg) { 10bb: 11 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 12 %gep = getelementptr inbounds i32, i32 addrspace(3)* %arg, i32 %lid 13 %ptr = bitcast i32 addrspace(3)* %gep to <2 x i32> addrspace(3)* 14 %load = load <2 x i32>, <2 x i32> addrspace(3)* %ptr, align 4 15 %v1 = extractelement <2 x i32> %load, i32 0 16 %v2 = extractelement <2 x i32> %load, i32 1 17 %v3 = insertelement <2 x i32> undef, i32 %v2, i32 0 18 %v4 = insertelement <2 x i32> %v3, i32 %v1, i32 1 19 store <2 x i32> %v4, <2 x i32> addrspace(3)* %ptr, align 4 20 ret void 21} 22 23; GCN-LABEL: test_local_misaligned_v4: 24; VECT-DAG: ds_read_b128 25; VECT-DAG: ds_write_b128 26; SPLIT-DAG: ds_read2_b32 27; SPLIT-DAG: ds_read2_b32 28; SPLIT-DAG: ds_write2_b32 29; SPLIT-DAG: ds_write2_b32 30define amdgpu_kernel void @test_local_misaligned_v4(i32 addrspace(3)* %arg) { 31bb: 32 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 33 %gep = getelementptr inbounds i32, i32 addrspace(3)* %arg, i32 %lid 34 %ptr = bitcast i32 addrspace(3)* %gep to <4 x i32> addrspace(3)* 35 %load = load <4 x i32>, <4 x i32> addrspace(3)* %ptr, align 4 36 %v1 = extractelement <4 x i32> %load, i32 0 37 %v2 = extractelement <4 x i32> %load, i32 1 38 %v3 = extractelement <4 x i32> %load, i32 2 39 %v4 = extractelement <4 x i32> %load, i32 3 40 %v5 = insertelement <4 x i32> undef, i32 %v4, i32 0 41 %v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1 42 %v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2 43 %v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3 44 store <4 x i32> %v8, <4 x i32> addrspace(3)* %ptr, align 4 45 ret void 46} 47 48; GCN-LABEL: test_local_misaligned_v3: 49; VECT-DAG: ds_read_b96 50; VECT-DAG: ds_write_b96 51; SPLIT-DAG: ds_read2_b32 52; SPLIT-DAG: ds_read_b32 53; SPLIT-DAG: ds_write2_b32 54; SPLIT-DAG: ds_write_b32 55define amdgpu_kernel void @test_local_misaligned_v3(i32 addrspace(3)* %arg) { 56bb: 57 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 58 %gep = getelementptr inbounds i32, i32 addrspace(3)* %arg, i32 %lid 59 %ptr = bitcast i32 addrspace(3)* %gep to <3 x i32> addrspace(3)* 60 %load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr, align 4 61 %v1 = extractelement <3 x i32> %load, i32 0 62 %v2 = extractelement <3 x i32> %load, i32 1 63 %v3 = extractelement <3 x i32> %load, i32 2 64 %v5 = insertelement <3 x i32> undef, i32 %v3, i32 0 65 %v6 = insertelement <3 x i32> %v5, i32 %v1, i32 1 66 %v7 = insertelement <3 x i32> %v6, i32 %v2, i32 2 67 store <3 x i32> %v7, <3 x i32> addrspace(3)* %ptr, align 4 68 ret void 69} 70 71; GCN-LABEL: test_flat_misaligned_v2: 72; VECT-DAG: flat_load_dwordx2 v 73; VECT-DAG: flat_store_dwordx2 v 74; SPLIT-DAG: flat_load_dword v 75; SPLIT-DAG: flat_load_dword v 76; SPLIT-DAG: flat_store_dword v 77; SPLIT-DAG: flat_store_dword v 78define amdgpu_kernel void @test_flat_misaligned_v2(i32* %arg) { 79bb: 80 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 81 %gep = getelementptr inbounds i32, i32* %arg, i32 %lid 82 %ptr = bitcast i32* %gep to <2 x i32>* 83 %load = load <2 x i32>, <2 x i32>* %ptr, align 4 84 %v1 = extractelement <2 x i32> %load, i32 0 85 %v2 = extractelement <2 x i32> %load, i32 1 86 %v3 = insertelement <2 x i32> undef, i32 %v2, i32 0 87 %v4 = insertelement <2 x i32> %v3, i32 %v1, i32 1 88 store <2 x i32> %v4, <2 x i32>* %ptr, align 4 89 ret void 90} 91 92; GCN-LABEL: test_flat_misaligned_v4: 93; VECT-DAG: flat_load_dwordx4 v 94; VECT-DAG: flat_store_dwordx4 v 95; SPLIT-DAG: flat_load_dword v 96; SPLIT-DAG: flat_load_dword v 97; SPLIT-DAG: flat_load_dword v 98; SPLIT-DAG: flat_load_dword v 99; SPLIT-DAG: flat_store_dword v 100; SPLIT-DAG: flat_store_dword v 101; SPLIT-DAG: flat_store_dword v 102; SPLIT-DAG: flat_store_dword v 103define amdgpu_kernel void @test_flat_misaligned_v4(i32* %arg) { 104bb: 105 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 106 %gep = getelementptr inbounds i32, i32* %arg, i32 %lid 107 %ptr = bitcast i32* %gep to <4 x i32>* 108 %load = load <4 x i32>, <4 x i32>* %ptr, align 4 109 %v1 = extractelement <4 x i32> %load, i32 0 110 %v2 = extractelement <4 x i32> %load, i32 1 111 %v3 = extractelement <4 x i32> %load, i32 2 112 %v4 = extractelement <4 x i32> %load, i32 3 113 %v5 = insertelement <4 x i32> undef, i32 %v4, i32 0 114 %v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1 115 %v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2 116 %v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3 117 store <4 x i32> %v8, <4 x i32>* %ptr, align 4 118 ret void 119} 120 121; TODO: Reinstate the test below once v3i32/v3f32 is reinstated. 122 123; GCN-LABEL: test_flat_misaligned_v3: 124; xVECT-DAG: flat_load_dwordx3 v 125; xVECT-DAG: flat_store_dwordx3 v 126; xSPLIT-DAG: flat_load_dword v 127; xSPLIT-DAG: flat_load_dword v 128; xSPLIT-DAG: flat_load_dword v 129; xSPLIT-DAG: flat_store_dword v 130; xSPLIT-DAG: flat_store_dword v 131; xSPLIT-DAG: flat_store_dword v 132define amdgpu_kernel void @test_flat_misaligned_v3(i32* %arg) { 133bb: 134 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 135 %gep = getelementptr inbounds i32, i32* %arg, i32 %lid 136 %ptr = bitcast i32* %gep to <3 x i32>* 137 %load = load <3 x i32>, <3 x i32>* %ptr, align 4 138 %v1 = extractelement <3 x i32> %load, i32 0 139 %v2 = extractelement <3 x i32> %load, i32 1 140 %v3 = extractelement <3 x i32> %load, i32 2 141 %v5 = insertelement <3 x i32> undef, i32 %v3, i32 0 142 %v6 = insertelement <3 x i32> %v5, i32 %v1, i32 1 143 %v7 = insertelement <3 x i32> %v6, i32 %v2, i32 2 144 store <3 x i32> %v7, <3 x i32>* %ptr, align 4 145 ret void 146} 147 148; GCN-LABEL: test_local_aligned_v2: 149; GCN-DAG: ds_read_b64 150; GCN-DAG: ds_write_b64 151define amdgpu_kernel void @test_local_aligned_v2(i32 addrspace(3)* %arg) { 152bb: 153 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 154 %gep = getelementptr inbounds i32, i32 addrspace(3)* %arg, i32 %lid 155 %ptr = bitcast i32 addrspace(3)* %gep to <2 x i32> addrspace(3)* 156 %load = load <2 x i32>, <2 x i32> addrspace(3)* %ptr, align 8 157 %v1 = extractelement <2 x i32> %load, i32 0 158 %v2 = extractelement <2 x i32> %load, i32 1 159 %v3 = insertelement <2 x i32> undef, i32 %v2, i32 0 160 %v4 = insertelement <2 x i32> %v3, i32 %v1, i32 1 161 store <2 x i32> %v4, <2 x i32> addrspace(3)* %ptr, align 8 162 ret void 163} 164 165; GCN-LABEL: test_local_aligned_v3: 166; GCN-DAG: ds_read_b96 167; GCN-DAG: ds_write_b96 168define amdgpu_kernel void @test_local_aligned_v3(i32 addrspace(3)* %arg) { 169bb: 170 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 171 %gep = getelementptr inbounds i32, i32 addrspace(3)* %arg, i32 %lid 172 %ptr = bitcast i32 addrspace(3)* %gep to <3 x i32> addrspace(3)* 173 %load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr, align 16 174 %v1 = extractelement <3 x i32> %load, i32 0 175 %v2 = extractelement <3 x i32> %load, i32 1 176 %v3 = extractelement <3 x i32> %load, i32 2 177 %v5 = insertelement <3 x i32> undef, i32 %v3, i32 0 178 %v6 = insertelement <3 x i32> %v5, i32 %v1, i32 1 179 %v7 = insertelement <3 x i32> %v6, i32 %v2, i32 2 180 store <3 x i32> %v7, <3 x i32> addrspace(3)* %ptr, align 16 181 ret void 182} 183 184; GCN-LABEL: test_flat_aligned_v2: 185; GCN-DAG: flat_load_dwordx2 v 186; GCN-DAG: flat_store_dwordx2 v 187define amdgpu_kernel void @test_flat_aligned_v2(i32* %arg) { 188bb: 189 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 190 %gep = getelementptr inbounds i32, i32* %arg, i32 %lid 191 %ptr = bitcast i32* %gep to <2 x i32>* 192 %load = load <2 x i32>, <2 x i32>* %ptr, align 8 193 %v1 = extractelement <2 x i32> %load, i32 0 194 %v2 = extractelement <2 x i32> %load, i32 1 195 %v3 = insertelement <2 x i32> undef, i32 %v2, i32 0 196 %v4 = insertelement <2 x i32> %v3, i32 %v1, i32 1 197 store <2 x i32> %v4, <2 x i32>* %ptr, align 8 198 ret void 199} 200 201; GCN-LABEL: test_flat_aligned_v4: 202; GCN-DAG: flat_load_dwordx4 v 203; GCN-DAG: flat_store_dwordx4 v 204define amdgpu_kernel void @test_flat_aligned_v4(i32* %arg) { 205bb: 206 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 207 %gep = getelementptr inbounds i32, i32* %arg, i32 %lid 208 %ptr = bitcast i32* %gep to <4 x i32>* 209 %load = load <4 x i32>, <4 x i32>* %ptr, align 16 210 %v1 = extractelement <4 x i32> %load, i32 0 211 %v2 = extractelement <4 x i32> %load, i32 1 212 %v3 = extractelement <4 x i32> %load, i32 2 213 %v4 = extractelement <4 x i32> %load, i32 3 214 %v5 = insertelement <4 x i32> undef, i32 %v4, i32 0 215 %v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1 216 %v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2 217 %v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3 218 store <4 x i32> %v8, <4 x i32>* %ptr, align 16 219 ret void 220} 221 222; GCN-LABEL: test_local_v4_aligned8: 223; GCN-DAG: ds_read_b128 224; GCN-DAG: ds_write_b128 225define amdgpu_kernel void @test_local_v4_aligned8(i32 addrspace(3)* %arg) { 226bb: 227 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 228 %gep = getelementptr inbounds i32, i32 addrspace(3)* %arg, i32 %lid 229 %ptr = bitcast i32 addrspace(3)* %gep to <4 x i32> addrspace(3)* 230 %load = load <4 x i32>, <4 x i32> addrspace(3)* %ptr, align 8 231 %v1 = extractelement <4 x i32> %load, i32 0 232 %v2 = extractelement <4 x i32> %load, i32 1 233 %v3 = extractelement <4 x i32> %load, i32 2 234 %v4 = extractelement <4 x i32> %load, i32 3 235 %v5 = insertelement <4 x i32> undef, i32 %v4, i32 0 236 %v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1 237 %v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2 238 %v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3 239 store <4 x i32> %v8, <4 x i32> addrspace(3)* %ptr, align 8 240 ret void 241} 242 243; GCN-LABEL: test_flat_v4_aligned8: 244; VECT-DAG: flat_load_dwordx4 v 245; VECT-DAG: flat_store_dwordx4 v 246; SPLIT-DAG: flat_load_dwordx2 v 247; SPLIT-DAG: flat_load_dwordx2 v 248; SPLIT-DAG: flat_store_dwordx2 v 249; SPLIT-DAG: flat_store_dwordx2 v 250define amdgpu_kernel void @test_flat_v4_aligned8(i32* %arg) { 251bb: 252 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 253 %gep = getelementptr inbounds i32, i32* %arg, i32 %lid 254 %ptr = bitcast i32* %gep to <4 x i32>* 255 %load = load <4 x i32>, <4 x i32>* %ptr, align 8 256 %v1 = extractelement <4 x i32> %load, i32 0 257 %v2 = extractelement <4 x i32> %load, i32 1 258 %v3 = extractelement <4 x i32> %load, i32 2 259 %v4 = extractelement <4 x i32> %load, i32 3 260 %v5 = insertelement <4 x i32> undef, i32 %v4, i32 0 261 %v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1 262 %v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2 263 %v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3 264 store <4 x i32> %v8, <4 x i32>* %ptr, align 8 265 ret void 266} 267 268declare i32 @llvm.amdgcn.workitem.id.x() 269