1; RUN: llc -march=amdgcn -mcpu=bonaire -show-mc-encoding < %s | FileCheck --check-prefixes=GCN,CI,ALL %s 2; RUN: llc -march=amdgcn -mcpu=carrizo --show-mc-encoding < %s | FileCheck --check-prefixes=GCN,VI,ALL %s 3; RUN: llc -march=amdgcn -mcpu=gfx900 --show-mc-encoding < %s | FileCheck --check-prefixes=GCN,GFX9,ALL %s 4; RUN: llc -march=amdgcn -mcpu=bonaire -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=4 < %s -mattr=-flat-for-global | FileCheck --check-prefixes=GCNHSA,ALL %s 5; RUN: llc -march=amdgcn -mcpu=carrizo -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=4 -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GCNHSA,ALL %s 6; RUN: llc -march=amdgcn -mcpu=gfx1010 -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=4 -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GCNHSA,GFX10HSA,ALL %s 7 8; FIXME: align on alloca seems to be ignored for private_segment_alignment 9 10; ALL-LABEL: {{^}}large_alloca_compute_shader: 11 12; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0 13; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD0 14; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1 15; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD1 16; GCN-DAG: s_mov_b32 s{{[0-9]+}}, -1 17; CI-DAG: s_mov_b32 s{{[0-9]+}}, 0xe8f000 18; VI-DAG: s_mov_b32 s{{[0-9]+}}, 0xe80000 19; GFX9-DAG: s_mov_b32 s{{[0-9]+}}, 0xe00000 20 21 22; GFX10HSA: s_add_u32 [[FLAT_SCR_LO:s[0-9]+]], s{{[0-9]+}}, s{{[0-9]+}} 23; GFX10HSA-DAG: s_addc_u32 [[FLAT_SCR_HI:s[0-9]+]], s{{[0-9]+}}, 0 24; GFX10HSA-DAG: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), [[FLAT_SCR_LO]] 25; GFX10HSA-DAG: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), [[FLAT_SCR_HI]] 26 27; GCNHSA: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, s[0:3], 0 offen 28; GCNHSA: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, s[0:3], 0 offen 29 30; GCNHSA: .amdhsa_kernel large_alloca_compute_shader 31; GCNHSA: .amdhsa_group_segment_fixed_size 0 32; GCNHSA: .amdhsa_private_segment_fixed_size 32772 33; GCNHSA: .amdhsa_user_sgpr_private_segment_buffer 1 34; GCNHSA: .amdhsa_user_sgpr_dispatch_ptr 0 35; GCNHSA: .amdhsa_user_sgpr_queue_ptr 0 36; GCNHSA: .amdhsa_user_sgpr_kernarg_segment_ptr 1 37; GCNHSA: .amdhsa_user_sgpr_dispatch_id 0 38; GCNHSA: .amdhsa_user_sgpr_flat_scratch_init 1 39; GCNHSA: .amdhsa_user_sgpr_private_segment_size 0 40; GCNHSA: .amdhsa_system_sgpr_private_segment_wavefront_offset 1 41; GCNHSA: .amdhsa_system_sgpr_workgroup_id_x 1 42; GCNHSA: .amdhsa_system_sgpr_workgroup_id_y 0 43; GCNHSA: .amdhsa_system_sgpr_workgroup_id_z 0 44; GCNHSA: .amdhsa_system_sgpr_workgroup_info 0 45; GCNHSA: .amdhsa_system_vgpr_workitem_id 0 46; GCNHSA: .amdhsa_next_free_vgpr 3 47; GCNHSA: .amdhsa_next_free_sgpr 10 48; GCNHSA: .amdhsa_float_round_mode_32 0 49; GCNHSA: .amdhsa_float_round_mode_16_64 0 50; GCNHSA: .amdhsa_float_denorm_mode_32 3 51; GCNHSA: .amdhsa_float_denorm_mode_16_64 3 52; GCNHSA: .amdhsa_dx10_clamp 1 53; GCNHSA: .amdhsa_ieee_mode 1 54; GCNHSA: .amdhsa_exception_fp_ieee_invalid_op 0 55; GCNHSA: .amdhsa_exception_fp_denorm_src 0 56; GCNHSA: .amdhsa_exception_fp_ieee_div_zero 0 57; GCNHSA: .amdhsa_exception_fp_ieee_overflow 0 58; GCNHSA: .amdhsa_exception_fp_ieee_underflow 0 59; GCNHSA: .amdhsa_exception_fp_ieee_inexact 0 60; GCNHSA: .amdhsa_exception_int_div_zero 0 61; GCNHSA: .end_amdhsa_kernel 62 63; Scratch size = alloca size + emergency stack slot, align {{.*}}, addrspace(5) 64; ALL: ; ScratchSize: 32772 65define amdgpu_kernel void @large_alloca_compute_shader(i32 %x, i32 %y) #0 { 66 %large = alloca [8192 x i32], align 4, addrspace(5) 67 %gep = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %large, i32 0, i32 8191 68 store volatile i32 %x, i32 addrspace(5)* %gep 69 %gep1 = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %large, i32 0, i32 %y 70 %val = load volatile i32, i32 addrspace(5)* %gep1 71 store volatile i32 %val, i32 addrspace(1)* undef 72 ret void 73} 74 75attributes #0 = { nounwind } 76