1; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 --amdhsa-code-object-version=2 -amdgpu-ir-lower-kernel-arguments=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=VI,GCN,HSA-VI,FUNC %s 2 3; Repeat of some problematic tests in kernel-args.ll, with the IR 4; argument lowering pass disabled. Struct padding needs to be 5; accounted for, as well as legalization of types changing offsets. 6 7; FUNC-LABEL: {{^}}i1_arg: 8; HSA-VI: kernarg_segment_byte_size = 12 9; HSA-VI: kernarg_segment_alignment = 4 10 11; GCN: s_load_dword s 12; GCN: s_and_b32 13define amdgpu_kernel void @i1_arg(i1 addrspace(1)* %out, i1 %x) nounwind { 14 store i1 %x, i1 addrspace(1)* %out, align 1 15 ret void 16} 17 18; FUNC-LABEL: {{^}}v3i8_arg: 19; HSA-VI: kernarg_segment_byte_size = 12 20; HSA-VI: kernarg_segment_alignment = 4 21; HSA-VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x0 22; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x8 23define amdgpu_kernel void @v3i8_arg(<3 x i8> addrspace(1)* nocapture %out, <3 x i8> %in) nounwind { 24entry: 25 store <3 x i8> %in, <3 x i8> addrspace(1)* %out, align 4 26 ret void 27} 28 29; FUNC-LABEL: {{^}}i65_arg: 30; HSA-VI: kernarg_segment_byte_size = 24 31; HSA-VI: kernarg_segment_alignment = 4 32; HSA-VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x0 33; HSA-VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x8 34define amdgpu_kernel void @i65_arg(i65 addrspace(1)* nocapture %out, i65 %in) nounwind { 35entry: 36 store i65 %in, i65 addrspace(1)* %out, align 4 37 ret void 38} 39 40; FUNC-LABEL: {{^}}empty_struct_arg: 41; HSA-VI: kernarg_segment_byte_size = 0 42define amdgpu_kernel void @empty_struct_arg({} %in) nounwind { 43 ret void 44} 45 46; The correct load offsets for these: 47; load 4 from 0, 48; load 8 from 8 49; load 4 from 24 50; load 8 from 32 51 52; With the SelectionDAG argument lowering, the alignments for the 53; struct members is not properly considered, making these wrong. 54 55; FIXME: Total argument size is computed wrong 56; FUNC-LABEL: {{^}}struct_argument_alignment: 57; HSA-VI: kernarg_segment_byte_size = 40 58; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x0 59; HSA-VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x8 60; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x18 61; HSA-VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x20 62define amdgpu_kernel void @struct_argument_alignment({i32, i64} %arg0, i8, {i32, i64} %arg1) { 63 %val0 = extractvalue {i32, i64} %arg0, 0 64 %val1 = extractvalue {i32, i64} %arg0, 1 65 %val2 = extractvalue {i32, i64} %arg1, 0 66 %val3 = extractvalue {i32, i64} %arg1, 1 67 store volatile i32 %val0, i32 addrspace(1)* null 68 store volatile i64 %val1, i64 addrspace(1)* null 69 store volatile i32 %val2, i32 addrspace(1)* null 70 store volatile i64 %val3, i64 addrspace(1)* null 71 ret void 72} 73 74; No padding between i8 and next struct, but round up at end to 4 byte 75; multiple. 76; FUNC-LABEL: {{^}}packed_struct_argument_alignment: 77; HSA-VI: kernarg_segment_byte_size = 28 78; HSA-VI: global_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, off offset:17 79; HSA-VI: global_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, off offset:13 80; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x0 81; HSA-VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x4 82define amdgpu_kernel void @packed_struct_argument_alignment(<{i32, i64}> %arg0, i8, <{i32, i64}> %arg1) { 83 %val0 = extractvalue <{i32, i64}> %arg0, 0 84 %val1 = extractvalue <{i32, i64}> %arg0, 1 85 %val2 = extractvalue <{i32, i64}> %arg1, 0 86 %val3 = extractvalue <{i32, i64}> %arg1, 1 87 store volatile i32 %val0, i32 addrspace(1)* null 88 store volatile i64 %val1, i64 addrspace(1)* null 89 store volatile i32 %val2, i32 addrspace(1)* null 90 store volatile i64 %val3, i64 addrspace(1)* null 91 ret void 92} 93 94; GCN-LABEL: {{^}}struct_argument_alignment_after: 95; HSA-VI: kernarg_segment_byte_size = 64 96; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x0 97; HSA-VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x8 98; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x18 99; HSA-VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x20 100; HSA-VI: s_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x30 101define amdgpu_kernel void @struct_argument_alignment_after({i32, i64} %arg0, i8, {i32, i64} %arg2, i8, <4 x i32> %arg4) { 102 %val0 = extractvalue {i32, i64} %arg0, 0 103 %val1 = extractvalue {i32, i64} %arg0, 1 104 %val2 = extractvalue {i32, i64} %arg2, 0 105 %val3 = extractvalue {i32, i64} %arg2, 1 106 store volatile i32 %val0, i32 addrspace(1)* null 107 store volatile i64 %val1, i64 addrspace(1)* null 108 store volatile i32 %val2, i32 addrspace(1)* null 109 store volatile i64 %val3, i64 addrspace(1)* null 110 store volatile <4 x i32> %arg4, <4 x i32> addrspace(1)* null 111 ret void 112} 113 114; GCN-LABEL: {{^}}array_3xi32: 115; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x0 116; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x4 117; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x8 118; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0xc 119define amdgpu_kernel void @array_3xi32(i16 %arg0, [3 x i32] %arg1) { 120 store volatile i16 %arg0, i16 addrspace(1)* undef 121 store volatile [3 x i32] %arg1, [3 x i32] addrspace(1)* undef 122 ret void 123} 124 125; GCN-LABEL: {{^}}array_3xi16: 126; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x0 127; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x4 128define amdgpu_kernel void @array_3xi16(i8 %arg0, [3 x i16] %arg1) { 129 store volatile i8 %arg0, i8 addrspace(1)* undef 130 store volatile [3 x i16] %arg1, [3 x i16] addrspace(1)* undef 131 ret void 132} 133 134; GCN-LABEL: {{^}}v2i15_arg: 135; GCN: s_load_dword [[DWORD:s[0-9]+]] 136; GCN-DAG: s_bfe_u32 [[BFE:s[0-9]+]], [[DWORD]], 0x100010{{$}} 137; GCN-DAG: s_and_b32 [[AND:s[0-9]+]], [[DWORD]], 0x7fff{{$}} 138define amdgpu_kernel void @v2i15_arg(<2 x i15> addrspace(1)* nocapture %out, <2 x i15> %in) { 139entry: 140 store <2 x i15> %in, <2 x i15> addrspace(1)* %out, align 4 141 ret void 142} 143 144; GCN-LABEL: {{^}}v3i15_arg: 145; GCN: s_load_dword [[DWORD:s[0-9]+]] 146; GCN: s_lshl_b64 147; GCN: s_and_b32 148; GCN: s_and_b32 149; GCN: s_or_b32 150define amdgpu_kernel void @v3i15_arg(<3 x i15> addrspace(1)* nocapture %out, <3 x i15> %in) { 151entry: 152 store <3 x i15> %in, <3 x i15> addrspace(1)* %out, align 4 153 ret void 154} 155 156; Byref pointers should only be treated as offsets from kernarg 157; GCN-LABEL: {{^}}byref_constant_i8_arg: 158; GCN: kernarg_segment_byte_size = 12 159; GCN: v_mov_b32_e32 v[[VPTR_LO:[0-9]+]], s4 160; GCN: v_mov_b32_e32 v[[VPTR_HI:[0-9]+]], s5 161; GCN: global_load_ubyte v{{[0-9]+}}, v{{\[}}[[VPTR_LO]]:[[VPTR_HI]]{{\]}}, off offset:8 162define amdgpu_kernel void @byref_constant_i8_arg(i32 addrspace(1)* nocapture %out, i8 addrspace(4)* byref(i8) %in.byref) { 163 %in = load i8, i8 addrspace(4)* %in.byref 164 %ext = zext i8 %in to i32 165 store i32 %ext, i32 addrspace(1)* %out, align 4 166 ret void 167} 168 169; GCN-LABEL: {{^}}byref_constant_i16_arg: 170; GCN: kernarg_segment_byte_size = 12 171; GCN: v_mov_b32_e32 v[[VPTR_LO:[0-9]+]], s4 172; GCN: v_mov_b32_e32 v[[VPTR_HI:[0-9]+]], s5 173; GCN: global_load_ushort v{{[0-9]+}}, v{{\[}}[[VPTR_LO]]:[[VPTR_HI]]{{\]}}, off offset:8 174define amdgpu_kernel void @byref_constant_i16_arg(i32 addrspace(1)* nocapture %out, i16 addrspace(4)* byref(i16) %in.byref) { 175 %in = load i16, i16 addrspace(4)* %in.byref 176 %ext = zext i16 %in to i32 177 store i32 %ext, i32 addrspace(1)* %out, align 4 178 ret void 179} 180 181; GCN-LABEL: {{^}}byref_constant_i32_arg: 182; GCN: kernarg_segment_byte_size = 16 183; GCN: s_load_dword [[IN:s[0-9]+]], s[4:5], 0x8{{$}} 184; GCN: s_load_dword [[OFFSET:s[0-9]+]], s[4:5], 0xc{{$}} 185define amdgpu_kernel void @byref_constant_i32_arg(i32 addrspace(1)* nocapture %out, i32 addrspace(4)* byref(i32) %in.byref, i32 %after.offset) { 186 %in = load i32, i32 addrspace(4)* %in.byref 187 store volatile i32 %in, i32 addrspace(1)* %out, align 4 188 store volatile i32 %after.offset, i32 addrspace(1)* %out, align 4 189 ret void 190} 191 192; GCN-LABEL: {{^}}byref_constant_v4i32_arg: 193; GCN: kernarg_segment_byte_size = 36 194; GCN: s_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x10{{$}} 195; GCN: s_load_dword s{{[0-9]+}}, s[4:5], 0x20{{$}} 196define amdgpu_kernel void @byref_constant_v4i32_arg(<4 x i32> addrspace(1)* nocapture %out, <4 x i32> addrspace(4)* byref(<4 x i32>) %in.byref, i32 %after.offset) { 197 %in = load <4 x i32>, <4 x i32> addrspace(4)* %in.byref 198 store volatile <4 x i32> %in, <4 x i32> addrspace(1)* %out, align 4 199 %out.cast = bitcast <4 x i32> addrspace(1)* %out to i32 addrspace(1)* 200 store volatile i32 %after.offset, i32 addrspace(1)* %out.cast, align 4 201 ret void 202} 203 204; GCN-LABEL: {{^}}byref_align_constant_i32_arg: 205; GCN: kernarg_segment_byte_size = 264 206; GCN-DAG: s_load_dword [[IN:s[0-9]+]], s[4:5], 0x100{{$}} 207; GCN-DAG: s_load_dword [[AFTER_OFFSET:s[0-9]+]], s[4:5], 0x104{{$}} 208; GCN-DAG: v_mov_b32_e32 [[V_IN:v[0-9]+]], [[IN]] 209; GCN-DAG: v_mov_b32_e32 [[V_AFTER_OFFSET:v[0-9]+]], [[AFTER_OFFSET]] 210; GCN: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[V_IN]] 211; GCN: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[V_AFTER_OFFSET]] 212define amdgpu_kernel void @byref_align_constant_i32_arg(i32 addrspace(1)* nocapture %out, i32 addrspace(4)* byref(i32) align(256) %in.byref, i32 %after.offset) { 213 %in = load i32, i32 addrspace(4)* %in.byref 214 store volatile i32 %in, i32 addrspace(1)* %out, align 4 215 store volatile i32 %after.offset, i32 addrspace(1)* %out, align 4 216 ret void 217} 218 219; GCN-LABEL: {{^}}byref_natural_align_constant_v16i32_arg: 220; GCN: kernarg_segment_byte_size = 132 221; GCN-DAG: s_load_dword s{{[0-9]+}}, s[4:5], 0x80 222; GCN-DAG: s_load_dwordx16 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x40{{$}} 223define amdgpu_kernel void @byref_natural_align_constant_v16i32_arg(i32 addrspace(1)* nocapture %out, i8, <16 x i32> addrspace(4)* byref(<16 x i32>) align(64) %in.byref, i32 %after.offset) { 224 %in = load <16 x i32>, <16 x i32> addrspace(4)* %in.byref 225 %cast.out = bitcast i32 addrspace(1)* %out to <16 x i32> addrspace(1)* 226 store volatile <16 x i32> %in, <16 x i32> addrspace(1)* %cast.out, align 4 227 store volatile i32 %after.offset, i32 addrspace(1)* %out, align 4 228 ret void 229} 230 231; Also accept byref kernel arguments with other global address spaces. 232; GCN-LABEL: {{^}}byref_global_i32_arg: 233; GCN: kernarg_segment_byte_size = 12 234; GCN: s_load_dword [[IN:s[0-9]+]], s[4:5], 0x8{{$}} 235define amdgpu_kernel void @byref_global_i32_arg(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* byref(i32) %in.byref) { 236 %in = load i32, i32 addrspace(1)* %in.byref 237 store i32 %in, i32 addrspace(1)* %out, align 4 238 ret void 239} 240 241; GCN-LABEL: {{^}}byref_flat_i32_arg: 242; GCN: flat_load_dword [[IN:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}} offset:8{{$}} 243define amdgpu_kernel void @byref_flat_i32_arg(i32 addrspace(1)* nocapture %out, i32* byref(i32) %in.byref) { 244 %in = load i32, i32* %in.byref 245 store i32 %in, i32 addrspace(1)* %out, align 4 246 ret void 247} 248 249; GCN-LABEL: {{^}}byref_constant_32bit_i32_arg: 250; GCN: s_add_i32 s[[PTR_LO:[0-9]+]], s4, 8 251; GCN: s_mov_b32 s[[PTR_HI:[0-9]+]], 0{{$}} 252; GCN: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x0{{$}} 253define amdgpu_kernel void @byref_constant_32bit_i32_arg(i32 addrspace(1)* nocapture %out, i32 addrspace(6)* byref(i32) %in.byref) { 254 %in = load i32, i32 addrspace(6)* %in.byref 255 store i32 %in, i32 addrspace(1)* %out, align 4 256 ret void 257} 258 259; define amdgpu_kernel void @byref_unknown_as_i32_arg(i32 addrspace(1)* nocapture %out, i32 addrspace(999)* byref %in.byref) { 260; %in = load i32, i32 addrspace(999)* %in.byref 261; store i32 %in, i32 addrspace(1)* %out, align 4 262; ret void 263; } 264 265; GCN-LABEL: {{^}}multi_byref_constant_i32_arg: 266; GCN: kernarg_segment_byte_size = 20 267; GCN: s_load_dword {{s[0-9]+}}, s[4:5], 0x8 268; GCN: s_load_dword {{s[0-9]+}}, s[4:5], 0xc 269; GCN: s_load_dword {{s[0-9]+}}, s[4:5], 0x10 270define amdgpu_kernel void @multi_byref_constant_i32_arg(i32 addrspace(1)* nocapture %out, i32 addrspace(4)* byref(i32) %in0.byref, i32 addrspace(4)* byref(i32) %in1.byref, i32 %after.offset) { 271 %in0 = load i32, i32 addrspace(4)* %in0.byref 272 %in1 = load i32, i32 addrspace(4)* %in1.byref 273 store volatile i32 %in0, i32 addrspace(1)* %out, align 4 274 store volatile i32 %in1, i32 addrspace(1)* %out, align 4 275 store volatile i32 %after.offset, i32 addrspace(1)* %out, align 4 276 ret void 277} 278 279; GCN-LABEL: {{^}}byref_constant_i32_arg_offset0: 280; GCN: kernarg_segment_byte_size = 4 281; GCN-NOT: s4 282; GCN-NOT: s5 283; GCN: s_load_dword {{s[0-9]+}}, s[4:5], 0x0{{$}} 284define amdgpu_kernel void @byref_constant_i32_arg_offset0(i32 addrspace(4)* byref(i32) %in.byref) { 285 %in = load i32, i32 addrspace(4)* %in.byref 286 store i32 %in, i32 addrspace(1)* undef, align 4 287 ret void 288} 289