1; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope --check-prefixes=SI,GCN,MESA-GCN,FUNC %s 2; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=VI,GCN,MESA-VI,MESA-GCN,FUNC %s 3; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=VI,GCN,HSA-VI,FUNC %s 4; RUN: llc < %s -march=r600 -mcpu=redwood -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=EG,EGCM,FUNC %s 5; RUN: llc < %s -march=r600 -mcpu=cayman -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope --check-prefixes=CM,EGCM,FUNC %s 6 7; FUNC-LABEL: {{^}}i8_arg: 8; HSA-VI: kernarg_segment_byte_size = 12 9; HSA-VI: kernarg_segment_alignment = 4 10 11; SI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb 12; MESA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c 13; MESA-GCN: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xff 14 15; HSA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8 16; HSA-VI: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xff 17 18 19; EG: LSHR T0.X, KC0[2].Y, literal.x, 20; EG-NEXT: MOV * T1.X, KC0[2].Z, 21; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 22 23; CM: LSHR * T0.X, KC0[2].Y, literal.x, 24; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) 25; CM-NEXT: MOV * T1.X, KC0[2].Z, 26define amdgpu_kernel void @i8_arg(i32 addrspace(1)* nocapture %out, i8 %in) nounwind { 27 %ext = zext i8 %in to i32 28 store i32 %ext, i32 addrspace(1)* %out, align 4 29 ret void 30} 31 32; FUNC-LABEL: {{^}}i8_zext_arg: 33; HSA-VI: kernarg_segment_byte_size = 12 34; HSA-VI: kernarg_segment_alignment = 4 35; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb 36; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c 37 38; HSA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8 39; HSA-VI: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xff 40 41 42; EG: BFE_INT T0.X, T0.X, 0.0, literal.x, 43; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, 44; EG-NEXT: 8(1.121039e-44), 2(2.802597e-45) 45 46; CM: BFE_INT * T0.X, T0.X, 0.0, literal.x, 47; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) 48; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 49; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) 50define amdgpu_kernel void @i8_zext_arg(i32 addrspace(1)* nocapture %out, i8 zeroext %in) nounwind { 51 %ext = zext i8 %in to i32 52 store i32 %ext, i32 addrspace(1)* %out, align 4 53 ret void 54} 55 56; FUNC-LABEL: {{^}}i8_sext_arg: 57; HSA-VI: kernarg_segment_byte_size = 12 58; HSA-VI: kernarg_segment_alignment = 4 59; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb 60 61; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c 62 63; HSA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8 64; HSA-VI: s_sext_i32_i8 s{{[0-9]+}}, [[VAL]] 65; HSA-VI: flat_store_dword 66 67 68; EG: BFE_INT T0.X, T0.X, 0.0, literal.x, 69; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, 70; EG-NEXT: 8(1.121039e-44), 2(2.802597e-45) 71 72; CM: BFE_INT * T0.X, T0.X, 0.0, literal.x, 73; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) 74; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 75; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) 76define amdgpu_kernel void @i8_sext_arg(i32 addrspace(1)* nocapture %out, i8 signext %in) nounwind { 77 %ext = sext i8 %in to i32 78 store i32 %ext, i32 addrspace(1)* %out, align 4 79 ret void 80} 81 82; FUNC-LABEL: {{^}}i16_arg: 83; HSA-VI: kernarg_segment_byte_size = 12 84; HSA-VI: kernarg_segment_alignment = 4 85 86; SI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb 87 88; MESA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c 89; MESA-GCN: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xff 90 91; HSA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8 92; HSA-VI: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xffff{{$}} 93; HSA-VI: flat_store_dword 94 95 96; EG: LSHR T0.X, KC0[2].Y, literal.x, 97; EG-NEXT: MOV * T1.X, KC0[2].Z, 98; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 99 100; CM: LSHR * T0.X, KC0[2].Y, literal.x, 101; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) 102; CM-NEXT: MOV * T1.X, KC0[2].Z, 103define amdgpu_kernel void @i16_arg(i32 addrspace(1)* nocapture %out, i16 %in) nounwind { 104 %ext = zext i16 %in to i32 105 store i32 %ext, i32 addrspace(1)* %out, align 4 106 ret void 107} 108 109; FUNC-LABEL: {{^}}i16_zext_arg: 110; HSA-VI: kernarg_segment_byte_size = 12 111; HSA-VI: kernarg_segment_alignment = 4 112 113; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb 114; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c 115 116; HSA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8 117; HSA-VI: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xffff{{$}} 118; HSA-VI: flat_store_dword 119 120; EG: BFE_INT T0.X, T0.X, 0.0, literal.x, 121; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, 122; EG-NEXT: 16(2.242078e-44), 2(2.802597e-45) 123 124; CM: BFE_INT * T0.X, T0.X, 0.0, literal.x, 125; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00) 126; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 127; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) 128define amdgpu_kernel void @i16_zext_arg(i32 addrspace(1)* nocapture %out, i16 zeroext %in) nounwind { 129 %ext = zext i16 %in to i32 130 store i32 %ext, i32 addrspace(1)* %out, align 4 131 ret void 132} 133 134; FUNC-LABEL: {{^}}i16_sext_arg: 135; HSA-VI: kernarg_segment_byte_size = 12 136; HSA-VI: kernarg_segment_alignment = 4 137 138; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb 139; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c 140 141 142; HSA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8 143; HSA-VI: s_sext_i32_i16 s{{[0-9]+}}, [[VAL]] 144; HSA-VI: flat_store_dword 145 146; EG: BFE_INT T0.X, T0.X, 0.0, literal.x, 147; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, 148; EG-NEXT: 16(2.242078e-44), 2(2.802597e-45) 149 150; CM: BFE_INT * T0.X, T0.X, 0.0, literal.x, 151; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00) 152; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 153; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) 154define amdgpu_kernel void @i16_sext_arg(i32 addrspace(1)* nocapture %out, i16 signext %in) nounwind { 155 %ext = sext i16 %in to i32 156 store i32 %ext, i32 addrspace(1)* %out, align 4 157 ret void 158} 159 160; FUNC-LABEL: {{^}}i32_arg: 161; HSA-VI: kernarg_segment_byte_size = 12 162; HSA-VI: kernarg_segment_alignment = 4 163 164; EGCM: T{{[0-9]\.[XYZW]}}, KC0[2].Z 165; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb 166; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c 167; HSA-VI: s_load_dword s{{[0-9]}}, s[4:5], 0x8 168define amdgpu_kernel void @i32_arg(i32 addrspace(1)* nocapture %out, i32 %in) nounwind { 169entry: 170 store i32 %in, i32 addrspace(1)* %out, align 4 171 ret void 172} 173 174; FUNC-LABEL: {{^}}f32_arg: 175; HSA-VI: kernarg_segment_byte_size = 12 176; HSA-VI: kernarg_segment_alignment = 4 177; EGCM: T{{[0-9]\.[XYZW]}}, KC0[2].Z 178; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb 179; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c 180; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x8 181define amdgpu_kernel void @f32_arg(float addrspace(1)* nocapture %out, float %in) nounwind { 182entry: 183 store float %in, float addrspace(1)* %out, align 4 184 ret void 185} 186 187; FUNC-LABEL: {{^}}v2i8_arg: 188; HSA-VI: kernarg_segment_byte_size = 12 189; HSA-VI: kernarg_segment_alignment = 4 190 191; EGCM: VTX_READ_8 192; EGCM: VTX_READ_8 193 194; GCN: s_load_dword s 195; GCN-NOT: {{buffer|flat|global}}_load_ 196define amdgpu_kernel void @v2i8_arg(<2 x i8> addrspace(1)* %out, <2 x i8> %in) { 197entry: 198 store <2 x i8> %in, <2 x i8> addrspace(1)* %out 199 ret void 200} 201 202; FUNC-LABEL: {{^}}v2i16_arg: 203; HSA-VI: kernarg_segment_byte_size = 12 204; HSA-VI: kernarg_segment_alignment = 4 205 206; EGCM: VTX_READ_16 207; EGCM: VTX_READ_16 208 209; SI: s_load_dword s{{[0-9]+}}, s[0:1], 0xb 210; MESA-VI: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c 211; HSA-VI: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0x8 212define amdgpu_kernel void @v2i16_arg(<2 x i16> addrspace(1)* %out, <2 x i16> %in) { 213entry: 214 store <2 x i16> %in, <2 x i16> addrspace(1)* %out 215 ret void 216} 217 218; FUNC-LABEL: {{^}}v2i32_arg: 219; HSA-VI: kernarg_segment_byte_size = 16 220; HSA-VI: kernarg_segment_alignment = 4 221 222; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X 223; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W 224; SI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xb 225; MESA-VI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x2c 226; HSA-VI: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x8 227define amdgpu_kernel void @v2i32_arg(<2 x i32> addrspace(1)* nocapture %out, <2 x i32> %in) nounwind { 228entry: 229 store <2 x i32> %in, <2 x i32> addrspace(1)* %out, align 4 230 ret void 231} 232 233; FUNC-LABEL: {{^}}v2f32_arg: 234; HSA-VI: kernarg_segment_byte_size = 16 235; HSA-VI: kernarg_segment_alignment = 4 236 237; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X 238; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W 239; SI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xb 240; MESA-VI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x2c 241; HSA-VI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[4:5], 0x8 242define amdgpu_kernel void @v2f32_arg(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) nounwind { 243entry: 244 store <2 x float> %in, <2 x float> addrspace(1)* %out, align 4 245 ret void 246} 247 248; FUNC-LABEL: {{^}}v3i8_arg: 249; HSA-VI: kernarg_segment_byte_size = 12 250; HSA-VI: kernarg_segment_alignment = 4 251 252; EGCM-DAG: VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 40 253; EGCM-DAG: VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 41 254; EGCM-DAG: VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 42 255 256; SI: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb 257 258; VI-MESA: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c 259; VI-HSA: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0x8 260define amdgpu_kernel void @v3i8_arg(<3 x i8> addrspace(1)* nocapture %out, <3 x i8> %in) nounwind { 261entry: 262 store <3 x i8> %in, <3 x i8> addrspace(1)* %out, align 4 263 ret void 264} 265 266; FUNC-LABEL: {{^}}v3i16_arg: 267; HSA-VI: kernarg_segment_byte_size = 16 268; HSA-VI: kernarg_segment_alignment = 4 269 270; EGCM-DAG: VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 44 271; EGCM-DAG: VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 46 272; EGCM-DAG: VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 48 273 274; SI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb 275 276; VI-HSA: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x8 277; VI-MESA: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c 278define amdgpu_kernel void @v3i16_arg(<3 x i16> addrspace(1)* nocapture %out, <3 x i16> %in) nounwind { 279entry: 280 store <3 x i16> %in, <3 x i16> addrspace(1)* %out, align 4 281 ret void 282} 283 284; FUNC-LABEL: {{^}}v3i32_arg: 285; HSA-VI: kernarg_segment_byte_size = 32 286; HSA-VI: kernarg_segment_alignment = 4 287; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y 288; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z 289; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W 290; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0xd 291; MESA-VI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x34 292; HSA-VI: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x10 293define amdgpu_kernel void @v3i32_arg(<3 x i32> addrspace(1)* nocapture %out, <3 x i32> %in) nounwind { 294entry: 295 store <3 x i32> %in, <3 x i32> addrspace(1)* %out, align 4 296 ret void 297} 298 299; FUNC-LABEL: {{^}}v3f32_arg: 300; HSA-VI: kernarg_segment_byte_size = 32 301; HSA-VI: kernarg_segment_alignment = 4 302; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y 303; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z 304; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W 305; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0xd 306; MESA-VI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x34 307; HSA-VI: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x10 308define amdgpu_kernel void @v3f32_arg(<3 x float> addrspace(1)* nocapture %out, <3 x float> %in) nounwind { 309entry: 310 store <3 x float> %in, <3 x float> addrspace(1)* %out, align 4 311 ret void 312} 313 314; FUNC-LABEL: {{^}}v4i8_arg: 315; HSA-VI: kernarg_segment_byte_size = 12 316; HSA-VI: kernarg_segment_alignment = 4 317; EGCM: VTX_READ_8 318; EGCM: VTX_READ_8 319; EGCM: VTX_READ_8 320; EGCM: VTX_READ_8 321 322; GCN-DAG: s_load_dwordx2 s 323; GCN-DAG: s_load_dword s 324define amdgpu_kernel void @v4i8_arg(<4 x i8> addrspace(1)* %out, <4 x i8> %in) { 325entry: 326 store <4 x i8> %in, <4 x i8> addrspace(1)* %out 327 ret void 328} 329 330; FUNC-LABEL: {{^}}v4i16_arg: 331; HSA-VI: kernarg_segment_byte_size = 16 332; HSA-VI: kernarg_segment_alignment = 4 333; EGCM: VTX_READ_16 334; EGCM: VTX_READ_16 335; EGCM: VTX_READ_16 336; EGCM: VTX_READ_16 337 338; SI-DAG: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0xb 339; SI-DAG: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x9 340 341; MESA-VI-DAG: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x24 342; MESA-VI-DAG: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x2c 343 344 345; MESA-VI-DAG: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x24 346; MESA-VI-DAG: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x2c 347 348; HSA-VI-DAG: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x0 349; HSA-VI-DAG: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x8 350define amdgpu_kernel void @v4i16_arg(<4 x i16> addrspace(1)* %out, <4 x i16> %in) { 351entry: 352 store <4 x i16> %in, <4 x i16> addrspace(1)* %out 353 ret void 354} 355 356; FUNC-LABEL: {{^}}v4i32_arg: 357; HSA-VI: kernarg_segment_byte_size = 32 358; HSA-VI: kernarg_segment_alignment = 4 359; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y 360; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z 361; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W 362; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].X 363 364; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xd 365; MESA-VI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x34 366; HSA-VI: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x10 367define amdgpu_kernel void @v4i32_arg(<4 x i32> addrspace(1)* nocapture %out, <4 x i32> %in) nounwind { 368entry: 369 store <4 x i32> %in, <4 x i32> addrspace(1)* %out, align 4 370 ret void 371} 372 373; FUNC-LABEL: {{^}}v4f32_arg: 374; HSA-VI: kernarg_segment_byte_size = 32 375; HSA-VI: kernarg_segment_alignment = 4 376; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y 377; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z 378; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W 379; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].X 380; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xd 381; MESA-VI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x34 382; HSA-VI: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x10 383define amdgpu_kernel void @v4f32_arg(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) nounwind { 384entry: 385 store <4 x float> %in, <4 x float> addrspace(1)* %out, align 4 386 ret void 387} 388 389; FIXME: Lots of unpack and re-pack junk on VI 390; FUNC-LABEL: {{^}}v8i8_arg: 391; HSA-VI: kernarg_segment_byte_size = 16 392; HSA-VI: kernarg_segment_alignment = 4 393; EGCM: VTX_READ_8 394; EGCM: VTX_READ_8 395; EGCM: VTX_READ_8 396; EGCM: VTX_READ_8 397; EGCM: VTX_READ_8 398; EGCM: VTX_READ_8 399; EGCM: VTX_READ_8 400; EGCM: VTX_READ_8 401 402; SI-NOT: {{buffer|flat|global}}_load 403; SI: s_load_dwordx2 s 404; SI-NEXT: s_load_dwordx2 s 405; SI-NOT: {{buffer|flat|global}}_load 406 407; VI: s_load_dwordx2 s 408; VI-NEXT: s_load_dwordx2 s 409; VI-NOT: lshl 410; VI-NOT: _or 411; VI-NOT: _sdwa 412define amdgpu_kernel void @v8i8_arg(<8 x i8> addrspace(1)* %out, <8 x i8> %in) { 413entry: 414 store <8 x i8> %in, <8 x i8> addrspace(1)* %out 415 ret void 416} 417 418; FUNC-LABEL: {{^}}v8i16_arg: 419; HSA-VI: kernarg_segment_byte_size = 32 420; HSA-VI: kernarg_segment_alignment = 4 421; EGCM: VTX_READ_16 422; EGCM: VTX_READ_16 423; EGCM: VTX_READ_16 424; EGCM: VTX_READ_16 425; EGCM: VTX_READ_16 426; EGCM: VTX_READ_16 427; EGCM: VTX_READ_16 428; EGCM: VTX_READ_16 429 430; SI: s_load_dwordx4 431; SI-NEXT: s_load_dwordx2 432; SI-NOT: {{buffer|flat|global}}_load 433 434 435; MESA-VI: s_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x34 436 437; HSA-VI: s_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x10 438define amdgpu_kernel void @v8i16_arg(<8 x i16> addrspace(1)* %out, <8 x i16> %in) { 439entry: 440 store <8 x i16> %in, <8 x i16> addrspace(1)* %out 441 ret void 442} 443 444; FUNC-LABEL: {{^}}v8i32_arg: 445; HSA-VI: kernarg_segment_byte_size = 64 446; HSA-VI: kernarg_segment_alignment = 5 447; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Y 448; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Z 449; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].W 450; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].X 451; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Y 452; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Z 453; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].W 454; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].X 455 456; SI: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x11 457; MESA-VI: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x44 458; HSA-VI: s_load_dwordx8 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x20 459define amdgpu_kernel void @v8i32_arg(<8 x i32> addrspace(1)* nocapture %out, <8 x i32> %in) nounwind { 460entry: 461 store <8 x i32> %in, <8 x i32> addrspace(1)* %out, align 4 462 ret void 463} 464 465; FUNC-LABEL: {{^}}v8f32_arg: 466; HSA-VI: kernarg_segment_byte_size = 64 467; HSA-VI: kernarg_segment_alignment = 5 468; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Y 469; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Z 470; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].W 471; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].X 472; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Y 473; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Z 474; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].W 475; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].X 476; SI: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x11 477define amdgpu_kernel void @v8f32_arg(<8 x float> addrspace(1)* nocapture %out, <8 x float> %in) nounwind { 478entry: 479 store <8 x float> %in, <8 x float> addrspace(1)* %out, align 4 480 ret void 481} 482 483; FIXME: Pack/repack on VI 484 485; FUNC-LABEL: {{^}}v16i8_arg: 486; HSA-VI: kernarg_segment_byte_size = 32 487; HSA-VI: kernarg_segment_alignment = 4 488; EGCM: VTX_READ_8 489; EGCM: VTX_READ_8 490; EGCM: VTX_READ_8 491; EGCM: VTX_READ_8 492; EGCM: VTX_READ_8 493; EGCM: VTX_READ_8 494; EGCM: VTX_READ_8 495; EGCM: VTX_READ_8 496; EGCM: VTX_READ_8 497; EGCM: VTX_READ_8 498; EGCM: VTX_READ_8 499; EGCM: VTX_READ_8 500; EGCM: VTX_READ_8 501; EGCM: VTX_READ_8 502; EGCM: VTX_READ_8 503; EGCM: VTX_READ_8 504 505; SI: s_load_dwordx4 s 506; SI-NEXT: s_load_dwordx2 s 507; SI-NOT: {{buffer|flat|global}}_load 508 509 510; VI: s_load_dwordx4 s 511; VI-NOT: shr 512; VI-NOT: shl 513; VI-NOT: _sdwa 514; VI-NOT: _or_ 515define amdgpu_kernel void @v16i8_arg(<16 x i8> addrspace(1)* %out, <16 x i8> %in) { 516entry: 517 store <16 x i8> %in, <16 x i8> addrspace(1)* %out 518 ret void 519} 520 521; FUNC-LABEL: {{^}}v16i16_arg: 522; HSA-VI: kernarg_segment_byte_size = 64 523; HSA-VI: kernarg_segment_alignment = 5 524; EGCM: VTX_READ_16 525; EGCM: VTX_READ_16 526; EGCM: VTX_READ_16 527; EGCM: VTX_READ_16 528; EGCM: VTX_READ_16 529 530; EGCM: VTX_READ_16 531; EGCM: VTX_READ_16 532; EGCM: VTX_READ_16 533; EGCM: VTX_READ_16 534; EGCM: VTX_READ_16 535; EGCM: VTX_READ_16 536; EGCM: VTX_READ_16 537; EGCM: VTX_READ_16 538; EGCM: VTX_READ_16 539; EGCM: VTX_READ_16 540; EGCM: VTX_READ_16 541 542; SI: s_load_dwordx8 s 543; SI-NEXT: s_load_dwordx2 s 544; SI-NOT: {{buffer|flat|global}}_load 545 546 547; MESA-VI: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x44 548 549; HSA-VI: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x20 550define amdgpu_kernel void @v16i16_arg(<16 x i16> addrspace(1)* %out, <16 x i16> %in) { 551entry: 552 store <16 x i16> %in, <16 x i16> addrspace(1)* %out 553 ret void 554} 555 556; FUNC-LABEL: {{^}}v16i32_arg: 557; HSA-VI: kernarg_segment_byte_size = 128 558; HSA-VI: kernarg_segment_alignment = 6 559; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Y 560; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Z 561; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].W 562; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].X 563; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Y 564; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Z 565; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].W 566; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].X 567; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Y 568; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Z 569; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].W 570; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].X 571; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Y 572; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Z 573; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].W 574; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X 575; SI: s_load_dwordx16 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x19 576; MESA-VI: s_load_dwordx16 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x64 577; HSA-VI: s_load_dwordx16 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x40 578define amdgpu_kernel void @v16i32_arg(<16 x i32> addrspace(1)* nocapture %out, <16 x i32> %in) nounwind { 579entry: 580 store <16 x i32> %in, <16 x i32> addrspace(1)* %out, align 4 581 ret void 582} 583 584; FUNC-LABEL: {{^}}v16f32_arg: 585; HSA-VI: kernarg_segment_byte_size = 128 586; HSA-VI: kernarg_segment_alignment = 6 587; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Y 588; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Z 589; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].W 590; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].X 591; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Y 592; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Z 593; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].W 594; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].X 595; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Y 596; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Z 597; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].W 598; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].X 599; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Y 600; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Z 601; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].W 602; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X 603; SI: s_load_dwordx16 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x19 604; MESA-VI: s_load_dwordx16 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x64 605; HSA-VI: s_load_dwordx16 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x40 606define amdgpu_kernel void @v16f32_arg(<16 x float> addrspace(1)* nocapture %out, <16 x float> %in) nounwind { 607entry: 608 store <16 x float> %in, <16 x float> addrspace(1)* %out, align 4 609 ret void 610} 611 612; FUNC-LABEL: {{^}}kernel_arg_i64: 613; MESA-VI: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[0:1], 0x24 614; HSA-VI: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x0 615 616; MESA-GCN: buffer_store_dwordx2 617define amdgpu_kernel void @kernel_arg_i64(i64 addrspace(1)* %out, i64 %a) nounwind { 618 store i64 %a, i64 addrspace(1)* %out, align 8 619 ret void 620} 621 622; FUNC-LABEL: {{^}}f64_kernel_arg: 623; SI-DAG: s_load_dwordx4 s[{{[0-9]:[0-9]}}], s[0:1], 0x9 624; MESA-VI-DAG: s_load_dwordx4 s[{{[0-9]:[0-9]}}], s[0:1], 0x24 625; MESA-GCN: buffer_store_dwordx2 626 627; HSA-VI: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x0 628define amdgpu_kernel void @f64_kernel_arg(double addrspace(1)* %out, double %in) { 629entry: 630 store double %in, double addrspace(1)* %out 631 ret void 632} 633 634; XFUNC-LABEL: {{^}}kernel_arg_v1i64: 635; XGCN: s_load_dwordx2 636; XGCN: s_load_dwordx2 637; XGCN: buffer_store_dwordx2 638; define amdgpu_kernel void @kernel_arg_v1i64(<1 x i64> addrspace(1)* %out, <1 x i64> %a) nounwind { 639; store <1 x i64> %a, <1 x i64> addrspace(1)* %out, align 8 640; ret void 641; } 642 643; FUNC-LABEL: {{^}}i65_arg: 644; HSA-VI: kernarg_segment_byte_size = 24 645; HSA-VI: kernarg_segment_alignment = 4 646; HSA-VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x0 647; HSA-VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x8 648define amdgpu_kernel void @i65_arg(i65 addrspace(1)* nocapture %out, i65 %in) nounwind { 649entry: 650 store i65 %in, i65 addrspace(1)* %out, align 4 651 ret void 652} 653 654; FUNC-LABEL: {{^}}i1_arg: 655; HSA-VI: kernarg_segment_byte_size = 12 656; HSA-VI: kernarg_segment_alignment = 4 657 658; GCN: s_load_dword s 659; GCN: s_and_b32 660; GCN: {{buffer|flat}}_store_byte 661define amdgpu_kernel void @i1_arg(i1 addrspace(1)* %out, i1 %x) nounwind { 662 store i1 %x, i1 addrspace(1)* %out, align 1 663 ret void 664} 665 666; FUNC-LABEL: {{^}}i1_arg_zext_i32: 667; HSA-VI: kernarg_segment_byte_size = 12 668; HSA-VI: kernarg_segment_alignment = 4 669 670; GCN: s_load_dword 671; SGCN: buffer_store_dword 672define amdgpu_kernel void @i1_arg_zext_i32(i32 addrspace(1)* %out, i1 %x) nounwind { 673 %ext = zext i1 %x to i32 674 store i32 %ext, i32 addrspace(1)* %out, align 4 675 ret void 676} 677 678; FUNC-LABEL: {{^}}i1_arg_zext_i64: 679; HSA-VI: kernarg_segment_byte_size = 12 680; HSA-VI: kernarg_segment_alignment = 4 681 682; GCN: s_load_dword s 683; GCN: {{buffer|flat}}_store_dwordx2 684define amdgpu_kernel void @i1_arg_zext_i64(i64 addrspace(1)* %out, i1 %x) nounwind { 685 %ext = zext i1 %x to i64 686 store i64 %ext, i64 addrspace(1)* %out, align 8 687 ret void 688} 689 690; FUNC-LABEL: {{^}}i1_arg_sext_i32: 691; HSA-VI: kernarg_segment_byte_size = 12 692; HSA-VI: kernarg_segment_alignment = 4 693 694; GCN: s_load_dword 695; GCN: {{buffer|flat}}_store_dword 696define amdgpu_kernel void @i1_arg_sext_i32(i32 addrspace(1)* %out, i1 %x) nounwind { 697 %ext = sext i1 %x to i32 698 store i32 %ext, i32addrspace(1)* %out, align 4 699 ret void 700} 701 702; FUNC-LABEL: {{^}}i1_arg_sext_i64: 703; HSA-VI: kernarg_segment_byte_size = 12 704; HSA-VI: kernarg_segment_alignment = 4 705 706; GCN: s_load_dword 707; GCN: s_bfe_i64 708; GCN: {{buffer|flat}}_store_dwordx2 709define amdgpu_kernel void @i1_arg_sext_i64(i64 addrspace(1)* %out, i1 %x) nounwind { 710 %ext = sext i1 %x to i64 711 store i64 %ext, i64 addrspace(1)* %out, align 8 712 ret void 713} 714 715; FUNC-LABEL: {{^}}empty_struct_arg: 716; HSA-VI: kernarg_segment_byte_size = 0 717define amdgpu_kernel void @empty_struct_arg({} %in) nounwind { 718 ret void 719} 720 721; The correct load offsets for these: 722; load 4 from 0, 723; load 8 from 8 724; load 4 from 24 725; load 8 from 32 726 727; With the SelectionDAG argument lowering, the alignments for the 728; struct members is not properly considered, making these wrong. 729 730; FIXME: Total argument size is computed wrong 731; FUNC-LABEL: {{^}}struct_argument_alignment: 732; HSA-VI: kernarg_segment_byte_size = 40 733; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x0 734; HSA-VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x8 735; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x18 736; HSA-VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x20 737define amdgpu_kernel void @struct_argument_alignment({i32, i64} %arg0, i8, {i32, i64} %arg1) { 738 %val0 = extractvalue {i32, i64} %arg0, 0 739 %val1 = extractvalue {i32, i64} %arg0, 1 740 %val2 = extractvalue {i32, i64} %arg1, 0 741 %val3 = extractvalue {i32, i64} %arg1, 1 742 store volatile i32 %val0, i32 addrspace(1)* null 743 store volatile i64 %val1, i64 addrspace(1)* null 744 store volatile i32 %val2, i32 addrspace(1)* null 745 store volatile i64 %val3, i64 addrspace(1)* null 746 ret void 747} 748 749; No padding between i8 and next struct, but round up at end to 4 byte 750; multiple. 751; FUNC-LABEL: {{^}}packed_struct_argument_alignment: 752; HSA-VI: kernarg_segment_byte_size = 28 753; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x0 754; HSA-VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x4 755; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0xc 756; HSA-VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x10 757define amdgpu_kernel void @packed_struct_argument_alignment(<{i32, i64}> %arg0, i8, <{i32, i64}> %arg1) { 758 %val0 = extractvalue <{i32, i64}> %arg0, 0 759 %val1 = extractvalue <{i32, i64}> %arg0, 1 760 %val2 = extractvalue <{i32, i64}> %arg1, 0 761 %val3 = extractvalue <{i32, i64}> %arg1, 1 762 store volatile i32 %val0, i32 addrspace(1)* null 763 store volatile i64 %val1, i64 addrspace(1)* null 764 store volatile i32 %val2, i32 addrspace(1)* null 765 store volatile i64 %val3, i64 addrspace(1)* null 766 ret void 767} 768 769; GCN-LABEL: {{^}}struct_argument_alignment_after: 770; HSA-VI: kernarg_segment_byte_size = 64 771; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x0 772; HSA-VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x8 773; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x18 774; HSA-VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x20 775; HSA-VI: s_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x30 776define amdgpu_kernel void @struct_argument_alignment_after({i32, i64} %arg0, i8, {i32, i64} %arg2, i8, <4 x i32> %arg4) { 777 %val0 = extractvalue {i32, i64} %arg0, 0 778 %val1 = extractvalue {i32, i64} %arg0, 1 779 %val2 = extractvalue {i32, i64} %arg2, 0 780 %val3 = extractvalue {i32, i64} %arg2, 1 781 store volatile i32 %val0, i32 addrspace(1)* null 782 store volatile i64 %val1, i64 addrspace(1)* null 783 store volatile i32 %val2, i32 addrspace(1)* null 784 store volatile i64 %val3, i64 addrspace(1)* null 785 store volatile <4 x i32> %arg4, <4 x i32> addrspace(1)* null 786 ret void 787} 788 789; GCN-LABEL: {{^}}array_3xi32: 790; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x0 791; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x4 792; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x8 793; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0xc 794define amdgpu_kernel void @array_3xi32(i16 %arg0, [3 x i32] %arg1) { 795 store volatile i16 %arg0, i16 addrspace(1)* undef 796 store volatile [3 x i32] %arg1, [3 x i32] addrspace(1)* undef 797 ret void 798} 799 800; FIXME: Why not all scalar loads? 801; GCN-LABEL: {{^}}array_3xi16: 802; HSA-VI: s_add_u32 s{{[0-9]+}}, s4, 2 803; HSA-VI: s_addc_u32 s{{[0-9]+}}, s5, 0 804; HSA-VI: flat_load_ushort 805; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x0 806; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x4 807define amdgpu_kernel void @array_3xi16(i8 %arg0, [3 x i16] %arg1) { 808 store volatile i8 %arg0, i8 addrspace(1)* undef 809 store volatile [3 x i16] %arg1, [3 x i16] addrspace(1)* undef 810 ret void 811} 812