1# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass post-RA-hazard-rec %s -o - | FileCheck %s -check-prefixes=GCN 2# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass post-RA-hazard-rec %s -o - | FileCheck %s -check-prefixes=GCN,CIVI 3# RUN: llc -march=amdgcn -mcpu=fiji -run-pass post-RA-hazard-rec %s -o - | FileCheck %s -check-prefixes=GCN,CIVI,VI 4# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass post-RA-hazard-rec %s -o - | FileCheck %s -check-prefixes=GCN,CIVI,VI,GFX9 5 6--- | 7 define void @div_fmas() { ret void } 8 define void @s_getreg() { ret void } 9 define void @s_setreg() { ret void } 10 define void @vmem_gt_8dw_store() { ret void } 11 define void @readwrite_lane() { ret void } 12 define void @rfe() { ret void } 13 define void @s_mov_fed_b32() { ret void } 14 define void @s_movrel() { ret void } 15 define void @v_interp() { ret void } 16 17 define void @mov_fed_hazard_crash_on_dbg_value(i32 addrspace(1)* %A) { 18 entry: 19 %A.addr = alloca i32 addrspace(1)*, align 4 20 store i32 addrspace(1)* %A, i32 addrspace(1)** %A.addr, align 4 21 call void @llvm.dbg.declare(metadata i32 addrspace(1)** %A.addr, metadata !5, metadata !11), !dbg !12 22 ret void 23 } 24 25 declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 26 27 !llvm.dbg.cu = !{!0} 28 !llvm.module.flags = !{!3, !4} 29 30 !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.9.0 (trunk 268929)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) 31 !1 = !DIFile(filename: "test01.cl", directory: "/dev/null") 32 !2 = !{} 33 !3 = !{i32 2, !"Dwarf Version", i32 2} 34 !4 = !{i32 2, !"Debug Info Version", i32 3} 35 !5 = !DILocalVariable(name: "A", arg: 1, scope: !6, file: !1, line: 1, type: !9) 36 !6 = distinct !DISubprogram(name: "test", scope: !1, file: !1, line: 1, type: !7, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2) 37 !7 = !DISubroutineType(types: !8) 38 !8 = !{null, !9} 39 !9 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !10, size: 64, align: 32) 40 !10 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) 41 !11 = !DIExpression() 42 !12 = !DILocation(line: 1, column: 30, scope: !6) 43 44... 45--- 46# GCN-LABEL: name: div_fmas 47 48# GCN-LABEL: bb.0: 49# GCN: S_MOV_B64 50# GCN-NOT: S_NOP 51# GCN: V_DIV_FMAS 52 53# GCN-LABEL: bb.1: 54# GCN: V_CMP_EQ_I32 55# GCN: S_NOP 56# GCN: S_NOP 57# GCN: S_NOP 58# GCN: S_NOP 59# GCN: V_DIV_FMAS_F32 60 61# GCN-LABEL: bb.2: 62# GCN: V_CMP_EQ_I32 63# GCN: S_NOP 64# GCN: S_NOP 65# GCN: S_NOP 66# GCN: S_NOP 67# GCN: V_DIV_FMAS_F32 68 69# GCN-LABEL: bb.3: 70# GCN: V_DIV_SCALE_F32 71# GCN: S_NOP 72# GCN: S_NOP 73# GCN: S_NOP 74# GCN: S_NOP 75# GCN: V_DIV_FMAS_F32 76name: div_fmas 77 78body: | 79 bb.0: 80 successors: %bb.1 81 %vcc = S_MOV_B64 0 82 %vgpr0 = V_DIV_FMAS_F32 0, %vgpr1, 0, %vgpr2, 0, %vgpr3, 0, 0, implicit %vcc, implicit %exec 83 S_BRANCH %bb.1 84 85 bb.1: 86 successors: %bb.2 87 implicit %vcc = V_CMP_EQ_I32_e32 %vgpr1, %vgpr2, implicit %exec 88 %vgpr0 = V_DIV_FMAS_F32 0, %vgpr1, 0, %vgpr2, 0, %vgpr3, 0, 0, implicit %vcc, implicit %exec 89 S_BRANCH %bb.2 90 91 bb.2: 92 successors: %bb.3 93 %vcc = V_CMP_EQ_I32_e64 %vgpr1, %vgpr2, implicit %exec 94 %vgpr0 = V_DIV_FMAS_F32 0, %vgpr1, 0, %vgpr2, 0, %vgpr3, 0, 0, implicit %vcc, implicit %exec 95 S_BRANCH %bb.3 96 97 bb.3: 98 %vgpr4, %vcc = V_DIV_SCALE_F32 %vgpr1, %vgpr1, %vgpr3, implicit %exec 99 %vgpr0 = V_DIV_FMAS_F32 0, %vgpr1, 0, %vgpr2, 0, %vgpr3, 0, 0, implicit %vcc, implicit %exec 100 S_ENDPGM 101 102... 103 104... 105--- 106# GCN-LABEL: name: s_getreg 107 108# GCN-LABEL: bb.0: 109# GCN: S_SETREG 110# GCN: S_NOP 0 111# GCN: S_NOP 0 112# GCN: S_GETREG 113 114# GCN-LABEL: bb.1: 115# GCN: S_SETREG_IMM32 116# GCN: S_NOP 0 117# GCN: S_NOP 0 118# GCN: S_GETREG 119 120# GCN-LABEL: bb.2: 121# GCN: S_SETREG 122# GCN: S_NOP 0 123# GCN: S_GETREG 124 125# GCN-LABEL: bb.3: 126# GCN: S_SETREG 127# GCN-NEXT: S_GETREG 128 129name: s_getreg 130 131body: | 132 bb.0: 133 successors: %bb.1 134 S_SETREG_B32 %sgpr0, 1 135 %sgpr1 = S_GETREG_B32 1 136 S_BRANCH %bb.1 137 138 bb.1: 139 successors: %bb.2 140 S_SETREG_IMM32_B32 0, 1 141 %sgpr1 = S_GETREG_B32 1 142 S_BRANCH %bb.2 143 144 bb.2: 145 successors: %bb.3 146 S_SETREG_B32 %sgpr0, 1 147 %sgpr1 = S_MOV_B32 0 148 %sgpr2 = S_GETREG_B32 1 149 S_BRANCH %bb.3 150 151 bb.3: 152 S_SETREG_B32 %sgpr0, 0 153 %sgpr1 = S_GETREG_B32 1 154 S_ENDPGM 155... 156 157... 158--- 159# GCN-LABEL: name: s_setreg 160 161# GCN-LABEL: bb.0: 162# GCN: S_SETREG 163# GCN: S_NOP 0 164# VI: S_NOP 0 165# GCN-NEXT: S_SETREG 166 167# GCN-LABEL: bb.1: 168# GCN: S_SETREG 169# GCN: S_NOP 0 170# VI: S_NOP 0 171# GCN-NEXT: S_SETREG 172 173# GCN-LABEL: bb.2: 174# GCN: S_SETREG 175# GCN-NEXT: S_SETREG 176 177name: s_setreg 178 179body: | 180 bb.0: 181 successors: %bb.1 182 S_SETREG_B32 %sgpr0, 1 183 S_SETREG_B32 %sgpr1, 1 184 S_BRANCH %bb.1 185 186 bb.1: 187 successors: %bb.2 188 S_SETREG_B32 %sgpr0, 64 189 S_SETREG_B32 %sgpr1, 128 190 S_BRANCH %bb.2 191 192 bb.2: 193 S_SETREG_B32 %sgpr0, 1 194 S_SETREG_B32 %sgpr1, 0 195 S_ENDPGM 196... 197 198... 199--- 200# GCN-LABEL: name: vmem_gt_8dw_store 201 202# GCN-LABEL: bb.0: 203# GCN: BUFFER_STORE_DWORD_OFFSET 204# GCN-NEXT: V_MOV_B32 205# GCN: BUFFER_STORE_DWORDX3_OFFSET 206# CIVI: S_NOP 207# GCN-NEXT: V_MOV_B32 208# GCN: BUFFER_STORE_DWORDX4_OFFSET 209# GCN-NEXT: V_MOV_B32 210# GCN: BUFFER_STORE_DWORDX4_OFFSET 211# CIVI: S_NOP 212# GCN-NEXT: V_MOV_B32 213# GCN: BUFFER_STORE_FORMAT_XYZ_OFFSET 214# CIVI: S_NOP 215# GCN-NEXT: V_MOV_B32 216# GCN: BUFFER_STORE_FORMAT_XYZW_OFFSET 217# CIVI: S_NOP 218# GCN-NEXT: V_MOV_B32 219 220# GCN-LABEL: bb.1: 221# GCN: FLAT_STORE_DWORDX2 222# GCN-NEXT: V_MOV_B32 223# GCN: FLAT_STORE_DWORDX3 224# CIVI: S_NOP 225# GCN-NEXT: V_MOV_B32 226# GCN: FLAT_STORE_DWORDX4 227# CIVI: S_NOP 228# GCN-NEXT: V_MOV_B32 229# GCN: FLAT_ATOMIC_CMPSWAP_X2 230# CIVI: S_NOP 231# GCN-NEXT: V_MOV_B32 232# GCN: FLAT_ATOMIC_FCMPSWAP_X2 233# CIVI: S_NOP 234# GCN: V_MOV_B32 235 236name: vmem_gt_8dw_store 237 238body: | 239 bb.0: 240 successors: %bb.1 241 BUFFER_STORE_DWORD_OFFSET %vgpr3, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, 0, 0, implicit %exec 242 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 243 BUFFER_STORE_DWORDX3_OFFSET %vgpr2_vgpr3_vgpr4, %sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit %exec 244 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 245 BUFFER_STORE_DWORDX4_OFFSET %vgpr2_vgpr3_vgpr4_vgpr5, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, 0, 0, implicit %exec 246 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 247 BUFFER_STORE_DWORDX4_OFFSET %vgpr2_vgpr3_vgpr4_vgpr5, %sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit %exec 248 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 249 BUFFER_STORE_FORMAT_XYZ_OFFSET %vgpr2_vgpr3_vgpr4, %sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit %exec 250 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 251 BUFFER_STORE_FORMAT_XYZW_OFFSET %vgpr2_vgpr3_vgpr4_vgpr5, %sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit %exec 252 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 253 BUFFER_ATOMIC_CMPSWAP_X2_OFFSET %vgpr2_vgpr3_vgpr4_vgpr5, %sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, implicit %exec 254 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 255 S_BRANCH %bb.1 256 257 bb.1: 258 FLAT_STORE_DWORDX2 %vgpr0_vgpr1, %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr 259 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 260 FLAT_STORE_DWORDX3 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4, 0, 0, 0, implicit %exec, implicit %flat_scr 261 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 262 FLAT_STORE_DWORDX4 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr 263 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 264 FLAT_ATOMIC_CMPSWAP_X2 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, implicit %exec, implicit %flat_scr 265 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 266 FLAT_ATOMIC_FCMPSWAP_X2 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, implicit %exec, implicit %flat_scr 267 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 268 S_ENDPGM 269 270... 271 272... 273--- 274 275# GCN-LABEL: name: readwrite_lane 276 277# GCN-LABEL: bb.0: 278# GCN: V_ADD_I32 279# GCN: S_NOP 280# GCN: S_NOP 281# GCN: S_NOP 282# GCN: S_NOP 283# GCN: V_READLANE_B32 284 285# GCN-LABEL: bb.1: 286# GCN: V_ADD_I32 287# GCN: S_NOP 288# GCN: S_NOP 289# GCN: S_NOP 290# GCN: S_NOP 291# GCN: V_WRITELANE_B32 292 293# GCN-LABEL: bb.2: 294# GCN: V_ADD_I32 295# GCN: S_NOP 296# GCN: S_NOP 297# GCN: S_NOP 298# GCN: S_NOP 299# GCN: V_READLANE_B32 300 301# GCN-LABEL: bb.3: 302# GCN: V_ADD_I32 303# GCN: S_NOP 304# GCN: S_NOP 305# GCN: S_NOP 306# GCN: S_NOP 307# GCN: V_WRITELANE_B32 308 309name: readwrite_lane 310 311body: | 312 bb.0: 313 successors: %bb.1 314 %vgpr0,%sgpr0_sgpr1 = V_ADD_I32_e64 %vgpr1, %vgpr2, implicit %vcc, implicit %exec 315 %sgpr4 = V_READLANE_B32 %vgpr4, %sgpr0 316 S_BRANCH %bb.1 317 318 bb.1: 319 successors: %bb.2 320 %vgpr0,%sgpr0_sgpr1 = V_ADD_I32_e64 %vgpr1, %vgpr2, implicit %vcc, implicit %exec 321 %vgpr4 = V_WRITELANE_B32 %sgpr0, %sgpr0 322 S_BRANCH %bb.2 323 324 bb.2: 325 successors: %bb.3 326 %vgpr0,implicit %vcc = V_ADD_I32_e32 %vgpr1, %vgpr2, implicit %vcc, implicit %exec 327 %sgpr4 = V_READLANE_B32 %vgpr4, %vcc_lo 328 S_BRANCH %bb.3 329 330 bb.3: 331 %vgpr0,implicit %vcc = V_ADD_I32_e32 %vgpr1, %vgpr2, implicit %vcc, implicit %exec 332 %vgpr4 = V_WRITELANE_B32 %sgpr4, %vcc_lo 333 S_ENDPGM 334 335... 336 337... 338--- 339 340# GCN-LABEL: name: rfe 341 342# GCN-LABEL: bb.0: 343# GCN: S_SETREG 344# VI: S_NOP 345# GCN-NEXT: S_RFE_B64 346 347# GCN-LABEL: bb.1: 348# GCN: S_SETREG 349# GCN-NEXT: S_RFE_B64 350 351name: rfe 352 353body: | 354 bb.0: 355 successors: %bb.1 356 S_SETREG_B32 %sgpr0, 3 357 S_RFE_B64 %sgpr2_sgpr3 358 S_BRANCH %bb.1 359 360 bb.1: 361 S_SETREG_B32 %sgpr0, 0 362 S_RFE_B64 %sgpr2_sgpr3 363 S_ENDPGM 364 365... 366 367... 368--- 369 370# GCN-LABEL: name: s_mov_fed_b32 371 372# GCN-LABEL: bb.0: 373# GCN: S_MOV_FED_B32 374# GFX9: S_NOP 375# GCN-NEXT: S_MOV_B32 376 377# GCN-LABEL: bb.1: 378# GCN: S_MOV_FED_B32 379# GFX9: S_NOP 380# GCN-NEXT: V_MOV_B32 381name: s_mov_fed_b32 382 383body: | 384 bb.0: 385 successors: %bb.1 386 %sgpr0 = S_MOV_FED_B32 %sgpr0 387 %sgpr0 = S_MOV_B32 %sgpr0 388 S_BRANCH %bb.1 389 390 bb.1: 391 %sgpr0 = S_MOV_FED_B32 %sgpr0 392 %vgpr0 = V_MOV_B32_e32 %sgpr0, implicit %exec 393 S_ENDPGM 394 395... 396 397... 398--- 399 400# GCN-LABEL: name: s_movrel 401 402# GCN-LABEL: bb.0: 403# GCN: S_MOV_B32 404# GFX9: S_NOP 405# GCN-NEXT: S_MOVRELS_B32 406 407# GCN-LABEL: bb.1: 408# GCN: S_MOV_B32 409# GFX9: S_NOP 410# GCN-NEXT: S_MOVRELS_B64 411 412# GCN-LABEL: bb.2: 413# GCN: S_MOV_B32 414# GFX9: S_NOP 415# GCN-NEXT: S_MOVRELD_B32 416 417# GCN-LABEL: bb.3: 418# GCN: S_MOV_B32 419# GFX9: S_NOP 420# GCN-NEXT: S_MOVRELD_B64 421 422name: s_movrel 423 424body: | 425 bb.0: 426 successors: %bb.1 427 %m0 = S_MOV_B32 0 428 %sgpr0 = S_MOVRELS_B32 %sgpr0, implicit %m0 429 S_BRANCH %bb.1 430 431 bb.1: 432 successors: %bb.2 433 %m0 = S_MOV_B32 0 434 %sgpr0_sgpr1 = S_MOVRELS_B64 %sgpr0_sgpr1, implicit %m0 435 S_BRANCH %bb.2 436 437 bb.2: 438 successors: %bb.3 439 %m0 = S_MOV_B32 0 440 %sgpr0 = S_MOVRELD_B32 %sgpr0, implicit %m0 441 S_BRANCH %bb.3 442 443 bb.3: 444 %m0 = S_MOV_B32 0 445 %sgpr0_sgpr1 = S_MOVRELD_B64 %sgpr0_sgpr1, implicit %m0 446 S_ENDPGM 447... 448 449... 450--- 451 452# GCN-LABEL: name: v_interp 453 454# GCN-LABEL: bb.0: 455# GCN: S_MOV_B32 456# GFX9: S_NOP 457# GCN-NEXT: V_INTERP_P1_F32 458 459# GCN-LABEL: bb.1: 460# GCN: S_MOV_B32 461# GFX9: S_NOP 462# GCN-NEXT: V_INTERP_P2_F32 463 464# GCN-LABEL: bb.2: 465# GCN: S_MOV_B32 466# GFX9: S_NOP 467# GCN-NEXT: V_INTERP_P1_F32_16bank 468 469# GCN-LABEL: bb.3: 470# GCN: S_MOV_B32 471# GFX9: S_NOP 472# GCN-NEXT: V_INTERP_MOV_F32 473 474name: v_interp 475 476body: | 477 bb.0: 478 successors: %bb.1 479 %m0 = S_MOV_B32 0 480 %vgpr0 = V_INTERP_P1_F32 %vgpr0, 0, 0, implicit %m0, implicit %exec 481 S_BRANCH %bb.1 482 483 bb.1: 484 successors: %bb.2 485 %m0 = S_MOV_B32 0 486 %vgpr0 = V_INTERP_P2_F32 %vgpr0, %vgpr1, 0, 0, implicit %m0, implicit %exec 487 S_BRANCH %bb.2 488 489 bb.2: 490 successors: %bb.3 491 %m0 = S_MOV_B32 0 492 %vgpr0 = V_INTERP_P1_F32_16bank %vgpr0, 0, 0, implicit %m0, implicit %exec 493 S_BRANCH %bb.3 494 495 bb.3: 496 %m0 = S_MOV_B32 0 497 %vgpr0 = V_INTERP_MOV_F32 0, 0, 0, implicit %m0, implicit %exec 498 S_ENDPGM 499... 500--- 501name: mov_fed_hazard_crash_on_dbg_value 502alignment: 0 503exposesReturnsTwice: false 504legalized: false 505regBankSelected: false 506selected: false 507tracksRegLiveness: true 508liveins: 509 - { reg: '%sgpr4_sgpr5' } 510 - { reg: '%sgpr6_sgpr7' } 511 - { reg: '%sgpr9' } 512 - { reg: '%sgpr0_sgpr1_sgpr2_sgpr3' } 513frameInfo: 514 isFrameAddressTaken: false 515 isReturnAddressTaken: false 516 hasStackMap: false 517 hasPatchPoint: false 518 stackSize: 16 519 offsetAdjustment: 0 520 maxAlignment: 8 521 adjustsStack: false 522 hasCalls: false 523 maxCallFrameSize: 0 524 hasOpaqueSPAdjustment: false 525 hasVAStart: false 526 hasMustTailInVarArgFunc: false 527stack: 528 - { id: 0, name: A.addr, offset: 0, size: 8, alignment: 8, local-offset: 0 } 529 - { id: 1, offset: 8, size: 4, alignment: 4 } 530body: | 531 bb.0.entry: 532 liveins: %sgpr4_sgpr5, %sgpr6_sgpr7, %sgpr9, %sgpr0_sgpr1_sgpr2_sgpr3 533 534 %flat_scr_lo = S_ADD_U32 %sgpr6, %sgpr9, implicit-def %scc 535 %flat_scr_hi = S_ADDC_U32 %sgpr7, 0, implicit-def %scc, implicit %scc 536 DBG_VALUE _, 2, !5, !11, debug-location !12 537 %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr4_sgpr5, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`) 538 dead %sgpr6_sgpr7 = KILL %sgpr4_sgpr5 539 %sgpr8 = S_MOV_B32 %sgpr5 540 %vgpr0 = V_MOV_B32_e32 killed %sgpr8, implicit %exec 541 BUFFER_STORE_DWORD_OFFSET %vgpr0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr9, 4, 0, 0, 0, implicit %exec :: (store 4 into %ir.A.addr + 4) 542 %sgpr8 = S_MOV_B32 %sgpr4, implicit killed %sgpr4_sgpr5 543 %vgpr0 = V_MOV_B32_e32 killed %sgpr8, implicit %exec 544 BUFFER_STORE_DWORD_OFFSET %vgpr0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr9, 0, 0, 0, 0, implicit %exec :: (store 4 into %ir.A.addr) 545 S_ENDPGM 546 547... 548