1# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass post-RA-hazard-rec %s -o - | FileCheck %s -check-prefixes=GCN 2# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass post-RA-hazard-rec %s -o - | FileCheck %s -check-prefixes=GCN,CIVI 3# RUN: llc -march=amdgcn -mcpu=fiji -run-pass post-RA-hazard-rec %s -o - | FileCheck %s -check-prefixes=GCN,CIVI,VI 4# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass post-RA-hazard-rec %s -o - | FileCheck %s -check-prefixes=GCN,CIVI,VI,GFX9 5 6--- | 7 define amdgpu_kernel void @div_fmas() { ret void } 8 define amdgpu_kernel void @s_getreg() { ret void } 9 define amdgpu_kernel void @s_setreg() { ret void } 10 define amdgpu_kernel void @vmem_gt_8dw_store() { ret void } 11 define amdgpu_kernel void @readwrite_lane() { ret void } 12 define amdgpu_kernel void @rfe() { ret void } 13 define amdgpu_kernel void @s_mov_fed_b32() { ret void } 14 define amdgpu_kernel void @s_movrel() { ret void } 15 define amdgpu_kernel void @v_interp() { ret void } 16 17 define amdgpu_kernel void @mov_fed_hazard_crash_on_dbg_value(i32 addrspace(1)* %A) { 18 entry: 19 %A.addr = alloca i32 addrspace(1)*, align 4 20 store i32 addrspace(1)* %A, i32 addrspace(1)** %A.addr, align 4 21 call void @llvm.dbg.declare(metadata i32 addrspace(1)** %A.addr, metadata !5, metadata !11), !dbg !12 22 ret void 23 } 24 25 declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 26 27 !llvm.dbg.cu = !{!0} 28 !llvm.module.flags = !{!3, !4} 29 30 !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.9.0 (trunk 268929)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) 31 !1 = !DIFile(filename: "test01.cl", directory: "/dev/null") 32 !2 = !{} 33 !3 = !{i32 2, !"Dwarf Version", i32 2} 34 !4 = !{i32 2, !"Debug Info Version", i32 3} 35 !5 = !DILocalVariable(name: "A", arg: 1, scope: !6, file: !1, line: 1, type: !9) 36 !6 = distinct !DISubprogram(name: "test", scope: !1, file: !1, line: 1, type: !7, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2) 37 !7 = !DISubroutineType(types: !8) 38 !8 = !{null, !9} 39 !9 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !10, size: 64, align: 32) 40 !10 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) 41 !11 = !DIExpression() 42 !12 = !DILocation(line: 1, column: 30, scope: !6) 43 44... 45--- 46# GCN-LABEL: name: div_fmas 47 48# GCN-LABEL: bb.0: 49# GCN: S_MOV_B64 50# GCN-NOT: S_NOP 51# GCN: V_DIV_FMAS 52 53# GCN-LABEL: bb.1: 54# GCN: V_CMP_EQ_I32 55# GCN: S_NOP 56# GCN: S_NOP 57# GCN: S_NOP 58# GCN: S_NOP 59# GCN: V_DIV_FMAS_F32 60 61# GCN-LABEL: bb.2: 62# GCN: V_CMP_EQ_I32 63# GCN: S_NOP 64# GCN: S_NOP 65# GCN: S_NOP 66# GCN: S_NOP 67# GCN: V_DIV_FMAS_F32 68 69# GCN-LABEL: bb.3: 70# GCN: V_DIV_SCALE_F32 71# GCN: S_NOP 72# GCN: S_NOP 73# GCN: S_NOP 74# GCN: S_NOP 75# GCN: V_DIV_FMAS_F32 76name: div_fmas 77 78body: | 79 bb.0: 80 %vcc = S_MOV_B64 0 81 %vgpr0 = V_DIV_FMAS_F32 0, %vgpr1, 0, %vgpr2, 0, %vgpr3, 0, 0, implicit %vcc, implicit %exec 82 S_BRANCH %bb.1 83 84 bb.1: 85 implicit %vcc = V_CMP_EQ_I32_e32 %vgpr1, %vgpr2, implicit %exec 86 %vgpr0 = V_DIV_FMAS_F32 0, %vgpr1, 0, %vgpr2, 0, %vgpr3, 0, 0, implicit %vcc, implicit %exec 87 S_BRANCH %bb.2 88 89 bb.2: 90 %vcc = V_CMP_EQ_I32_e64 %vgpr1, %vgpr2, implicit %exec 91 %vgpr0 = V_DIV_FMAS_F32 0, %vgpr1, 0, %vgpr2, 0, %vgpr3, 0, 0, implicit %vcc, implicit %exec 92 S_BRANCH %bb.3 93 94 bb.3: 95 %vgpr4, %vcc = V_DIV_SCALE_F32 %vgpr1, %vgpr1, %vgpr3, implicit %exec 96 %vgpr0 = V_DIV_FMAS_F32 0, %vgpr1, 0, %vgpr2, 0, %vgpr3, 0, 0, implicit %vcc, implicit %exec 97 S_ENDPGM 98 99... 100 101... 102--- 103# GCN-LABEL: name: s_getreg 104 105# GCN-LABEL: bb.0: 106# GCN: S_SETREG 107# GCN: S_NOP 0 108# GCN: S_NOP 0 109# GCN: S_GETREG 110 111# GCN-LABEL: bb.1: 112# GCN: S_SETREG_IMM32 113# GCN: S_NOP 0 114# GCN: S_NOP 0 115# GCN: S_GETREG 116 117# GCN-LABEL: bb.2: 118# GCN: S_SETREG 119# GCN: S_NOP 0 120# GCN: S_GETREG 121 122# GCN-LABEL: bb.3: 123# GCN: S_SETREG 124# GCN-NEXT: S_GETREG 125 126name: s_getreg 127 128body: | 129 bb.0: 130 S_SETREG_B32 %sgpr0, 1 131 %sgpr1 = S_GETREG_B32 1 132 S_BRANCH %bb.1 133 134 bb.1: 135 S_SETREG_IMM32_B32 0, 1 136 %sgpr1 = S_GETREG_B32 1 137 S_BRANCH %bb.2 138 139 bb.2: 140 S_SETREG_B32 %sgpr0, 1 141 %sgpr1 = S_MOV_B32 0 142 %sgpr2 = S_GETREG_B32 1 143 S_BRANCH %bb.3 144 145 bb.3: 146 S_SETREG_B32 %sgpr0, 0 147 %sgpr1 = S_GETREG_B32 1 148 S_ENDPGM 149... 150 151... 152--- 153# GCN-LABEL: name: s_setreg 154 155# GCN-LABEL: bb.0: 156# GCN: S_SETREG 157# GCN: S_NOP 0 158# VI: S_NOP 0 159# GCN-NEXT: S_SETREG 160 161# GCN-LABEL: bb.1: 162# GCN: S_SETREG 163# GCN: S_NOP 0 164# VI: S_NOP 0 165# GCN-NEXT: S_SETREG 166 167# GCN-LABEL: bb.2: 168# GCN: S_SETREG 169# GCN-NEXT: S_SETREG 170 171name: s_setreg 172 173body: | 174 bb.0: 175 S_SETREG_B32 %sgpr0, 1 176 S_SETREG_B32 %sgpr1, 1 177 S_BRANCH %bb.1 178 179 bb.1: 180 S_SETREG_B32 %sgpr0, 64 181 S_SETREG_B32 %sgpr1, 128 182 S_BRANCH %bb.2 183 184 bb.2: 185 S_SETREG_B32 %sgpr0, 1 186 S_SETREG_B32 %sgpr1, 0 187 S_ENDPGM 188... 189 190... 191--- 192# GCN-LABEL: name: vmem_gt_8dw_store 193 194# GCN-LABEL: bb.0: 195# GCN: BUFFER_STORE_DWORD_OFFSET 196# GCN-NEXT: V_MOV_B32 197# GCN: BUFFER_STORE_DWORDX3_OFFSET 198# CIVI: S_NOP 199# GCN-NEXT: V_MOV_B32 200# GCN: BUFFER_STORE_DWORDX4_OFFSET 201# GCN-NEXT: V_MOV_B32 202# GCN: BUFFER_STORE_DWORDX4_OFFSET 203# CIVI: S_NOP 204# GCN-NEXT: V_MOV_B32 205# GCN: BUFFER_STORE_FORMAT_XYZ_OFFSET 206# CIVI: S_NOP 207# GCN-NEXT: V_MOV_B32 208# GCN: BUFFER_STORE_FORMAT_XYZW_OFFSET 209# CIVI: S_NOP 210# GCN-NEXT: V_MOV_B32 211 212# GCN-LABEL: bb.1: 213# GCN: FLAT_STORE_DWORDX2 214# GCN-NEXT: V_MOV_B32 215# GCN: FLAT_STORE_DWORDX3 216# CIVI: S_NOP 217# GCN-NEXT: V_MOV_B32 218# GCN: FLAT_STORE_DWORDX4 219# CIVI: S_NOP 220# GCN-NEXT: V_MOV_B32 221# GCN: FLAT_ATOMIC_CMPSWAP_X2 222# CIVI: S_NOP 223# GCN-NEXT: V_MOV_B32 224# GCN: FLAT_ATOMIC_FCMPSWAP_X2 225# CIVI: S_NOP 226# GCN: V_MOV_B32 227 228name: vmem_gt_8dw_store 229 230body: | 231 bb.0: 232 BUFFER_STORE_DWORD_OFFSET %vgpr3, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, 0, 0, implicit %exec 233 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 234 BUFFER_STORE_DWORDX3_OFFSET %vgpr2_vgpr3_vgpr4, %sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit %exec 235 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 236 BUFFER_STORE_DWORDX4_OFFSET %vgpr2_vgpr3_vgpr4_vgpr5, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, 0, 0, implicit %exec 237 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 238 BUFFER_STORE_DWORDX4_OFFSET %vgpr2_vgpr3_vgpr4_vgpr5, %sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit %exec 239 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 240 BUFFER_STORE_FORMAT_XYZ_OFFSET %vgpr2_vgpr3_vgpr4, %sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit %exec 241 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 242 BUFFER_STORE_FORMAT_XYZW_OFFSET %vgpr2_vgpr3_vgpr4_vgpr5, %sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit %exec 243 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 244 BUFFER_ATOMIC_CMPSWAP_X2_OFFSET %vgpr2_vgpr3_vgpr4_vgpr5, %sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, implicit %exec 245 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 246 S_BRANCH %bb.1 247 248 bb.1: 249 FLAT_STORE_DWORDX2 %vgpr0_vgpr1, %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr 250 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 251 FLAT_STORE_DWORDX3 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4, 0, 0, 0, implicit %exec, implicit %flat_scr 252 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 253 FLAT_STORE_DWORDX4 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr 254 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 255 FLAT_ATOMIC_CMPSWAP_X2 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, implicit %exec, implicit %flat_scr 256 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 257 FLAT_ATOMIC_FCMPSWAP_X2 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, implicit %exec, implicit %flat_scr 258 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 259 S_ENDPGM 260 261... 262 263... 264--- 265 266# GCN-LABEL: name: readwrite_lane 267 268# GCN-LABEL: bb.0: 269# GCN: V_ADD_I32 270# GCN: S_NOP 271# GCN: S_NOP 272# GCN: S_NOP 273# GCN: S_NOP 274# GCN: V_READLANE_B32 275 276# GCN-LABEL: bb.1: 277# GCN: V_ADD_I32 278# GCN: S_NOP 279# GCN: S_NOP 280# GCN: S_NOP 281# GCN: S_NOP 282# GCN: V_WRITELANE_B32 283 284# GCN-LABEL: bb.2: 285# GCN: V_ADD_I32 286# GCN: S_NOP 287# GCN: S_NOP 288# GCN: S_NOP 289# GCN: S_NOP 290# GCN: V_READLANE_B32 291 292# GCN-LABEL: bb.3: 293# GCN: V_ADD_I32 294# GCN: S_NOP 295# GCN: S_NOP 296# GCN: S_NOP 297# GCN: S_NOP 298# GCN: V_WRITELANE_B32 299 300name: readwrite_lane 301 302body: | 303 bb.0: 304 %vgpr0,%sgpr0_sgpr1 = V_ADD_I32_e64 %vgpr1, %vgpr2, implicit %vcc, implicit %exec 305 %sgpr4 = V_READLANE_B32 %vgpr4, %sgpr0 306 S_BRANCH %bb.1 307 308 bb.1: 309 %vgpr0,%sgpr0_sgpr1 = V_ADD_I32_e64 %vgpr1, %vgpr2, implicit %vcc, implicit %exec 310 %vgpr4 = V_WRITELANE_B32 %sgpr0, %sgpr0 311 S_BRANCH %bb.2 312 313 bb.2: 314 %vgpr0,implicit %vcc = V_ADD_I32_e32 %vgpr1, %vgpr2, implicit %vcc, implicit %exec 315 %sgpr4 = V_READLANE_B32 %vgpr4, %vcc_lo 316 S_BRANCH %bb.3 317 318 bb.3: 319 %vgpr0,implicit %vcc = V_ADD_I32_e32 %vgpr1, %vgpr2, implicit %vcc, implicit %exec 320 %vgpr4 = V_WRITELANE_B32 %sgpr4, %vcc_lo 321 S_ENDPGM 322 323... 324 325... 326--- 327 328# GCN-LABEL: name: rfe 329 330# GCN-LABEL: bb.0: 331# GCN: S_SETREG 332# VI: S_NOP 333# GCN-NEXT: S_RFE_B64 334 335# GCN-LABEL: bb.1: 336# GCN: S_SETREG 337# GCN-NEXT: S_RFE_B64 338 339name: rfe 340 341body: | 342 bb.0: 343 S_SETREG_B32 %sgpr0, 3 344 S_RFE_B64 %sgpr2_sgpr3 345 S_BRANCH %bb.1 346 347 bb.1: 348 S_SETREG_B32 %sgpr0, 0 349 S_RFE_B64 %sgpr2_sgpr3 350 S_ENDPGM 351 352... 353 354... 355--- 356 357# GCN-LABEL: name: s_mov_fed_b32 358 359# GCN-LABEL: bb.0: 360# GCN: S_MOV_FED_B32 361# GFX9: S_NOP 362# GCN-NEXT: S_MOV_B32 363 364# GCN-LABEL: bb.1: 365# GCN: S_MOV_FED_B32 366# GFX9: S_NOP 367# GCN-NEXT: V_MOV_B32 368name: s_mov_fed_b32 369 370body: | 371 bb.0: 372 %sgpr0 = S_MOV_FED_B32 %sgpr0 373 %sgpr0 = S_MOV_B32 %sgpr0 374 S_BRANCH %bb.1 375 376 bb.1: 377 %sgpr0 = S_MOV_FED_B32 %sgpr0 378 %vgpr0 = V_MOV_B32_e32 %sgpr0, implicit %exec 379 S_ENDPGM 380 381... 382 383... 384--- 385 386# GCN-LABEL: name: s_movrel 387 388# GCN-LABEL: bb.0: 389# GCN: S_MOV_B32 390# GFX9: S_NOP 391# GCN-NEXT: S_MOVRELS_B32 392 393# GCN-LABEL: bb.1: 394# GCN: S_MOV_B32 395# GFX9: S_NOP 396# GCN-NEXT: S_MOVRELS_B64 397 398# GCN-LABEL: bb.2: 399# GCN: S_MOV_B32 400# GFX9: S_NOP 401# GCN-NEXT: S_MOVRELD_B32 402 403# GCN-LABEL: bb.3: 404# GCN: S_MOV_B32 405# GFX9: S_NOP 406# GCN-NEXT: S_MOVRELD_B64 407 408name: s_movrel 409 410body: | 411 bb.0: 412 %m0 = S_MOV_B32 0 413 %sgpr0 = S_MOVRELS_B32 %sgpr0, implicit %m0 414 S_BRANCH %bb.1 415 416 bb.1: 417 %m0 = S_MOV_B32 0 418 %sgpr0_sgpr1 = S_MOVRELS_B64 %sgpr0_sgpr1, implicit %m0 419 S_BRANCH %bb.2 420 421 bb.2: 422 %m0 = S_MOV_B32 0 423 %sgpr0 = S_MOVRELD_B32 %sgpr0, implicit %m0 424 S_BRANCH %bb.3 425 426 bb.3: 427 %m0 = S_MOV_B32 0 428 %sgpr0_sgpr1 = S_MOVRELD_B64 %sgpr0_sgpr1, implicit %m0 429 S_ENDPGM 430... 431 432... 433--- 434 435# GCN-LABEL: name: v_interp 436 437# GCN-LABEL: bb.0: 438# GCN: S_MOV_B32 439# GFX9: S_NOP 440# GCN-NEXT: V_INTERP_P1_F32 441 442# GCN-LABEL: bb.1: 443# GCN: S_MOV_B32 444# GFX9: S_NOP 445# GCN-NEXT: V_INTERP_P2_F32 446 447# GCN-LABEL: bb.2: 448# GCN: S_MOV_B32 449# GFX9: S_NOP 450# GCN-NEXT: V_INTERP_P1_F32_16bank 451 452# GCN-LABEL: bb.3: 453# GCN: S_MOV_B32 454# GFX9: S_NOP 455# GCN-NEXT: V_INTERP_MOV_F32 456 457name: v_interp 458 459body: | 460 bb.0: 461 %m0 = S_MOV_B32 0 462 %vgpr0 = V_INTERP_P1_F32 %vgpr0, 0, 0, implicit %m0, implicit %exec 463 S_BRANCH %bb.1 464 465 bb.1: 466 %m0 = S_MOV_B32 0 467 %vgpr0 = V_INTERP_P2_F32 %vgpr0, %vgpr1, 0, 0, implicit %m0, implicit %exec 468 S_BRANCH %bb.2 469 470 bb.2: 471 %m0 = S_MOV_B32 0 472 %vgpr0 = V_INTERP_P1_F32_16bank %vgpr0, 0, 0, implicit %m0, implicit %exec 473 S_BRANCH %bb.3 474 475 bb.3: 476 %m0 = S_MOV_B32 0 477 %vgpr0 = V_INTERP_MOV_F32 0, 0, 0, implicit %m0, implicit %exec 478 S_ENDPGM 479... 480--- 481name: mov_fed_hazard_crash_on_dbg_value 482alignment: 0 483exposesReturnsTwice: false 484legalized: false 485regBankSelected: false 486selected: false 487tracksRegLiveness: true 488liveins: 489 - { reg: '%sgpr4_sgpr5' } 490 - { reg: '%sgpr6_sgpr7' } 491 - { reg: '%sgpr9' } 492 - { reg: '%sgpr0_sgpr1_sgpr2_sgpr3' } 493frameInfo: 494 isFrameAddressTaken: false 495 isReturnAddressTaken: false 496 hasStackMap: false 497 hasPatchPoint: false 498 stackSize: 16 499 offsetAdjustment: 0 500 maxAlignment: 8 501 adjustsStack: false 502 hasCalls: false 503 maxCallFrameSize: 0 504 hasOpaqueSPAdjustment: false 505 hasVAStart: false 506 hasMustTailInVarArgFunc: false 507stack: 508 - { id: 0, name: A.addr, offset: 0, size: 8, alignment: 8, local-offset: 0 } 509 - { id: 1, offset: 8, size: 4, alignment: 4 } 510body: | 511 bb.0.entry: 512 liveins: %sgpr4_sgpr5, %sgpr6_sgpr7, %sgpr9, %sgpr0_sgpr1_sgpr2_sgpr3 513 514 %flat_scr_lo = S_ADD_U32 %sgpr6, %sgpr9, implicit-def %scc 515 %flat_scr_hi = S_ADDC_U32 %sgpr7, 0, implicit-def %scc, implicit %scc 516 DBG_VALUE _, 2, !5, !11, debug-location !12 517 %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr4_sgpr5, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`) 518 dead %sgpr6_sgpr7 = KILL %sgpr4_sgpr5 519 %sgpr8 = S_MOV_B32 %sgpr5 520 %vgpr0 = V_MOV_B32_e32 killed %sgpr8, implicit %exec 521 BUFFER_STORE_DWORD_OFFSET %vgpr0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr9, 4, 0, 0, 0, implicit %exec :: (store 4 into %ir.A.addr + 4) 522 %sgpr8 = S_MOV_B32 %sgpr4, implicit killed %sgpr4_sgpr5 523 %vgpr0 = V_MOV_B32_e32 killed %sgpr8, implicit %exec 524 BUFFER_STORE_DWORD_OFFSET %vgpr0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr9, 0, 0, 0, 0, implicit %exec :: (store 4 into %ir.A.addr) 525 S_ENDPGM 526 527... 528