1# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass post-RA-hazard-rec %s -o - | FileCheck %s -check-prefixes=GCN 2# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass post-RA-hazard-rec %s -o - | FileCheck %s -check-prefixes=GCN,CIVI 3# RUN: llc -march=amdgcn -mcpu=fiji -run-pass post-RA-hazard-rec %s -o - | FileCheck %s -check-prefixes=GCN,CIVI,VI 4# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass post-RA-hazard-rec %s -o - | FileCheck %s -check-prefixes=GCN,CIVI,VI,GFX9 5 6--- | 7 define amdgpu_kernel void @div_fmas() { ret void } 8 define amdgpu_kernel void @s_getreg() { ret void } 9 define amdgpu_kernel void @s_setreg() { ret void } 10 define amdgpu_kernel void @vmem_gt_8dw_store() { ret void } 11 define amdgpu_kernel void @readwrite_lane() { ret void } 12 define amdgpu_kernel void @rfe() { ret void } 13 define amdgpu_kernel void @s_movrel() { ret void } 14 define amdgpu_kernel void @v_interp() { ret void } 15 define amdgpu_kernel void @dpp() { ret void } 16... 17--- 18# GCN-LABEL: name: div_fmas 19 20# GCN-LABEL: bb.0: 21# GCN: S_MOV_B64 22# GCN-NOT: S_NOP 23# GCN: V_DIV_FMAS 24 25# GCN-LABEL: bb.1: 26# GCN: V_CMP_EQ_I32 27# GCN: S_NOP 28# GCN: S_NOP 29# GCN: S_NOP 30# GCN: S_NOP 31# GCN: V_DIV_FMAS_F32 32 33# GCN-LABEL: bb.2: 34# GCN: V_CMP_EQ_I32 35# GCN: S_NOP 36# GCN: S_NOP 37# GCN: S_NOP 38# GCN: S_NOP 39# GCN: V_DIV_FMAS_F32 40 41# GCN-LABEL: bb.3: 42# GCN: V_DIV_SCALE_F32 43# GCN: S_NOP 44# GCN: S_NOP 45# GCN: S_NOP 46# GCN: S_NOP 47# GCN: V_DIV_FMAS_F32 48name: div_fmas 49 50body: | 51 bb.0: 52 $vcc = S_MOV_B64 0 53 $vgpr0 = V_DIV_FMAS_F32 0, $vgpr1, 0, $vgpr2, 0, $vgpr3, 0, 0, implicit $mode, implicit $vcc, implicit $exec 54 S_BRANCH %bb.1 55 56 bb.1: 57 implicit $vcc = V_CMP_EQ_I32_e32 $vgpr1, $vgpr2, implicit $exec 58 $vgpr0 = V_DIV_FMAS_F32 0, $vgpr1, 0, $vgpr2, 0, $vgpr3, 0, 0, implicit $mode, implicit $vcc, implicit $exec 59 S_BRANCH %bb.2 60 61 bb.2: 62 $vcc = V_CMP_EQ_I32_e64 $vgpr1, $vgpr2, implicit $exec 63 $vgpr0 = V_DIV_FMAS_F32 0, $vgpr1, 0, $vgpr2, 0, $vgpr3, 0, 0, implicit $mode, implicit $vcc, implicit $exec 64 S_BRANCH %bb.3 65 66 bb.3: 67 $vgpr4, $vcc = V_DIV_SCALE_F32 $vgpr1, $vgpr1, $vgpr3, implicit $mode, implicit $exec 68 $vgpr0 = V_DIV_FMAS_F32 0, $vgpr1, 0, $vgpr2, 0, $vgpr3, 0, 0, implicit $mode, implicit $vcc, implicit $exec 69 S_ENDPGM 0 70 71... 72 73... 74--- 75# GCN-LABEL: name: s_getreg 76 77# GCN-LABEL: bb.0: 78# GCN: S_SETREG 79# GCN: S_NOP 0 80# GCN: S_NOP 0 81# GCN: S_GETREG 82 83# GCN-LABEL: bb.1: 84# GCN: S_SETREG_IMM32 85# GCN: S_NOP 0 86# GCN: S_NOP 0 87# GCN: S_GETREG 88 89# GCN-LABEL: bb.2: 90# GCN: S_SETREG 91# GCN: S_NOP 0 92# GCN: S_GETREG 93 94# GCN-LABEL: bb.3: 95# GCN: S_SETREG 96# GCN-NEXT: S_GETREG 97 98name: s_getreg 99 100body: | 101 bb.0: 102 S_SETREG_B32 $sgpr0, 1, implicit-def $mode, implicit $mode 103 $sgpr1 = S_GETREG_B32 1, implicit-def $mode, implicit $mode 104 S_BRANCH %bb.1 105 106 bb.1: 107 S_SETREG_IMM32_B32 0, 1, implicit-def $mode, implicit $mode 108 $sgpr1 = S_GETREG_B32 1, implicit-def $mode, implicit $mode 109 S_BRANCH %bb.2 110 111 bb.2: 112 S_SETREG_B32 $sgpr0, 1, implicit-def $mode, implicit $mode 113 $sgpr1 = S_MOV_B32 0 114 $sgpr2 = S_GETREG_B32 1, implicit-def $mode, implicit $mode 115 S_BRANCH %bb.3 116 117 bb.3: 118 S_SETREG_B32 $sgpr0, 0, implicit-def $mode, implicit $mode 119 $sgpr1 = S_GETREG_B32 1, implicit-def $mode, implicit $mode 120 S_ENDPGM 0 121... 122 123... 124--- 125# GCN-LABEL: name: s_setreg 126 127# GCN-LABEL: bb.0: 128# GCN: S_SETREG 129# GCN: S_NOP 0 130# VI: S_NOP 0 131# GCN-NEXT: S_SETREG 132 133# GCN-LABEL: bb.1: 134# GCN: S_SETREG 135# GCN: S_NOP 0 136# VI: S_NOP 0 137# GCN-NEXT: S_SETREG 138 139# GCN-LABEL: bb.2: 140# GCN: S_SETREG 141# GCN-NEXT: S_SETREG 142 143name: s_setreg 144 145body: | 146 bb.0: 147 S_SETREG_B32 $sgpr0, 1, implicit-def $mode, implicit $mode 148 S_SETREG_B32 $sgpr1, 1, implicit-def $mode, implicit $mode 149 S_BRANCH %bb.1 150 151 bb.1: 152 S_SETREG_B32 $sgpr0, 64, implicit-def $mode, implicit $mode 153 S_SETREG_B32 $sgpr1, 128, implicit-def $mode, implicit $mode 154 S_BRANCH %bb.2 155 156 bb.2: 157 S_SETREG_B32 $sgpr0, 1, implicit-def $mode, implicit $mode 158 S_SETREG_B32 $sgpr1, 0, implicit-def $mode, implicit $mode 159 S_ENDPGM 0 160... 161 162... 163--- 164# GCN-LABEL: name: vmem_gt_8dw_store 165 166# GCN-LABEL: bb.0: 167# GCN: BUFFER_STORE_DWORD_OFFSET 168# GCN-NEXT: V_MOV_B32 169# GCN: BUFFER_STORE_DWORDX3_OFFSET 170# CIVI: S_NOP 171# GCN-NEXT: V_MOV_B32 172# GCN: BUFFER_STORE_DWORDX4_OFFSET 173# GCN-NEXT: V_MOV_B32 174# GCN: BUFFER_STORE_DWORDX4_OFFSET 175# CIVI: S_NOP 176# GCN-NEXT: V_MOV_B32 177# GCN: BUFFER_STORE_FORMAT_XYZ_OFFSET 178# CIVI: S_NOP 179# GCN-NEXT: V_MOV_B32 180# GCN: BUFFER_STORE_FORMAT_XYZW_OFFSET 181# CIVI: S_NOP 182# GCN-NEXT: V_MOV_B32 183 184# GCN-LABEL: bb.1: 185# GCN: FLAT_STORE_DWORDX2 186# GCN-NEXT: V_MOV_B32 187# GCN: FLAT_STORE_DWORDX3 188# CIVI: S_NOP 189# GCN-NEXT: V_MOV_B32 190# GCN: FLAT_STORE_DWORDX4 191# CIVI: S_NOP 192# GCN-NEXT: V_MOV_B32 193# GCN: FLAT_ATOMIC_CMPSWAP_X2 194# CIVI: S_NOP 195# GCN-NEXT: V_MOV_B32 196# GCN: FLAT_ATOMIC_FCMPSWAP_X2 197# CIVI: S_NOP 198# GCN: V_MOV_B32 199 200name: vmem_gt_8dw_store 201 202body: | 203 bb.0: 204 BUFFER_STORE_DWORD_OFFSET $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, 0, implicit $exec 205 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 206 BUFFER_STORE_DWORDX3_OFFSET $vgpr2_vgpr3_vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, 0, implicit $exec 207 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 208 BUFFER_STORE_DWORDX4_OFFSET $vgpr2_vgpr3_vgpr4_vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, 0, implicit $exec 209 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 210 BUFFER_STORE_DWORDX4_OFFSET $vgpr2_vgpr3_vgpr4_vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, 0, implicit $exec 211 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 212 BUFFER_STORE_FORMAT_XYZ_OFFSET $vgpr2_vgpr3_vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, 0, implicit $exec 213 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 214 BUFFER_STORE_FORMAT_XYZW_OFFSET $vgpr2_vgpr3_vgpr4_vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, 0, implicit $exec 215 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 216 BUFFER_ATOMIC_CMPSWAP_X2_OFFSET $vgpr2_vgpr3_vgpr4_vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, implicit $exec 217 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 218 S_BRANCH %bb.1 219 220 bb.1: 221 FLAT_STORE_DWORDX2 $vgpr0_vgpr1, $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr 222 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 223 FLAT_STORE_DWORDX3 $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4, 0, 0, 0, 0, implicit $exec, implicit $flat_scr 224 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 225 FLAT_STORE_DWORDX4 $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr 226 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 227 FLAT_ATOMIC_CMPSWAP_X2 $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, implicit $exec, implicit $flat_scr 228 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 229 FLAT_ATOMIC_FCMPSWAP_X2 $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, implicit $exec, implicit $flat_scr 230 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 231 S_ENDPGM 0 232 233... 234 235... 236--- 237 238# GCN-LABEL: name: readwrite_lane 239 240# GCN-LABEL: bb.0: 241# GCN: V_ADD_CO_U32 242# GCN: S_NOP 243# GCN: S_NOP 244# GCN: S_NOP 245# GCN: S_NOP 246# GCN: V_READLANE_B32 247 248# GCN-LABEL: bb.1: 249# GCN: V_ADD_CO_U32 250# GCN: S_NOP 251# GCN: S_NOP 252# GCN: S_NOP 253# GCN: S_NOP 254# GCN: V_WRITELANE_B32 255 256# GCN-LABEL: bb.2: 257# GCN: V_ADD_CO_U32 258# GCN: S_NOP 259# GCN: S_NOP 260# GCN: S_NOP 261# GCN: S_NOP 262# GCN: V_READLANE_B32 263 264# GCN-LABEL: bb.3: 265# GCN: V_ADD_CO_U32 266# GCN: S_NOP 267# GCN: S_NOP 268# GCN: S_NOP 269# GCN: S_NOP 270# GCN: V_WRITELANE_B32 271 272name: readwrite_lane 273 274body: | 275 bb.0: 276 $vgpr0,$sgpr0_sgpr1 = V_ADD_CO_U32_e64 $vgpr1, $vgpr2, implicit $vcc, 0, implicit $exec 277 $sgpr4 = V_READLANE_B32 $vgpr4, $sgpr0 278 S_BRANCH %bb.1 279 280 bb.1: 281 $vgpr0,$sgpr0_sgpr1 = V_ADD_CO_U32_e64 $vgpr1, $vgpr2, implicit $vcc, 0, implicit $exec 282 $vgpr4 = V_WRITELANE_B32 $sgpr0, $sgpr0, $vgpr4 283 S_BRANCH %bb.2 284 285 bb.2: 286 $vgpr0,implicit $vcc = V_ADD_CO_U32_e32 $vgpr1, $vgpr2, implicit $vcc, implicit $exec 287 $sgpr4 = V_READLANE_B32 $vgpr4, $vcc_lo 288 S_BRANCH %bb.3 289 290 bb.3: 291 $m0 = S_MOV_B32 $sgpr4 292 $vgpr0,implicit $vcc = V_ADD_CO_U32_e32 $vgpr1, $vgpr2, implicit $vcc, implicit $exec 293 $vgpr4 = V_WRITELANE_B32 $m0, $vcc_lo, $vgpr4 294 S_ENDPGM 0 295 296... 297 298... 299--- 300 301# GCN-LABEL: name: rfe 302 303# GCN-LABEL: bb.0: 304# GCN: S_SETREG 305# VI: S_NOP 306# GCN-NEXT: S_RFE_B64 307 308# GCN-LABEL: bb.1: 309# GCN: S_SETREG 310# GCN-NEXT: S_RFE_B64 311 312name: rfe 313 314body: | 315 bb.0: 316 S_SETREG_B32 $sgpr0, 3, implicit-def $mode, implicit $mode 317 S_RFE_B64 $sgpr2_sgpr3 318 S_BRANCH %bb.1 319 320 bb.1: 321 S_SETREG_B32 $sgpr0, 0, implicit-def $mode, implicit $mode 322 S_RFE_B64 $sgpr2_sgpr3 323 S_ENDPGM 0 324 325... 326 327... 328--- 329 330# GCN-LABEL: name: s_movrel 331 332# GCN-LABEL: bb.0: 333# GCN: S_MOV_B32 334# GFX9: S_NOP 335# GCN-NEXT: S_MOVRELS_B32 336 337# GCN-LABEL: bb.1: 338# GCN: S_MOV_B32 339# GFX9: S_NOP 340# GCN-NEXT: S_MOVRELS_B64 341 342# GCN-LABEL: bb.2: 343# GCN: S_MOV_B32 344# GFX9: S_NOP 345# GCN-NEXT: S_MOVRELD_B32 346 347# GCN-LABEL: bb.3: 348# GCN: S_MOV_B32 349# GFX9: S_NOP 350# GCN-NEXT: S_MOVRELD_B64 351 352name: s_movrel 353 354body: | 355 bb.0: 356 $m0 = S_MOV_B32 0 357 $sgpr0 = S_MOVRELS_B32 $sgpr0, implicit $m0 358 S_BRANCH %bb.1 359 360 bb.1: 361 $m0 = S_MOV_B32 0 362 $sgpr0_sgpr1 = S_MOVRELS_B64 $sgpr0_sgpr1, implicit $m0 363 S_BRANCH %bb.2 364 365 bb.2: 366 $m0 = S_MOV_B32 0 367 S_MOVRELD_B32 $sgpr0, $sgpr0, implicit $m0 368 S_BRANCH %bb.3 369 370 bb.3: 371 $m0 = S_MOV_B32 0 372 S_MOVRELD_B64 $sgpr0_sgpr1, $sgpr0_sgpr1, implicit $m0 373 S_ENDPGM 0 374... 375 376... 377--- 378 379# GCN-LABEL: name: v_interp 380 381# GCN-LABEL: bb.0: 382# GCN: S_MOV_B32 383# GFX9-NEXT: S_NOP 384# GCN-NEXT: V_INTERP_P1_F32 385 386# GCN-LABEL: bb.1: 387# GCN: S_MOV_B32 388# GFX9-NEXT: S_NOP 389# GCN-NEXT: V_INTERP_P2_F32 390 391# GCN-LABEL: bb.2: 392# GCN: S_MOV_B32 393# GFX9-NEXT: S_NOP 394# GCN-NEXT: V_INTERP_P1_F32_16bank 395 396# GCN-LABEL: bb.3: 397# GCN: S_MOV_B32 398# GFX9-NEXT: S_NOP 399# GCN-NEXT: V_INTERP_MOV_F32 400 401name: v_interp 402 403body: | 404 bb.0: 405 $m0 = S_MOV_B32 0 406 $vgpr0 = V_INTERP_P1_F32 $vgpr0, 0, 0, implicit $mode, implicit $m0, implicit $exec 407 S_BRANCH %bb.1 408 409 bb.1: 410 $m0 = S_MOV_B32 0 411 $vgpr0 = V_INTERP_P2_F32 $vgpr0, $vgpr1, 0, 0, implicit $mode, implicit $m0, implicit $exec 412 S_BRANCH %bb.2 413 414 bb.2: 415 $m0 = S_MOV_B32 0 416 $vgpr0 = V_INTERP_P1_F32_16bank $vgpr0, 0, 0, implicit $mode, implicit $m0, implicit $exec 417 S_BRANCH %bb.3 418 419 bb.3: 420 $m0 = S_MOV_B32 0 421 $vgpr0 = V_INTERP_MOV_F32 0, 0, 0, implicit $mode, implicit $m0, implicit $exec 422 S_ENDPGM 0 423... 424 425... 426--- 427 428# GCN-LABEL: name: dpp 429 430# VI-LABEL: bb.0: 431# VI: V_MOV_B32_e32 432# VI-NEXT: S_NOP 0 433# VI-NEXT: S_NOP 0 434# VI-NEXT: V_MOV_B32_dpp 435 436# VI-LABEL: bb.1: 437# VI: V_CMPX_EQ_I32_e32 438# VI-NEXT: S_NOP 0 439# VI-NEXT: S_NOP 0 440# VI-NEXT: S_NOP 0 441# VI-NEXT: S_NOP 0 442# VI-NEXT: S_NOP 0 443# VI-NEXT: V_MOV_B32_dpp 444 445name: dpp 446 447body: | 448 bb.0: 449 $vgpr0 = V_MOV_B32_e32 0, implicit $exec 450 $vgpr1 = V_MOV_B32_dpp $vgpr1, $vgpr0, 0, 15, 15, 0, implicit $exec 451 S_BRANCH %bb.1 452 453 bb.1: 454 implicit $exec, implicit $vcc = V_CMPX_EQ_I32_e32 $vgpr0, $vgpr1, implicit $exec 455 $vgpr3 = V_MOV_B32_dpp $vgpr3, $vgpr0, 0, 15, 15, 0, implicit $exec 456 S_ENDPGM 0 457... 458