1# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass post-RA-hazard-rec %s -o - | FileCheck %s -check-prefixes=GCN 2# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass post-RA-hazard-rec %s -o - | FileCheck %s -check-prefixes=GCN,CIVI 3# RUN: llc -march=amdgcn -mcpu=fiji -run-pass post-RA-hazard-rec %s -o - | FileCheck %s -check-prefixes=GCN,CIVI,VI 4 5--- | 6 define void @div_fmas() { ret void } 7 define void @s_getreg() { ret void } 8 define void @s_setreg() { ret void } 9 define void @vmem_gt_8dw_store() { ret void } 10 define void @readwrite_lane() { ret void } 11 define void @rfe() { ret void } 12... 13--- 14# GCN-LABEL: name: div_fmas 15 16# GCN-LABEL: bb.0: 17# GCN: S_MOV_B64 18# GCN-NOT: S_NOP 19# GCN: V_DIV_FMAS 20 21# GCN-LABEL: bb.1: 22# GCN: V_CMP_EQ_I32 23# GCN: S_NOP 24# GCN: S_NOP 25# GCN: S_NOP 26# GCN: S_NOP 27# GCN: V_DIV_FMAS_F32 28 29# GCN-LABEL: bb.2: 30# GCN: V_CMP_EQ_I32 31# GCN: S_NOP 32# GCN: S_NOP 33# GCN: S_NOP 34# GCN: S_NOP 35# GCN: V_DIV_FMAS_F32 36 37# GCN-LABEL: bb.3: 38# GCN: V_DIV_SCALE_F32 39# GCN: S_NOP 40# GCN: S_NOP 41# GCN: S_NOP 42# GCN: S_NOP 43# GCN: V_DIV_FMAS_F32 44name: div_fmas 45 46body: | 47 bb.0: 48 successors: %bb.1 49 %vcc = S_MOV_B64 0 50 %vgpr0 = V_DIV_FMAS_F32 0, %vgpr1, 0, %vgpr2, 0, %vgpr3, 0, 0, implicit %vcc, implicit %exec 51 S_BRANCH %bb.1 52 53 bb.1: 54 successors: %bb.2 55 implicit %vcc = V_CMP_EQ_I32_e32 %vgpr1, %vgpr2, implicit %exec 56 %vgpr0 = V_DIV_FMAS_F32 0, %vgpr1, 0, %vgpr2, 0, %vgpr3, 0, 0, implicit %vcc, implicit %exec 57 S_BRANCH %bb.2 58 59 bb.2: 60 successors: %bb.3 61 %vcc = V_CMP_EQ_I32_e64 %vgpr1, %vgpr2, implicit %exec 62 %vgpr0 = V_DIV_FMAS_F32 0, %vgpr1, 0, %vgpr2, 0, %vgpr3, 0, 0, implicit %vcc, implicit %exec 63 S_BRANCH %bb.3 64 65 bb.3: 66 %vgpr4, %vcc = V_DIV_SCALE_F32 0, %vgpr1, 0, %vgpr1, 0, %vgpr3, 0, 0, implicit %exec 67 %vgpr0 = V_DIV_FMAS_F32 0, %vgpr1, 0, %vgpr2, 0, %vgpr3, 0, 0, implicit %vcc, implicit %exec 68 S_ENDPGM 69 70... 71 72... 73--- 74# GCN-LABEL: name: s_getreg 75 76# GCN-LABEL: bb.0: 77# GCN: S_SETREG 78# GCN: S_NOP 0 79# GCN: S_NOP 0 80# GCN: S_GETREG 81 82# GCN-LABEL: bb.1: 83# GCN: S_SETREG_IMM32 84# GCN: S_NOP 0 85# GCN: S_NOP 0 86# GCN: S_GETREG 87 88# GCN-LABEL: bb.2: 89# GCN: S_SETREG 90# GCN: S_NOP 0 91# GCN: S_GETREG 92 93# GCN-LABEL: bb.3: 94# GCN: S_SETREG 95# GCN-NEXT: S_GETREG 96 97name: s_getreg 98 99body: | 100 bb.0: 101 successors: %bb.1 102 S_SETREG_B32 %sgpr0, 1 103 %sgpr1 = S_GETREG_B32 1 104 S_BRANCH %bb.1 105 106 bb.1: 107 successors: %bb.2 108 S_SETREG_IMM32_B32 0, 1 109 %sgpr1 = S_GETREG_B32 1 110 S_BRANCH %bb.2 111 112 bb.2: 113 successors: %bb.3 114 S_SETREG_B32 %sgpr0, 1 115 %sgpr1 = S_MOV_B32 0 116 %sgpr2 = S_GETREG_B32 1 117 S_BRANCH %bb.3 118 119 bb.3: 120 S_SETREG_B32 %sgpr0, 0 121 %sgpr1 = S_GETREG_B32 1 122 S_ENDPGM 123... 124 125... 126--- 127# GCN-LABEL: name: s_setreg 128 129# GCN-LABEL: bb.0: 130# GCN: S_SETREG 131# GCN: S_NOP 0 132# VI: S_NOP 0 133# GCN-NEXT: S_SETREG 134 135# GCN-LABEL: bb.1: 136# GCN: S_SETREG 137# GCN: S_NOP 0 138# VI: S_NOP 0 139# GCN-NEXT: S_SETREG 140 141# GCN-LABEL: bb.2: 142# GCN: S_SETREG 143# GCN-NEXT: S_SETREG 144 145name: s_setreg 146 147body: | 148 bb.0: 149 successors: %bb.1 150 S_SETREG_B32 %sgpr0, 1 151 S_SETREG_B32 %sgpr1, 1 152 S_BRANCH %bb.1 153 154 bb.1: 155 successors: %bb.2 156 S_SETREG_B32 %sgpr0, 64 157 S_SETREG_B32 %sgpr1, 128 158 S_BRANCH %bb.2 159 160 bb.2: 161 S_SETREG_B32 %sgpr0, 1 162 S_SETREG_B32 %sgpr1, 0 163 S_ENDPGM 164... 165 166... 167--- 168# GCN-LABEL: name: vmem_gt_8dw_store 169 170# GCN-LABEL: bb.0: 171# GCN: BUFFER_STORE_DWORD_OFFSET 172# GCN-NEXT: V_MOV_B32 173# GCN: BUFFER_STORE_DWORDX3_OFFSET 174# CIVI: S_NOP 175# GCN-NEXT: V_MOV_B32 176# GCN: BUFFER_STORE_DWORDX4_OFFSET 177# GCN-NEXT: V_MOV_B32 178# GCN: BUFFER_STORE_DWORDX4_OFFSET 179# CIVI: S_NOP 180# GCN-NEXT: V_MOV_B32 181# GCN: BUFFER_STORE_FORMAT_XYZ_OFFSET 182# CIVI: S_NOP 183# GCN-NEXT: V_MOV_B32 184# GCN: BUFFER_STORE_FORMAT_XYZW_OFFSET 185# CIVI: S_NOP 186# GCN-NEXT: V_MOV_B32 187 188# GCN-LABEL: bb.1: 189# GCN: FLAT_STORE_DWORDX2 190# GCN-NEXT: V_MOV_B32 191# GCN: FLAT_STORE_DWORDX3 192# CIVI: S_NOP 193# GCN-NEXT: V_MOV_B32 194# GCN: FLAT_STORE_DWORDX4 195# CIVI: S_NOP 196# GCN-NEXT: V_MOV_B32 197# GCN: FLAT_ATOMIC_CMPSWAP_X2 198# CIVI: S_NOP 199# GCN-NEXT: V_MOV_B32 200# GCN: FLAT_ATOMIC_FCMPSWAP_X2 201# CIVI: S_NOP 202# GCN: V_MOV_B32 203 204name: vmem_gt_8dw_store 205 206body: | 207 bb.0: 208 successors: %bb.1 209 BUFFER_STORE_DWORD_OFFSET %vgpr3, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, 0, 0, implicit %exec 210 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 211 BUFFER_STORE_DWORDX3_OFFSET %vgpr2_vgpr3_vgpr4, %sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit %exec 212 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 213 BUFFER_STORE_DWORDX4_OFFSET %vgpr2_vgpr3_vgpr4_vgpr5, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, 0, 0, implicit %exec 214 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 215 BUFFER_STORE_DWORDX4_OFFSET %vgpr2_vgpr3_vgpr4_vgpr5, %sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit %exec 216 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 217 BUFFER_STORE_FORMAT_XYZ_OFFSET %vgpr2_vgpr3_vgpr4, %sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit %exec 218 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 219 BUFFER_STORE_FORMAT_XYZW_OFFSET %vgpr2_vgpr3_vgpr4_vgpr5, %sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit %exec 220 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 221 BUFFER_ATOMIC_CMPSWAP_X2_OFFSET %vgpr2_vgpr3_vgpr4_vgpr5, %sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, implicit %exec 222 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 223 S_BRANCH %bb.1 224 225 bb.1: 226 FLAT_STORE_DWORDX2 %vgpr0_vgpr1, %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr 227 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 228 FLAT_STORE_DWORDX3 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4, 0, 0, 0, implicit %exec, implicit %flat_scr 229 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 230 FLAT_STORE_DWORDX4 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr 231 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 232 FLAT_ATOMIC_CMPSWAP_X2 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, implicit %exec, implicit %flat_scr 233 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 234 FLAT_ATOMIC_FCMPSWAP_X2 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, implicit %exec, implicit %flat_scr 235 %vgpr3 = V_MOV_B32_e32 0, implicit %exec 236 S_ENDPGM 237 238... 239 240... 241--- 242 243# GCN-LABEL: name: readwrite_lane 244 245# GCN-LABEL: bb.0: 246# GCN: V_ADD_I32 247# GCN: S_NOP 248# GCN: S_NOP 249# GCN: S_NOP 250# GCN: S_NOP 251# GCN: V_READLANE_B32 252 253# GCN-LABEL: bb.1: 254# GCN: V_ADD_I32 255# GCN: S_NOP 256# GCN: S_NOP 257# GCN: S_NOP 258# GCN: S_NOP 259# GCN: V_WRITELANE_B32 260 261# GCN-LABEL: bb.2: 262# GCN: V_ADD_I32 263# GCN: S_NOP 264# GCN: S_NOP 265# GCN: S_NOP 266# GCN: S_NOP 267# GCN: V_READLANE_B32 268 269# GCN-LABEL: bb.3: 270# GCN: V_ADD_I32 271# GCN: S_NOP 272# GCN: S_NOP 273# GCN: S_NOP 274# GCN: S_NOP 275# GCN: V_WRITELANE_B32 276 277name: readwrite_lane 278 279body: | 280 bb.0: 281 successors: %bb.1 282 %vgpr0,%sgpr0_sgpr1 = V_ADD_I32_e64 %vgpr1, %vgpr2, implicit %vcc, implicit %exec 283 %sgpr4 = V_READLANE_B32 %vgpr4, %sgpr0 284 S_BRANCH %bb.1 285 286 bb.1: 287 successors: %bb.2 288 %vgpr0,%sgpr0_sgpr1 = V_ADD_I32_e64 %vgpr1, %vgpr2, implicit %vcc, implicit %exec 289 %vgpr4 = V_WRITELANE_B32 %sgpr0, %sgpr0 290 S_BRANCH %bb.2 291 292 bb.2: 293 successors: %bb.3 294 %vgpr0,implicit %vcc = V_ADD_I32_e32 %vgpr1, %vgpr2, implicit %vcc, implicit %exec 295 %sgpr4 = V_READLANE_B32 %vgpr4, %vcc_lo 296 S_BRANCH %bb.3 297 298 bb.3: 299 %vgpr0,implicit %vcc = V_ADD_I32_e32 %vgpr1, %vgpr2, implicit %vcc, implicit %exec 300 %vgpr4 = V_WRITELANE_B32 %sgpr4, %vcc_lo 301 S_ENDPGM 302 303... 304 305... 306--- 307 308# GCN-LABEL: name: rfe 309 310# GCN-LABEL: bb.0: 311# GCN: S_SETREG 312# VI: S_NOP 313# GCN-NEXT: S_RFE_B64 314 315# GCN-LABEL: bb.1: 316# GCN: S_SETREG 317# GCN-NEXT: S_RFE_B64 318 319name: rfe 320 321body: | 322 bb.0: 323 successors: %bb.1 324 S_SETREG_B32 %sgpr0, 3 325 S_RFE_B64 %sgpr2_sgpr3 326 S_BRANCH %bb.1 327 328 bb.1: 329 S_SETREG_B32 %sgpr0, 0 330 S_RFE_B64 %sgpr2_sgpr3 331 S_ENDPGM 332 333... 334