1; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=gfx901 -enable-amdgpu-aa=0 -mattr=+flat-for-global,-fp64-fp16-denormals < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=GFX89 %s 2; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=fiji -enable-amdgpu-aa=0 -mattr=+flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=CIVI -check-prefix=VI -check-prefix=GFX89 %s 3; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=hawaii -enable-amdgpu-aa=0 -mattr=+flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=CIVI -check-prefix=CI %s 4 5; GCN-LABEL: {{^}}s_insertelement_v2i16_0: 6; GCN: s_load_dword [[VEC:s[0-9]+]] 7 8; CIVI: s_and_b32 [[ELT1:s[0-9]+]], [[VEC]], 0xffff0000{{$}} 9; CIVI: s_or_b32 s{{[0-9]+}}, [[ELT1]], 0x3e7{{$}} 10 11; GFX9-NOT: lshr 12; GFX9: s_pack_lh_b32_b16 s{{[0-9]+}}, 0x3e7, [[VEC]] 13define amdgpu_kernel void @s_insertelement_v2i16_0(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(2)* %vec.ptr) #0 { 14 %vec = load <2 x i16>, <2 x i16> addrspace(2)* %vec.ptr 15 %vecins = insertelement <2 x i16> %vec, i16 999, i32 0 16 store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out 17 ret void 18} 19 20; GCN-LABEL: {{^}}s_insertelement_v2i16_0_reg: 21; GCN: s_load_dword [[ELT0:s[0-9]+]] 22; GCN: s_load_dword [[VEC:s[0-9]+]] 23 24; CIVI-DAG: s_and_b32 [[ELT0]], [[ELT0]], 0xffff{{$}} 25; CIVI-DAG: s_and_b32 [[ELT1:s[0-9]+]], [[VEC]], 0xffff0000{{$}} 26; CIVI: s_or_b32 s{{[0-9]+}}, [[ELT0]], [[ELT1]] 27 28; GFX9-NOT: [[ELT0]] 29; GFX9-NOT: [[VEC]] 30; GFX9: s_pack_lh_b32_b16 s{{[0-9]+}}, [[ELT0]], [[VEC]] 31define amdgpu_kernel void @s_insertelement_v2i16_0_reg(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(2)* %vec.ptr, i16 %elt) #0 { 32 %vec = load <2 x i16>, <2 x i16> addrspace(2)* %vec.ptr 33 %vecins = insertelement <2 x i16> %vec, i16 %elt, i32 0 34 store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out 35 ret void 36} 37 38; GCN-LABEL: {{^}}s_insertelement_v2i16_0_multi_use_hi_reg: 39; GCN: s_load_dword [[ELT0:s[0-9]+]] 40; GCN: s_load_dword [[VEC:s[0-9]+]] 41 42; CIVI-DAG: s_and_b32 [[ELT0]], [[ELT0]], 0xffff{{$}} 43; CIVI: s_lshr_b32 [[SHR:s[0-9]+]], [[VEC]], 16 44; CIVI: s_lshl_b32 [[ELT1:s[0-9]+]], [[SHR]], 16 45; CIVI-DAG: s_or_b32 s{{[0-9]+}}, [[ELT0]], [[ELT1]] 46; CIVI-DAG: ; use [[SHR]] 47 48; GFX9: s_lshr_b32 [[ELT1:s[0-9]+]], [[VEC]], 16 49; GFX9-DAG: s_pack_ll_b32_b16 s{{[0-9]+}}, [[ELT0]], [[ELT1]] 50; GFX9-DAG: ; use [[ELT1]] 51define amdgpu_kernel void @s_insertelement_v2i16_0_multi_use_hi_reg(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(2)* %vec.ptr, i16 %elt) #0 { 52 %vec = load <2 x i16>, <2 x i16> addrspace(2)* %vec.ptr 53 %elt1 = extractelement <2 x i16> %vec, i32 1 54 %vecins = insertelement <2 x i16> %vec, i16 %elt, i32 0 55 store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out 56 %use1 = zext i16 %elt1 to i32 57 call void asm sideeffect "; use $0", "s"(i32 %use1) #0 58 ret void 59} 60 61; GCN-LABEL: {{^}}s_insertelement_v2i16_0_reghi: 62; GCN: s_load_dword [[ELT_ARG:s[0-9]+]], s[0:1] 63; GCN: s_load_dword [[VEC:s[0-9]+]] 64 65; CIVI-DAG: s_and_b32 [[ELT1:s[0-9]+]], [[VEC]], 0xffff0000{{$}} 66; CIVI: s_or_b32 s{{[0-9]+}}, [[ELT_ARG]], [[ELT1]] 67 68; GFX9-NOT: [[ELT0]] 69; GFX9-NOT: [[VEC]] 70; GFX9: s_pack_hh_b32_b16 s{{[0-9]+}}, [[ELT_ARG]], [[VEC]] 71define amdgpu_kernel void @s_insertelement_v2i16_0_reghi(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(2)* %vec.ptr, i32 %elt.arg) #0 { 72 %vec = load <2 x i16>, <2 x i16> addrspace(2)* %vec.ptr 73 %elt.hi = lshr i32 %elt.arg, 16 74 %elt = trunc i32 %elt.hi to i16 75 %vecins = insertelement <2 x i16> %vec, i16 %elt, i32 0 76 store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out 77 ret void 78} 79 80; GCN-LABEL: {{^}}s_insertelement_v2i16_0_reghi_multi_use_1: 81; GCN: s_load_dword [[ELT_ARG:s[0-9]+]], s[0:1] 82; GCN: s_load_dword [[VEC:s[0-9]+]], 83 84; CIVI-DAG: s_and_b32 [[ELT1:s[0-9]+]], [[VEC]], 0xffff0000{{$}} 85; CIVI: s_or_b32 s{{[0-9]+}}, [[ELT0]], [[ELT1]] 86 87; GFX9: s_lshr_b32 [[ELT1:s[0-9]+]], [[ELT_ARG]], 16 88; GFX9: s_pack_lh_b32_b16 s{{[0-9]+}}, [[ELT1]], [[VEC]] 89; GFX9: ; use [[ELT1]] 90define amdgpu_kernel void @s_insertelement_v2i16_0_reghi_multi_use_1(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(2)* %vec.ptr, i32 %elt.arg) #0 { 91 %vec = load <2 x i16>, <2 x i16> addrspace(2)* %vec.ptr 92 %elt.hi = lshr i32 %elt.arg, 16 93 %elt = trunc i32 %elt.hi to i16 94 %vecins = insertelement <2 x i16> %vec, i16 %elt, i32 0 95 store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out 96 %use1 = zext i16 %elt to i32 97 call void asm sideeffect "; use $0", "s"(i32 %use1) #0 98 ret void 99} 100 101; GCN-LABEL: {{^}}s_insertelement_v2i16_0_reghi_both_multi_use_1: 102; GCN: s_load_dword [[ELT_ARG:s[0-9]+]], s[0:1] 103; GCN: s_load_dword [[VEC:s[0-9]+]], 104 105; CIVI-DAG: s_lshr_b32 [[ELT_HI:s[0-9]+]], [[ELT_ARG]], 16 106; CIVI-DAG: s_lshr_b32 [[SHR:s[0-9]+]], [[VEC]], 16 107; CIVI-DAG: s_lshl_b32 [[VEC_HI:s[0-9]+]], [[SHR]], 16 108; CIVI: s_or_b32 s{{[0-9]+}}, [[ELT_HI]], [[VEC_HI]] 109 110; GFX9-DAG: s_lshr_b32 [[ELT_HI:s[0-9]+]], [[ELT_ARG]], 16 111; GFX9-DAG: s_lshr_b32 [[VEC_HI:s[0-9]+]], [[VEC]], 16 112; GFX9: s_pack_ll_b32_b16 s{{[0-9]+}}, [[ELT_HI]], [[VEC_HI]] 113; GFX9: ; use [[ELT_HI]] 114; GFX9: ; use [[VEC_HI]] 115define amdgpu_kernel void @s_insertelement_v2i16_0_reghi_both_multi_use_1(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(2)* %vec.ptr, i32 %elt.arg) #0 { 116 %vec = load <2 x i16>, <2 x i16> addrspace(2)* %vec.ptr 117 %elt.hi = lshr i32 %elt.arg, 16 118 %elt = trunc i32 %elt.hi to i16 119 %vec.hi = extractelement <2 x i16> %vec, i32 1 120 %vecins = insertelement <2 x i16> %vec, i16 %elt, i32 0 121 store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out 122 %use1 = zext i16 %elt to i32 123 %vec.hi.use1 = zext i16 %vec.hi to i32 124 125 call void asm sideeffect "; use $0", "s"(i32 %use1) #0 126 call void asm sideeffect "; use $0", "s"(i32 %vec.hi.use1) #0 127 ret void 128} 129 130; GCN-LABEL: {{^}}s_insertelement_v2i16_1: 131; GCN: s_load_dword [[VEC:s[0-9]+]] 132 133; GCN-NOT: s_lshr 134 135; CIVI: s_and_b32 [[ELT0:s[0-9]+]], [[VEC]], 0xffff{{$}} 136; CIVI: s_or_b32 [[INS:s[0-9]+]], [[ELT0]], 0x3e70000 137 138; GFX9: s_pack_ll_b32_b16 s{{[0-9]+}}, [[VEC]], 0x3e7 139define amdgpu_kernel void @s_insertelement_v2i16_1(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(2)* %vec.ptr) #0 { 140 %vec = load <2 x i16>, <2 x i16> addrspace(2)* %vec.ptr 141 %vecins = insertelement <2 x i16> %vec, i16 999, i32 1 142 store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out 143 ret void 144} 145 146; GCN-LABEL: {{^}}s_insertelement_v2i16_1_reg: 147; GCN: s_load_dword [[ELT1:s[0-9]+]] 148; GCN: s_load_dword [[VEC:s[0-9]+]] 149 150; CIVI: s_and_b32 [[ELT0:s[0-9]+]], [[VEC]], 0xffff{{$}} 151; CIVI: s_or_b32 s{{[0-9]+}}, [[ELT0]], [[ELT1]] 152 153; GCN-NOT: shlr 154; GFX9: s_pack_ll_b32_b16 s{{[0-9]+}}, [[VEC]], [[ELT1]] 155define amdgpu_kernel void @s_insertelement_v2i16_1_reg(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(2)* %vec.ptr, i16 %elt) #0 { 156 %vec = load <2 x i16>, <2 x i16> addrspace(2)* %vec.ptr 157 %vecins = insertelement <2 x i16> %vec, i16 %elt, i32 1 158 store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out 159 ret void 160} 161 162; GCN-LABEL: {{^}}s_insertelement_v2f16_0: 163; GCN: s_load_dword [[VEC:s[0-9]+]] 164; CIVI: s_and_b32 [[ELT1:s[0-9]+]], [[VEC:s[0-9]+]], 0xffff0000 165; CIVI: s_or_b32 s{{[0-9]+}}, [[ELT1]], 0x4500 166 167; GFX9: s_lshr_b32 [[ELT1:s[0-9]+]], [[VEC]], 16 168; GFX9: s_pack_ll_b32_b16 s{{[0-9]+}}, 0x4500, [[ELT1]] 169define amdgpu_kernel void @s_insertelement_v2f16_0(<2 x half> addrspace(1)* %out, <2 x half> addrspace(2)* %vec.ptr) #0 { 170 %vec = load <2 x half>, <2 x half> addrspace(2)* %vec.ptr 171 %vecins = insertelement <2 x half> %vec, half 5.000000e+00, i32 0 172 store <2 x half> %vecins, <2 x half> addrspace(1)* %out 173 ret void 174} 175 176; GCN-LABEL: {{^}}s_insertelement_v2f16_1: 177; GFX9: s_load_dword [[VEC:s[0-9]+]] 178; GCN-NOT: s_lshr 179 180; CIVI: s_and_b32 [[ELT0:s[0-9]+]], [[VEC]], 0xffff{{$}} 181; CIVI: s_or_b32 [[INS:s[0-9]+]], [[ELT0]], 0x45000000 182 183; GFX9: s_pack_ll_b32_b16 s{{[0-9]+}}, [[VEC]], 0x4500 184define amdgpu_kernel void @s_insertelement_v2f16_1(<2 x half> addrspace(1)* %out, <2 x half> addrspace(2)* %vec.ptr) #0 { 185 %vec = load <2 x half>, <2 x half> addrspace(2)* %vec.ptr 186 %vecins = insertelement <2 x half> %vec, half 5.000000e+00, i32 1 187 store <2 x half> %vecins, <2 x half> addrspace(1)* %out 188 ret void 189} 190 191; GCN-LABEL: {{^}}v_insertelement_v2i16_0: 192; GCN-DAG: flat_load_dword [[VEC:v[0-9]+]] 193; CIVI: v_and_b32_e32 [[ELT1:v[0-9]+]], 0xffff0000, [[VEC]] 194; CIVI: v_or_b32_e32 [[RES:v[0-9]+]], 0x3e7, [[ELT1]] 195 196; GFX9-DAG: s_movk_i32 [[ELT0:s[0-9]+]], 0x3e7{{$}} 197; GFX9-DAG: v_mov_b32_e32 [[MASK:v[0-9]+]], 0xffff{{$}} 198; GFX9: v_bfi_b32 [[RES:v[0-9]+]], [[MASK]], [[ELT0]], [[VEC]] 199; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RES]] 200define amdgpu_kernel void @v_insertelement_v2i16_0(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 201 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 202 %tid.ext = sext i32 %tid to i64 203 %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 204 %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 205 %vec = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep 206 %vecins = insertelement <2 x i16> %vec, i16 999, i32 0 207 store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out.gep 208 ret void 209} 210 211; GCN-LABEL: {{^}}v_insertelement_v2i16_0_reghi: 212; GCN-DAG: flat_load_dword [[VEC:v[0-9]+]] 213; GCN-DAG: s_load_dword [[ELT0:s[0-9]+]] 214 215; CIVI-DAG: s_lshr_b32 [[ELT0_SHIFT:s[0-9]+]], [[ELT0]], 16 216; CIVI-DAG: v_and_b32_e32 [[ELT1:v[0-9]+]], 0xffff0000, [[VEC]] 217; CIVI: v_or_b32_e32 [[RES:v[0-9]+]], [[ELT0_SHIFT]], [[ELT1]] 218 219; GFX9-DAG: v_mov_b32_e32 [[MASK:v[0-9]+]], 0xffff0000{{$}} 220; GFX9-DAG: v_lshrrev_b32_e64 [[ELT0_SHIFT:v[0-9]+]], 16, [[ELT0]] 221; GFX9: v_and_or_b32 [[RES:v[0-9]+]], [[VEC]], [[MASK]], [[ELT0_SHIFT]] 222 223; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RES]] 224define amdgpu_kernel void @v_insertelement_v2i16_0_reghi(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in, i32 %elt.arg) #0 { 225 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 226 %tid.ext = sext i32 %tid to i64 227 %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 228 %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 229 %vec = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep 230 %elt.hi = lshr i32 %elt.arg, 16 231 %elt = trunc i32 %elt.hi to i16 232 %vecins = insertelement <2 x i16> %vec, i16 %elt, i32 0 233 store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out.gep 234 ret void 235} 236 237; GCN-LABEL: {{^}}v_insertelement_v2i16_0_inlineimm: 238; GCN-DAG: flat_load_dword [[VEC:v[0-9]+]] 239 240; CIVI: v_and_b32_e32 [[ELT1:v[0-9]+]], 0xffff0000, [[VEC]] 241; CIVI: v_or_b32_e32 [[RES:v[0-9]+]], 53, [[ELT1]] 242 243; GFX9-DAG: v_mov_b32_e32 [[MASK:v[0-9]+]], 0xffff{{$}} 244; GFX9: v_bfi_b32 [[RES:v[0-9]+]], [[MASK]], 53, [[VEC]] 245 246; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RES]] 247define amdgpu_kernel void @v_insertelement_v2i16_0_inlineimm(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 248 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 249 %tid.ext = sext i32 %tid to i64 250 %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 251 %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 252 %vec = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep 253 %vecins = insertelement <2 x i16> %vec, i16 53, i32 0 254 store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out.gep 255 ret void 256} 257 258; FIXME: fold lshl_or c0, c1, v0 -> or (c0 << c1), v0 259 260; GCN-LABEL: {{^}}v_insertelement_v2i16_1: 261; VI: v_mov_b32_e32 [[K:v[0-9]+]], 0x3e70000 262; GCN-DAG: flat_load_dword [[VEC:v[0-9]+]] 263; CI: v_or_b32_e32 [[RES:v[0-9]+]], 0x3e70000, [[VEC]] 264; VI: v_or_b32_sdwa [[RES:v[0-9]+]], [[VEC]], [[K]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 265 266; GFX9-DAG: s_movk_i32 [[K:s[0-9]+]], 0x3e7 267; GFX9-DAG: v_and_b32_e32 [[ELT0:v[0-9]+]], 0xffff, [[VEC]] 268; GFX9: v_lshl_or_b32 [[RES:v[0-9]+]], [[K]], 16, [[ELT0]] 269 270; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RES]] 271define amdgpu_kernel void @v_insertelement_v2i16_1(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 272 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 273 %tid.ext = sext i32 %tid to i64 274 %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 275 %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 276 %vec = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep 277 %vecins = insertelement <2 x i16> %vec, i16 999, i32 1 278 store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out.gep 279 ret void 280} 281 282; GCN-LABEL: {{^}}v_insertelement_v2i16_1_inlineimm: 283; VI: v_mov_b32_e32 [[K:v[0-9]+]], 0xfff10000 284; GCN: flat_load_dword [[VEC:v[0-9]+]] 285; CI: v_and_b32_e32 [[ELT0:v[0-9]+]], 0xffff, [[VEC]] 286; GFX9: v_and_b32_e32 [[ELT0:v[0-9]+]], 0xffff, [[VEC]] 287; CI: v_or_b32_e32 [[RES:v[0-9]+]], 0xfff10000, [[ELT0]] 288; VI: v_or_b32_sdwa [[RES:v[0-9]+]], [[VEC]], [[K]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 289; GFX9: v_lshl_or_b32 [[RES:v[0-9]+]], -15, 16, [[ELT0]] 290; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RES]] 291define amdgpu_kernel void @v_insertelement_v2i16_1_inlineimm(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 292 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 293 %tid.ext = sext i32 %tid to i64 294 %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 295 %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 296 %vec = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep 297 %vecins = insertelement <2 x i16> %vec, i16 -15, i32 1 298 store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out.gep 299 ret void 300} 301 302; GCN-LABEL: {{^}}v_insertelement_v2f16_0: 303; GCN-DAG: flat_load_dword [[VEC:v[0-9]+]] 304 305; CIVI: v_and_b32_e32 [[ELT1:v[0-9]+]], 0xffff0000, [[VEC]] 306; CIVI: v_or_b32_e32 [[RES:v[0-9]+]], 0x4500, [[ELT1]] 307 308; GFX9-DAG: v_mov_b32_e32 [[ELT0:v[0-9]+]], 0x4500{{$}} 309; GFX9-DAG: v_lshrrev_b32_e32 [[ELT1:v[0-9]+]], 16, [[VEC]] 310; GFX9: v_lshl_or_b32 [[RES:v[0-9]+]], [[ELT1]], 16, [[ELT0]] 311 312; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RES]] 313define amdgpu_kernel void @v_insertelement_v2f16_0(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in) #0 { 314 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 315 %tid.ext = sext i32 %tid to i64 316 %in.gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %in, i64 %tid.ext 317 %out.gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %out, i64 %tid.ext 318 %vec = load <2 x half>, <2 x half> addrspace(1)* %in.gep 319 %vecins = insertelement <2 x half> %vec, half 5.000000e+00, i32 0 320 store <2 x half> %vecins, <2 x half> addrspace(1)* %out.gep 321 ret void 322} 323 324; GCN-LABEL: {{^}}v_insertelement_v2f16_0_inlineimm: 325; GCN: flat_load_dword [[VEC:v[0-9]+]] 326 327; CIVI: v_and_b32_e32 [[ELT1:v[0-9]+]], 0xffff0000, [[VEC]] 328; CIVI: v_or_b32_e32 [[RES:v[0-9]+]], 53, [[ELT1]] 329 330; GFX9: v_lshrrev_b32_e32 [[ELT1:v[0-9]+]], 16, [[VEC]] 331; GFX9: v_lshl_or_b32 [[RES:v[0-9]+]], [[ELT1]], 16, 53 332; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RES]] 333define amdgpu_kernel void @v_insertelement_v2f16_0_inlineimm(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in) #0 { 334 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 335 %tid.ext = sext i32 %tid to i64 336 %in.gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %in, i64 %tid.ext 337 %out.gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %out, i64 %tid.ext 338 %vec = load <2 x half>, <2 x half> addrspace(1)* %in.gep 339 %vecins = insertelement <2 x half> %vec, half 0xH0035, i32 0 340 store <2 x half> %vecins, <2 x half> addrspace(1)* %out.gep 341 ret void 342} 343 344; GCN-LABEL: {{^}}v_insertelement_v2f16_1: 345; VI: v_mov_b32_e32 [[K:v[0-9]+]], 0x45000000 346; GCN-DAG: flat_load_dword [[VEC:v[0-9]+]] 347; CI: v_or_b32_e32 [[RES:v[0-9]+]], 0x45000000, [[VEC]] 348; VI: v_or_b32_sdwa [[RES:v[0-9]+]], [[VEC]], [[K]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 349 350; GFX9-DAG: s_movk_i32 [[K:s[0-9]+]], 0x4500 351; GFX9-DAG: v_and_b32_e32 [[ELT0:v[0-9]+]], 0xffff, [[VEC]] 352; GFX9: v_lshl_or_b32 [[RES:v[0-9]+]], [[K]], 16, [[ELT0]] 353 354; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RES]] 355define amdgpu_kernel void @v_insertelement_v2f16_1(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in) #0 { 356 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 357 %tid.ext = sext i32 %tid to i64 358 %in.gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %in, i64 %tid.ext 359 %out.gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %out, i64 %tid.ext 360 %vec = load <2 x half>, <2 x half> addrspace(1)* %in.gep 361 %vecins = insertelement <2 x half> %vec, half 5.000000e+00, i32 1 362 store <2 x half> %vecins, <2 x half> addrspace(1)* %out.gep 363 ret void 364} 365 366; GCN-LABEL: {{^}}v_insertelement_v2f16_1_inlineimm: 367; VI: v_mov_b32_e32 [[K:v[0-9]+]], 0x230000 368; GCN: flat_load_dword [[VEC:v[0-9]+]] 369; CI: v_and_b32_e32 [[ELT0:v[0-9]+]], 0xffff, [[VEC]] 370; GFX9: v_and_b32_e32 [[ELT0:v[0-9]+]], 0xffff, [[VEC]] 371; CI: v_or_b32_e32 [[RES:v[0-9]+]], 0x230000, [[ELT0]] 372; VI: v_or_b32_sdwa [[RES:v[0-9]+]], [[VEC]], [[K]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 373; GFX9: v_lshl_or_b32 [[RES:v[0-9]+]], 35, 16, [[ELT0]] 374; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RES]] 375define amdgpu_kernel void @v_insertelement_v2f16_1_inlineimm(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in) #0 { 376 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 377 %tid.ext = sext i32 %tid to i64 378 %in.gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %in, i64 %tid.ext 379 %out.gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %out, i64 %tid.ext 380 %vec = load <2 x half>, <2 x half> addrspace(1)* %in.gep 381 %vecins = insertelement <2 x half> %vec, half 0xH0023, i32 1 382 store <2 x half> %vecins, <2 x half> addrspace(1)* %out.gep 383 ret void 384} 385 386; FIXME: Enable for others when argument load not split 387; GCN-LABEL: {{^}}s_insertelement_v2i16_dynamic: 388; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x3e7 389; GCN: s_load_dword [[IDX:s[0-9]+]] 390; GCN: s_load_dword [[VEC:s[0-9]+]] 391; GCN-DAG: v_mov_b32_e32 [[VVEC:v[0-9]+]], [[VEC]] 392; GCN-DAG: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 16 393; GCN-DAG: s_lshl_b32 [[MASK:s[0-9]+]], 0xffff, [[SCALED_IDX]] 394; GCN: v_bfi_b32 [[RESULT:v[0-9]+]], [[MASK]], [[K]], [[VVEC]] 395; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]] 396define amdgpu_kernel void @s_insertelement_v2i16_dynamic(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(2)* %vec.ptr, i32 addrspace(2)* %idx.ptr) #0 { 397 %idx = load volatile i32, i32 addrspace(2)* %idx.ptr 398 %vec = load <2 x i16>, <2 x i16> addrspace(2)* %vec.ptr 399 %vecins = insertelement <2 x i16> %vec, i16 999, i32 %idx 400 store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out 401 ret void 402} 403 404; GCN-LABEL: {{^}}v_insertelement_v2i16_dynamic_sgpr: 405; GCN-DAG: flat_load_dword [[VEC:v[0-9]+]] 406; GCN-DAG: s_load_dword [[IDX:s[0-9]+]] 407; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x3e7 408; GCN-DAG: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 16 409; GCN-DAG: s_lshl_b32 [[MASK:s[0-9]+]], 0xffff, [[SCALED_IDX]] 410; GCN: v_bfi_b32 [[RESULT:v[0-9]+]], [[MASK]], [[K]], [[VEC]] 411; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]] 412define amdgpu_kernel void @v_insertelement_v2i16_dynamic_sgpr(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in, i32 %idx) #0 { 413 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 414 %tid.ext = sext i32 %tid to i64 415 %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 416 %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 417 %vec = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep 418 %vecins = insertelement <2 x i16> %vec, i16 999, i32 %idx 419 store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out.gep 420 ret void 421} 422 423; GCN-LABEL: {{^}}v_insertelement_v2i16_dynamic_vgpr: 424; GCN: flat_load_dword [[IDX:v[0-9]+]] 425; GCN: flat_load_dword [[VEC:v[0-9]+]] 426; GFX89-DAG: s_mov_b32 [[MASKK:s[0-9]+]], 0xffff{{$}} 427; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x3e7 428 429; GFX89-DAG: v_lshlrev_b32_e32 [[SCALED_IDX:v[0-9]+]], 16, [[IDX]] 430; GFX89-DAG: v_lshlrev_b32_e64 [[MASK:v[0-9]+]], [[SCALED_IDX]], [[MASKK]] 431 432; CI-DAG: v_lshlrev_b32_e32 [[SCALED_IDX:v[0-9]+]], 16, [[IDX]] 433; CI-DAG: v_lshl_b32_e32 [[MASK:v[0-9]+]], 0xffff, [[SCALED_IDX]] 434 435; GCN: v_bfi_b32 [[RESULT:v[0-9]+]], [[MASK]], [[K]], [[VEC]] 436; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]] 437define amdgpu_kernel void @v_insertelement_v2i16_dynamic_vgpr(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in, i32 addrspace(1)* %idx.ptr) #0 { 438 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 439 %tid.ext = sext i32 %tid to i64 440 %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 441 %idx.gep = getelementptr inbounds i32, i32 addrspace(1)* %idx.ptr, i64 %tid.ext 442 %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 443 %idx = load i32, i32 addrspace(1)* %idx.gep 444 %vec = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep 445 %vecins = insertelement <2 x i16> %vec, i16 999, i32 %idx 446 store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out.gep 447 ret void 448} 449 450; GCN-LABEL: {{^}}v_insertelement_v2f16_dynamic_vgpr: 451; GCN: flat_load_dword [[IDX:v[0-9]+]] 452; GCN: flat_load_dword [[VEC:v[0-9]+]] 453; GFX89-DAG: s_mov_b32 [[MASKK:s[0-9]+]], 0xffff{{$}} 454; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x1234 455 456; GFX89-DAG: v_lshlrev_b32_e32 [[SCALED_IDX:v[0-9]+]], 16, [[IDX]] 457; GFX89-DAG: v_lshlrev_b32_e64 [[MASK:v[0-9]+]], [[SCALED_IDX]], [[MASKK]] 458 459; CI-DAG: v_lshlrev_b32_e32 [[SCALED_IDX:v[0-9]+]], 16, [[IDX]] 460; CI-DAG: v_lshl_b32_e32 [[MASK:v[0-9]+]], 0xffff, [[SCALED_IDX]] 461 462; GCN: v_bfi_b32 [[RESULT:v[0-9]+]], [[MASK]], [[K]], [[VEC]] 463; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]] 464define amdgpu_kernel void @v_insertelement_v2f16_dynamic_vgpr(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in, i32 addrspace(1)* %idx.ptr) #0 { 465 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 466 %tid.ext = sext i32 %tid to i64 467 %in.gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %in, i64 %tid.ext 468 %idx.gep = getelementptr inbounds i32, i32 addrspace(1)* %idx.ptr, i64 %tid.ext 469 %out.gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %out, i64 %tid.ext 470 %idx = load i32, i32 addrspace(1)* %idx.gep 471 %vec = load <2 x half>, <2 x half> addrspace(1)* %in.gep 472 %vecins = insertelement <2 x half> %vec, half 0xH1234, i32 %idx 473 store <2 x half> %vecins, <2 x half> addrspace(1)* %out.gep 474 ret void 475} 476 477declare i32 @llvm.amdgcn.workitem.id.x() #1 478 479attributes #0 = { nounwind } 480attributes #1 = { nounwind readnone } 481