1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -enable-amdgpu-aa=0 -mattr=+flat-for-global -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX89,GFX9 %s
3; RUN: llc -verify-machineinstrs -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -enable-amdgpu-aa=0 -mattr=+flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX89,CIVI,VI %s
4; RUN: llc -verify-machineinstrs -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -enable-amdgpu-aa=0 -mattr=+flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI,CI %s
5
6define amdgpu_kernel void @s_insertelement_v2i16_0(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(4)* %vec.ptr) #0 {
7; GFX9-LABEL: s_insertelement_v2i16_0:
8; GFX9:       ; %bb.0:
9; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
10; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
11; GFX9-NEXT:    v_mov_b32_e32 v0, s0
12; GFX9-NEXT:    s_load_dword s0, s[2:3], 0x0
13; GFX9-NEXT:    v_mov_b32_e32 v1, s1
14; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
15; GFX9-NEXT:    s_pack_lh_b32_b16 s0, 0x3e7, s0
16; GFX9-NEXT:    v_mov_b32_e32 v2, s0
17; GFX9-NEXT:    global_store_dword v[0:1], v2, off
18; GFX9-NEXT:    s_endpgm
19;
20; CIVI-LABEL: s_insertelement_v2i16_0:
21; CIVI:       ; %bb.0:
22; CIVI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
23; CIVI-NEXT:    s_waitcnt lgkmcnt(0)
24; CIVI-NEXT:    v_mov_b32_e32 v0, s0
25; CIVI-NEXT:    s_load_dword s0, s[2:3], 0x0
26; CIVI-NEXT:    v_mov_b32_e32 v1, s1
27; CIVI-NEXT:    s_waitcnt lgkmcnt(0)
28; CIVI-NEXT:    s_and_b32 s0, s0, 0xffff0000
29; CIVI-NEXT:    s_or_b32 s0, s0, 0x3e7
30; CIVI-NEXT:    v_mov_b32_e32 v2, s0
31; CIVI-NEXT:    flat_store_dword v[0:1], v2
32; CIVI-NEXT:    s_endpgm
33  %vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr
34  %vecins = insertelement <2 x i16> %vec, i16 999, i32 0
35  store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out
36  ret void
37}
38
39
40define amdgpu_kernel void @s_insertelement_v2i16_0_reg(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(4)* %vec.ptr, [8 x i32], i16 %elt) #0 {
41; GFX9-LABEL: s_insertelement_v2i16_0_reg:
42; GFX9:       ; %bb.0:
43; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
44; GFX9-NEXT:    s_load_dword s4, s[4:5], 0x30
45; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
46; GFX9-NEXT:    v_mov_b32_e32 v0, s0
47; GFX9-NEXT:    s_load_dword s0, s[2:3], 0x0
48; GFX9-NEXT:    v_mov_b32_e32 v1, s1
49; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
50; GFX9-NEXT:    s_pack_lh_b32_b16 s0, s4, s0
51; GFX9-NEXT:    v_mov_b32_e32 v2, s0
52; GFX9-NEXT:    global_store_dword v[0:1], v2, off
53; GFX9-NEXT:    s_endpgm
54;
55; VI-LABEL: s_insertelement_v2i16_0_reg:
56; VI:       ; %bb.0:
57; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
58; VI-NEXT:    s_load_dword s4, s[4:5], 0x30
59; VI-NEXT:    s_waitcnt lgkmcnt(0)
60; VI-NEXT:    v_mov_b32_e32 v0, s0
61; VI-NEXT:    s_load_dword s0, s[2:3], 0x0
62; VI-NEXT:    v_mov_b32_e32 v1, s1
63; VI-NEXT:    s_and_b32 s1, s4, 0xffff
64; VI-NEXT:    s_waitcnt lgkmcnt(0)
65; VI-NEXT:    s_and_b32 s0, s0, 0xffff0000
66; VI-NEXT:    s_or_b32 s0, s1, s0
67; VI-NEXT:    v_mov_b32_e32 v2, s0
68; VI-NEXT:    flat_store_dword v[0:1], v2
69; VI-NEXT:    s_endpgm
70;
71; CI-LABEL: s_insertelement_v2i16_0_reg:
72; CI:       ; %bb.0:
73; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
74; CI-NEXT:    s_load_dword s4, s[4:5], 0xc
75; CI-NEXT:    s_waitcnt lgkmcnt(0)
76; CI-NEXT:    s_load_dword s2, s[2:3], 0x0
77; CI-NEXT:    v_mov_b32_e32 v0, s0
78; CI-NEXT:    v_mov_b32_e32 v1, s1
79; CI-NEXT:    s_and_b32 s1, s4, 0xffff
80; CI-NEXT:    s_waitcnt lgkmcnt(0)
81; CI-NEXT:    s_and_b32 s0, s2, 0xffff0000
82; CI-NEXT:    s_or_b32 s0, s1, s0
83; CI-NEXT:    v_mov_b32_e32 v2, s0
84; CI-NEXT:    flat_store_dword v[0:1], v2
85; CI-NEXT:    s_endpgm
86  %vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr
87  %vecins = insertelement <2 x i16> %vec, i16 %elt, i32 0
88  store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out
89  ret void
90}
91
92define amdgpu_kernel void @s_insertelement_v2i16_0_multi_use_hi_reg(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(4)* %vec.ptr, [8 x i32], i16 %elt) #0 {
93; GFX9-LABEL: s_insertelement_v2i16_0_multi_use_hi_reg:
94; GFX9:       ; %bb.0:
95; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
96; GFX9-NEXT:    s_load_dword s4, s[4:5], 0x30
97; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
98; GFX9-NEXT:    s_load_dword s2, s[2:3], 0x0
99; GFX9-NEXT:    v_mov_b32_e32 v0, s0
100; GFX9-NEXT:    v_mov_b32_e32 v1, s1
101; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
102; GFX9-NEXT:    s_lshr_b32 s0, s2, 16
103; GFX9-NEXT:    s_pack_ll_b32_b16 s1, s4, s0
104; GFX9-NEXT:    v_mov_b32_e32 v2, s1
105; GFX9-NEXT:    global_store_dword v[0:1], v2, off
106; GFX9-NEXT:    ;;#ASMSTART
107; GFX9-NEXT:    ; use s0
108; GFX9-NEXT:    ;;#ASMEND
109; GFX9-NEXT:    s_endpgm
110;
111; VI-LABEL: s_insertelement_v2i16_0_multi_use_hi_reg:
112; VI:       ; %bb.0:
113; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
114; VI-NEXT:    s_load_dword s4, s[4:5], 0x30
115; VI-NEXT:    s_waitcnt lgkmcnt(0)
116; VI-NEXT:    v_mov_b32_e32 v0, s0
117; VI-NEXT:    s_load_dword s0, s[2:3], 0x0
118; VI-NEXT:    v_mov_b32_e32 v1, s1
119; VI-NEXT:    s_and_b32 s1, s4, 0xffff
120; VI-NEXT:    s_waitcnt lgkmcnt(0)
121; VI-NEXT:    s_lshr_b32 s2, s0, 16
122; VI-NEXT:    s_and_b32 s0, s0, 0xffff0000
123; VI-NEXT:    s_or_b32 s0, s1, s0
124; VI-NEXT:    v_mov_b32_e32 v2, s0
125; VI-NEXT:    flat_store_dword v[0:1], v2
126; VI-NEXT:    ;;#ASMSTART
127; VI-NEXT:    ; use s2
128; VI-NEXT:    ;;#ASMEND
129; VI-NEXT:    s_endpgm
130;
131; CI-LABEL: s_insertelement_v2i16_0_multi_use_hi_reg:
132; CI:       ; %bb.0:
133; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
134; CI-NEXT:    s_load_dword s4, s[4:5], 0xc
135; CI-NEXT:    s_waitcnt lgkmcnt(0)
136; CI-NEXT:    s_load_dword s2, s[2:3], 0x0
137; CI-NEXT:    v_mov_b32_e32 v1, s1
138; CI-NEXT:    v_mov_b32_e32 v0, s0
139; CI-NEXT:    s_and_b32 s0, s4, 0xffff
140; CI-NEXT:    s_waitcnt lgkmcnt(0)
141; CI-NEXT:    s_lshr_b32 s1, s2, 16
142; CI-NEXT:    s_lshl_b32 s2, s1, 16
143; CI-NEXT:    s_or_b32 s0, s0, s2
144; CI-NEXT:    v_mov_b32_e32 v2, s0
145; CI-NEXT:    flat_store_dword v[0:1], v2
146; CI-NEXT:    ;;#ASMSTART
147; CI-NEXT:    ; use s1
148; CI-NEXT:    ;;#ASMEND
149; CI-NEXT:    s_endpgm
150  %vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr
151  %elt1 = extractelement <2 x i16> %vec, i32 1
152  %vecins = insertelement <2 x i16> %vec, i16 %elt, i32 0
153  store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out
154  %use1 = zext i16 %elt1 to i32
155  call void asm sideeffect "; use $0", "s"(i32 %use1) #0
156  ret void
157}
158
159define amdgpu_kernel void @s_insertelement_v2i16_0_reghi(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(4)* %vec.ptr, [8 x i32], i32 %elt.arg) #0 {
160; GFX9-LABEL: s_insertelement_v2i16_0_reghi:
161; GFX9:       ; %bb.0:
162; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
163; GFX9-NEXT:    s_load_dword s4, s[4:5], 0x30
164; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
165; GFX9-NEXT:    v_mov_b32_e32 v0, s0
166; GFX9-NEXT:    s_load_dword s0, s[2:3], 0x0
167; GFX9-NEXT:    v_mov_b32_e32 v1, s1
168; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
169; GFX9-NEXT:    s_pack_hh_b32_b16 s0, s4, s0
170; GFX9-NEXT:    v_mov_b32_e32 v2, s0
171; GFX9-NEXT:    global_store_dword v[0:1], v2, off
172; GFX9-NEXT:    s_endpgm
173;
174; VI-LABEL: s_insertelement_v2i16_0_reghi:
175; VI:       ; %bb.0:
176; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
177; VI-NEXT:    s_load_dword s4, s[4:5], 0x30
178; VI-NEXT:    s_waitcnt lgkmcnt(0)
179; VI-NEXT:    v_mov_b32_e32 v0, s0
180; VI-NEXT:    s_load_dword s0, s[2:3], 0x0
181; VI-NEXT:    v_mov_b32_e32 v1, s1
182; VI-NEXT:    s_lshr_b32 s1, s4, 16
183; VI-NEXT:    s_waitcnt lgkmcnt(0)
184; VI-NEXT:    s_and_b32 s0, s0, 0xffff0000
185; VI-NEXT:    s_or_b32 s0, s1, s0
186; VI-NEXT:    v_mov_b32_e32 v2, s0
187; VI-NEXT:    flat_store_dword v[0:1], v2
188; VI-NEXT:    s_endpgm
189;
190; CI-LABEL: s_insertelement_v2i16_0_reghi:
191; CI:       ; %bb.0:
192; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
193; CI-NEXT:    s_load_dword s4, s[4:5], 0xc
194; CI-NEXT:    s_waitcnt lgkmcnt(0)
195; CI-NEXT:    s_load_dword s2, s[2:3], 0x0
196; CI-NEXT:    v_mov_b32_e32 v0, s0
197; CI-NEXT:    v_mov_b32_e32 v1, s1
198; CI-NEXT:    s_lshr_b32 s1, s4, 16
199; CI-NEXT:    s_waitcnt lgkmcnt(0)
200; CI-NEXT:    s_and_b32 s0, s2, 0xffff0000
201; CI-NEXT:    s_or_b32 s0, s1, s0
202; CI-NEXT:    v_mov_b32_e32 v2, s0
203; CI-NEXT:    flat_store_dword v[0:1], v2
204; CI-NEXT:    s_endpgm
205  %vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr
206  %elt.hi = lshr i32 %elt.arg, 16
207  %elt = trunc i32 %elt.hi to i16
208  %vecins = insertelement <2 x i16> %vec, i16 %elt, i32 0
209  store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out
210  ret void
211}
212
213define amdgpu_kernel void @s_insertelement_v2i16_0_reghi_multi_use_1(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(4)* %vec.ptr, i32 %elt.arg) #0 {
214; GFX9-LABEL: s_insertelement_v2i16_0_reghi_multi_use_1:
215; GFX9:       ; %bb.0:
216; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
217; GFX9-NEXT:    s_load_dword s4, s[4:5], 0x10
218; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
219; GFX9-NEXT:    s_load_dword s2, s[2:3], 0x0
220; GFX9-NEXT:    v_mov_b32_e32 v0, s0
221; GFX9-NEXT:    s_lshr_b32 s0, s4, 16
222; GFX9-NEXT:    v_mov_b32_e32 v1, s1
223; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
224; GFX9-NEXT:    s_pack_lh_b32_b16 s1, s0, s2
225; GFX9-NEXT:    v_mov_b32_e32 v2, s1
226; GFX9-NEXT:    global_store_dword v[0:1], v2, off
227; GFX9-NEXT:    ;;#ASMSTART
228; GFX9-NEXT:    ; use s0
229; GFX9-NEXT:    ;;#ASMEND
230; GFX9-NEXT:    s_endpgm
231;
232; VI-LABEL: s_insertelement_v2i16_0_reghi_multi_use_1:
233; VI:       ; %bb.0:
234; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
235; VI-NEXT:    s_load_dword s4, s[4:5], 0x10
236; VI-NEXT:    s_waitcnt lgkmcnt(0)
237; VI-NEXT:    s_load_dword s2, s[2:3], 0x0
238; VI-NEXT:    v_mov_b32_e32 v0, s0
239; VI-NEXT:    v_mov_b32_e32 v1, s1
240; VI-NEXT:    s_lshr_b32 s0, s4, 16
241; VI-NEXT:    s_waitcnt lgkmcnt(0)
242; VI-NEXT:    s_and_b32 s1, s2, 0xffff0000
243; VI-NEXT:    s_or_b32 s1, s0, s1
244; VI-NEXT:    v_mov_b32_e32 v2, s1
245; VI-NEXT:    flat_store_dword v[0:1], v2
246; VI-NEXT:    ;;#ASMSTART
247; VI-NEXT:    ; use s0
248; VI-NEXT:    ;;#ASMEND
249; VI-NEXT:    s_endpgm
250;
251; CI-LABEL: s_insertelement_v2i16_0_reghi_multi_use_1:
252; CI:       ; %bb.0:
253; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
254; CI-NEXT:    s_load_dword s4, s[4:5], 0x4
255; CI-NEXT:    s_waitcnt lgkmcnt(0)
256; CI-NEXT:    s_load_dword s2, s[2:3], 0x0
257; CI-NEXT:    v_mov_b32_e32 v0, s0
258; CI-NEXT:    v_mov_b32_e32 v1, s1
259; CI-NEXT:    s_lshr_b32 s0, s4, 16
260; CI-NEXT:    s_waitcnt lgkmcnt(0)
261; CI-NEXT:    s_and_b32 s1, s2, 0xffff0000
262; CI-NEXT:    s_or_b32 s1, s0, s1
263; CI-NEXT:    v_mov_b32_e32 v2, s1
264; CI-NEXT:    flat_store_dword v[0:1], v2
265; CI-NEXT:    ;;#ASMSTART
266; CI-NEXT:    ; use s0
267; CI-NEXT:    ;;#ASMEND
268; CI-NEXT:    s_endpgm
269  %vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr
270  %elt.hi = lshr i32 %elt.arg, 16
271  %elt = trunc i32 %elt.hi to i16
272  %vecins = insertelement <2 x i16> %vec, i16 %elt, i32 0
273  store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out
274  %use1 = zext i16 %elt to i32
275  call void asm sideeffect "; use $0", "s"(i32 %use1) #0
276  ret void
277}
278
279define amdgpu_kernel void @s_insertelement_v2i16_0_reghi_both_multi_use_1(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(4)* %vec.ptr, i32 %elt.arg) #0 {
280; GFX9-LABEL: s_insertelement_v2i16_0_reghi_both_multi_use_1:
281; GFX9:       ; %bb.0:
282; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
283; GFX9-NEXT:    s_load_dword s4, s[4:5], 0x10
284; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
285; GFX9-NEXT:    v_mov_b32_e32 v0, s0
286; GFX9-NEXT:    s_load_dword s0, s[2:3], 0x0
287; GFX9-NEXT:    v_mov_b32_e32 v1, s1
288; GFX9-NEXT:    s_lshr_b32 s1, s4, 16
289; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
290; GFX9-NEXT:    s_lshr_b32 s0, s0, 16
291; GFX9-NEXT:    s_pack_ll_b32_b16 s2, s1, s0
292; GFX9-NEXT:    v_mov_b32_e32 v2, s2
293; GFX9-NEXT:    global_store_dword v[0:1], v2, off
294; GFX9-NEXT:    ;;#ASMSTART
295; GFX9-NEXT:    ; use s1
296; GFX9-NEXT:    ;;#ASMEND
297; GFX9-NEXT:    ;;#ASMSTART
298; GFX9-NEXT:    ; use s0
299; GFX9-NEXT:    ;;#ASMEND
300; GFX9-NEXT:    s_endpgm
301;
302; VI-LABEL: s_insertelement_v2i16_0_reghi_both_multi_use_1:
303; VI:       ; %bb.0:
304; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
305; VI-NEXT:    s_load_dword s4, s[4:5], 0x10
306; VI-NEXT:    s_waitcnt lgkmcnt(0)
307; VI-NEXT:    v_mov_b32_e32 v0, s0
308; VI-NEXT:    s_load_dword s0, s[2:3], 0x0
309; VI-NEXT:    v_mov_b32_e32 v1, s1
310; VI-NEXT:    s_lshr_b32 s1, s4, 16
311; VI-NEXT:    s_waitcnt lgkmcnt(0)
312; VI-NEXT:    s_lshr_b32 s2, s0, 16
313; VI-NEXT:    s_and_b32 s0, s0, 0xffff0000
314; VI-NEXT:    s_or_b32 s0, s1, s0
315; VI-NEXT:    v_mov_b32_e32 v2, s0
316; VI-NEXT:    flat_store_dword v[0:1], v2
317; VI-NEXT:    ;;#ASMSTART
318; VI-NEXT:    ; use s1
319; VI-NEXT:    ;;#ASMEND
320; VI-NEXT:    ;;#ASMSTART
321; VI-NEXT:    ; use s2
322; VI-NEXT:    ;;#ASMEND
323; VI-NEXT:    s_endpgm
324;
325; CI-LABEL: s_insertelement_v2i16_0_reghi_both_multi_use_1:
326; CI:       ; %bb.0:
327; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
328; CI-NEXT:    s_load_dword s4, s[4:5], 0x4
329; CI-NEXT:    s_waitcnt lgkmcnt(0)
330; CI-NEXT:    v_mov_b32_e32 v0, s0
331; CI-NEXT:    s_load_dword s0, s[2:3], 0x0
332; CI-NEXT:    v_mov_b32_e32 v2, s4
333; CI-NEXT:    v_mov_b32_e32 v1, s1
334; CI-NEXT:    s_lshr_b32 s1, s4, 16
335; CI-NEXT:    s_waitcnt lgkmcnt(0)
336; CI-NEXT:    s_lshr_b32 s0, s0, 16
337; CI-NEXT:    v_alignbit_b32 v2, s0, v2, 16
338; CI-NEXT:    flat_store_dword v[0:1], v2
339; CI-NEXT:    ;;#ASMSTART
340; CI-NEXT:    ; use s1
341; CI-NEXT:    ;;#ASMEND
342; CI-NEXT:    ;;#ASMSTART
343; CI-NEXT:    ; use s0
344; CI-NEXT:    ;;#ASMEND
345; CI-NEXT:    s_endpgm
346  %vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr
347  %elt.hi = lshr i32 %elt.arg, 16
348  %elt = trunc i32 %elt.hi to i16
349  %vec.hi = extractelement <2 x i16> %vec, i32 1
350  %vecins = insertelement <2 x i16> %vec, i16 %elt, i32 0
351  store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out
352  %use1 = zext i16 %elt to i32
353  %vec.hi.use1 = zext i16 %vec.hi to i32
354
355  call void asm sideeffect "; use $0", "s"(i32 %use1) #0
356  call void asm sideeffect "; use $0", "s"(i32 %vec.hi.use1) #0
357  ret void
358}
359
360define amdgpu_kernel void @s_insertelement_v2i16_1(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(4)* %vec.ptr) #0 {
361; GFX9-LABEL: s_insertelement_v2i16_1:
362; GFX9:       ; %bb.0:
363; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
364; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
365; GFX9-NEXT:    v_mov_b32_e32 v0, s0
366; GFX9-NEXT:    s_load_dword s0, s[2:3], 0x0
367; GFX9-NEXT:    v_mov_b32_e32 v1, s1
368; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
369; GFX9-NEXT:    s_pack_ll_b32_b16 s0, s0, 0x3e7
370; GFX9-NEXT:    v_mov_b32_e32 v2, s0
371; GFX9-NEXT:    global_store_dword v[0:1], v2, off
372; GFX9-NEXT:    s_endpgm
373;
374; CIVI-LABEL: s_insertelement_v2i16_1:
375; CIVI:       ; %bb.0:
376; CIVI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
377; CIVI-NEXT:    s_waitcnt lgkmcnt(0)
378; CIVI-NEXT:    v_mov_b32_e32 v0, s0
379; CIVI-NEXT:    s_load_dword s0, s[2:3], 0x0
380; CIVI-NEXT:    v_mov_b32_e32 v1, s1
381; CIVI-NEXT:    s_waitcnt lgkmcnt(0)
382; CIVI-NEXT:    s_and_b32 s0, s0, 0xffff
383; CIVI-NEXT:    s_or_b32 s0, s0, 0x3e70000
384; CIVI-NEXT:    v_mov_b32_e32 v2, s0
385; CIVI-NEXT:    flat_store_dword v[0:1], v2
386; CIVI-NEXT:    s_endpgm
387  %vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr
388  %vecins = insertelement <2 x i16> %vec, i16 999, i32 1
389  store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out
390  ret void
391}
392
393define amdgpu_kernel void @s_insertelement_v2i16_1_reg(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(4)* %vec.ptr, [8 x i32], i16 %elt) #0 {
394; GFX9-LABEL: s_insertelement_v2i16_1_reg:
395; GFX9:       ; %bb.0:
396; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
397; GFX9-NEXT:    s_load_dword s4, s[4:5], 0x30
398; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
399; GFX9-NEXT:    v_mov_b32_e32 v0, s0
400; GFX9-NEXT:    s_load_dword s0, s[2:3], 0x0
401; GFX9-NEXT:    v_mov_b32_e32 v1, s1
402; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
403; GFX9-NEXT:    s_pack_ll_b32_b16 s0, s0, s4
404; GFX9-NEXT:    v_mov_b32_e32 v2, s0
405; GFX9-NEXT:    global_store_dword v[0:1], v2, off
406; GFX9-NEXT:    s_endpgm
407;
408; VI-LABEL: s_insertelement_v2i16_1_reg:
409; VI:       ; %bb.0:
410; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
411; VI-NEXT:    s_load_dword s4, s[4:5], 0x30
412; VI-NEXT:    s_waitcnt lgkmcnt(0)
413; VI-NEXT:    v_mov_b32_e32 v0, s0
414; VI-NEXT:    s_load_dword s0, s[2:3], 0x0
415; VI-NEXT:    v_mov_b32_e32 v1, s1
416; VI-NEXT:    s_lshl_b32 s1, s4, 16
417; VI-NEXT:    s_waitcnt lgkmcnt(0)
418; VI-NEXT:    s_and_b32 s0, s0, 0xffff
419; VI-NEXT:    s_or_b32 s0, s0, s1
420; VI-NEXT:    v_mov_b32_e32 v2, s0
421; VI-NEXT:    flat_store_dword v[0:1], v2
422; VI-NEXT:    s_endpgm
423;
424; CI-LABEL: s_insertelement_v2i16_1_reg:
425; CI:       ; %bb.0:
426; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
427; CI-NEXT:    s_load_dword s4, s[4:5], 0xc
428; CI-NEXT:    s_waitcnt lgkmcnt(0)
429; CI-NEXT:    s_load_dword s2, s[2:3], 0x0
430; CI-NEXT:    v_mov_b32_e32 v0, s0
431; CI-NEXT:    v_mov_b32_e32 v1, s1
432; CI-NEXT:    s_lshl_b32 s1, s4, 16
433; CI-NEXT:    s_waitcnt lgkmcnt(0)
434; CI-NEXT:    s_and_b32 s0, s2, 0xffff
435; CI-NEXT:    s_or_b32 s0, s0, s1
436; CI-NEXT:    v_mov_b32_e32 v2, s0
437; CI-NEXT:    flat_store_dword v[0:1], v2
438; CI-NEXT:    s_endpgm
439  %vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr
440  %vecins = insertelement <2 x i16> %vec, i16 %elt, i32 1
441  store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out
442  ret void
443}
444
445define amdgpu_kernel void @s_insertelement_v2f16_0(<2 x half> addrspace(1)* %out, <2 x half> addrspace(4)* %vec.ptr) #0 {
446; GFX9-LABEL: s_insertelement_v2f16_0:
447; GFX9:       ; %bb.0:
448; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
449; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
450; GFX9-NEXT:    v_mov_b32_e32 v0, s0
451; GFX9-NEXT:    s_load_dword s0, s[2:3], 0x0
452; GFX9-NEXT:    v_mov_b32_e32 v1, s1
453; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
454; GFX9-NEXT:    s_lshr_b32 s0, s0, 16
455; GFX9-NEXT:    s_pack_ll_b32_b16 s0, 0x4500, s0
456; GFX9-NEXT:    v_mov_b32_e32 v2, s0
457; GFX9-NEXT:    global_store_dword v[0:1], v2, off
458; GFX9-NEXT:    s_endpgm
459;
460; CIVI-LABEL: s_insertelement_v2f16_0:
461; CIVI:       ; %bb.0:
462; CIVI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
463; CIVI-NEXT:    s_waitcnt lgkmcnt(0)
464; CIVI-NEXT:    v_mov_b32_e32 v0, s0
465; CIVI-NEXT:    s_load_dword s0, s[2:3], 0x0
466; CIVI-NEXT:    v_mov_b32_e32 v1, s1
467; CIVI-NEXT:    s_waitcnt lgkmcnt(0)
468; CIVI-NEXT:    s_and_b32 s0, s0, 0xffff0000
469; CIVI-NEXT:    s_or_b32 s0, s0, 0x4500
470; CIVI-NEXT:    v_mov_b32_e32 v2, s0
471; CIVI-NEXT:    flat_store_dword v[0:1], v2
472; CIVI-NEXT:    s_endpgm
473  %vec = load <2 x half>, <2 x half> addrspace(4)* %vec.ptr
474  %vecins = insertelement <2 x half> %vec, half 5.000000e+00, i32 0
475  store <2 x half> %vecins, <2 x half> addrspace(1)* %out
476  ret void
477}
478
479define amdgpu_kernel void @s_insertelement_v2f16_1(<2 x half> addrspace(1)* %out, <2 x half> addrspace(4)* %vec.ptr) #0 {
480; GFX9-LABEL: s_insertelement_v2f16_1:
481; GFX9:       ; %bb.0:
482; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
483; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
484; GFX9-NEXT:    v_mov_b32_e32 v0, s0
485; GFX9-NEXT:    s_load_dword s0, s[2:3], 0x0
486; GFX9-NEXT:    v_mov_b32_e32 v1, s1
487; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
488; GFX9-NEXT:    s_pack_ll_b32_b16 s0, s0, 0x4500
489; GFX9-NEXT:    v_mov_b32_e32 v2, s0
490; GFX9-NEXT:    global_store_dword v[0:1], v2, off
491; GFX9-NEXT:    s_endpgm
492;
493; CIVI-LABEL: s_insertelement_v2f16_1:
494; CIVI:       ; %bb.0:
495; CIVI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
496; CIVI-NEXT:    s_waitcnt lgkmcnt(0)
497; CIVI-NEXT:    v_mov_b32_e32 v0, s0
498; CIVI-NEXT:    s_load_dword s0, s[2:3], 0x0
499; CIVI-NEXT:    v_mov_b32_e32 v1, s1
500; CIVI-NEXT:    s_waitcnt lgkmcnt(0)
501; CIVI-NEXT:    s_and_b32 s0, s0, 0xffff
502; CIVI-NEXT:    s_or_b32 s0, s0, 0x45000000
503; CIVI-NEXT:    v_mov_b32_e32 v2, s0
504; CIVI-NEXT:    flat_store_dword v[0:1], v2
505; CIVI-NEXT:    s_endpgm
506  %vec = load <2 x half>, <2 x half> addrspace(4)* %vec.ptr
507  %vecins = insertelement <2 x half> %vec, half 5.000000e+00, i32 1
508  store <2 x half> %vecins, <2 x half> addrspace(1)* %out
509  ret void
510}
511
512define amdgpu_kernel void @v_insertelement_v2i16_0(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 {
513; GFX9-LABEL: v_insertelement_v2i16_0:
514; GFX9:       ; %bb.0:
515; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
516; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
517; GFX9-NEXT:    v_mov_b32_e32 v2, 0xffff
518; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
519; GFX9-NEXT:    global_load_dword v1, v0, s[2:3]
520; GFX9-NEXT:    s_movk_i32 s2, 0x3e7
521; GFX9-NEXT:    s_waitcnt vmcnt(0)
522; GFX9-NEXT:    v_bfi_b32 v1, v2, s2, v1
523; GFX9-NEXT:    global_store_dword v0, v1, s[0:1]
524; GFX9-NEXT:    s_endpgm
525;
526; VI-LABEL: v_insertelement_v2i16_0:
527; VI:       ; %bb.0:
528; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
529; VI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
530; VI-NEXT:    s_waitcnt lgkmcnt(0)
531; VI-NEXT:    v_mov_b32_e32 v1, s3
532; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v2
533; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
534; VI-NEXT:    flat_load_dword v0, v[0:1]
535; VI-NEXT:    v_mov_b32_e32 v3, s1
536; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v2
537; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
538; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
539; VI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
540; VI-NEXT:    v_or_b32_e32 v0, 0x3e7, v0
541; VI-NEXT:    flat_store_dword v[2:3], v0
542; VI-NEXT:    s_endpgm
543;
544; CI-LABEL: v_insertelement_v2i16_0:
545; CI:       ; %bb.0:
546; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
547; CI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
548; CI-NEXT:    s_waitcnt lgkmcnt(0)
549; CI-NEXT:    v_mov_b32_e32 v1, s3
550; CI-NEXT:    v_add_i32_e32 v0, vcc, s2, v2
551; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
552; CI-NEXT:    flat_load_dword v0, v[0:1]
553; CI-NEXT:    v_mov_b32_e32 v3, s1
554; CI-NEXT:    v_add_i32_e32 v2, vcc, s0, v2
555; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
556; CI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
557; CI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
558; CI-NEXT:    v_or_b32_e32 v0, 0x3e7, v0
559; CI-NEXT:    flat_store_dword v[2:3], v0
560; CI-NEXT:    s_endpgm
561  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
562  %tid.ext = sext i32 %tid to i64
563  %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
564  %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
565  %vec = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
566  %vecins = insertelement <2 x i16> %vec, i16 999, i32 0
567  store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out.gep
568  ret void
569}
570
571define amdgpu_kernel void @v_insertelement_v2i16_0_reghi(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in, i32 %elt.arg) #0 {
572; GFX9-LABEL: v_insertelement_v2i16_0_reghi:
573; GFX9:       ; %bb.0:
574; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
575; GFX9-NEXT:    s_load_dword s4, s[4:5], 0x10
576; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
577; GFX9-NEXT:    v_mov_b32_e32 v3, 0xffff0000
578; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
579; GFX9-NEXT:    global_load_dword v1, v0, s[2:3]
580; GFX9-NEXT:    v_lshrrev_b32_e64 v2, 16, s4
581; GFX9-NEXT:    s_waitcnt vmcnt(0)
582; GFX9-NEXT:    v_and_or_b32 v1, v1, v3, v2
583; GFX9-NEXT:    global_store_dword v0, v1, s[0:1]
584; GFX9-NEXT:    s_endpgm
585;
586; VI-LABEL: v_insertelement_v2i16_0_reghi:
587; VI:       ; %bb.0:
588; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
589; VI-NEXT:    s_load_dword s4, s[4:5], 0x10
590; VI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
591; VI-NEXT:    s_waitcnt lgkmcnt(0)
592; VI-NEXT:    v_mov_b32_e32 v1, s3
593; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v2
594; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
595; VI-NEXT:    flat_load_dword v0, v[0:1]
596; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v2
597; VI-NEXT:    v_mov_b32_e32 v3, s1
598; VI-NEXT:    s_lshr_b32 s0, s4, 16
599; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
600; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
601; VI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
602; VI-NEXT:    v_or_b32_e32 v0, s0, v0
603; VI-NEXT:    flat_store_dword v[2:3], v0
604; VI-NEXT:    s_endpgm
605;
606; CI-LABEL: v_insertelement_v2i16_0_reghi:
607; CI:       ; %bb.0:
608; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
609; CI-NEXT:    s_load_dword s4, s[4:5], 0x4
610; CI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
611; CI-NEXT:    s_waitcnt lgkmcnt(0)
612; CI-NEXT:    v_mov_b32_e32 v1, s3
613; CI-NEXT:    v_add_i32_e32 v0, vcc, s2, v2
614; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
615; CI-NEXT:    flat_load_dword v3, v[0:1]
616; CI-NEXT:    v_add_i32_e32 v0, vcc, s0, v2
617; CI-NEXT:    v_mov_b32_e32 v1, s1
618; CI-NEXT:    s_lshr_b32 s0, s4, 16
619; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
620; CI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
621; CI-NEXT:    v_and_b32_e32 v2, 0xffff0000, v3
622; CI-NEXT:    v_or_b32_e32 v2, s0, v2
623; CI-NEXT:    flat_store_dword v[0:1], v2
624; CI-NEXT:    s_endpgm
625  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
626  %tid.ext = sext i32 %tid to i64
627  %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
628  %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
629  %vec = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
630  %elt.hi = lshr i32 %elt.arg, 16
631  %elt = trunc i32 %elt.hi to i16
632  %vecins = insertelement <2 x i16> %vec, i16 %elt, i32 0
633  store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out.gep
634  ret void
635}
636
637define amdgpu_kernel void @v_insertelement_v2i16_0_inlineimm(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 {
638; GFX9-LABEL: v_insertelement_v2i16_0_inlineimm:
639; GFX9:       ; %bb.0:
640; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
641; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
642; GFX9-NEXT:    v_mov_b32_e32 v2, 0xffff
643; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
644; GFX9-NEXT:    global_load_dword v1, v0, s[2:3]
645; GFX9-NEXT:    s_waitcnt vmcnt(0)
646; GFX9-NEXT:    v_bfi_b32 v1, v2, 53, v1
647; GFX9-NEXT:    global_store_dword v0, v1, s[0:1]
648; GFX9-NEXT:    s_endpgm
649;
650; VI-LABEL: v_insertelement_v2i16_0_inlineimm:
651; VI:       ; %bb.0:
652; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
653; VI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
654; VI-NEXT:    s_waitcnt lgkmcnt(0)
655; VI-NEXT:    v_mov_b32_e32 v1, s3
656; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v2
657; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
658; VI-NEXT:    flat_load_dword v0, v[0:1]
659; VI-NEXT:    v_mov_b32_e32 v3, s1
660; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v2
661; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
662; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
663; VI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
664; VI-NEXT:    v_or_b32_e32 v0, 53, v0
665; VI-NEXT:    flat_store_dword v[2:3], v0
666; VI-NEXT:    s_endpgm
667;
668; CI-LABEL: v_insertelement_v2i16_0_inlineimm:
669; CI:       ; %bb.0:
670; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
671; CI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
672; CI-NEXT:    s_waitcnt lgkmcnt(0)
673; CI-NEXT:    v_mov_b32_e32 v1, s3
674; CI-NEXT:    v_add_i32_e32 v0, vcc, s2, v2
675; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
676; CI-NEXT:    flat_load_dword v0, v[0:1]
677; CI-NEXT:    v_mov_b32_e32 v3, s1
678; CI-NEXT:    v_add_i32_e32 v2, vcc, s0, v2
679; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
680; CI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
681; CI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
682; CI-NEXT:    v_or_b32_e32 v0, 53, v0
683; CI-NEXT:    flat_store_dword v[2:3], v0
684; CI-NEXT:    s_endpgm
685  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
686  %tid.ext = sext i32 %tid to i64
687  %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
688  %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
689  %vec = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
690  %vecins = insertelement <2 x i16> %vec, i16 53, i32 0
691  store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out.gep
692  ret void
693}
694
695; FIXME: fold lshl_or c0, c1, v0 -> or (c0 << c1), v0
696define amdgpu_kernel void @v_insertelement_v2i16_1(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 {
697; GFX9-LABEL: v_insertelement_v2i16_1:
698; GFX9:       ; %bb.0:
699; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
700; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
701; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
702; GFX9-NEXT:    global_load_dword v1, v0, s[2:3]
703; GFX9-NEXT:    s_movk_i32 s2, 0x3e7
704; GFX9-NEXT:    s_waitcnt vmcnt(0)
705; GFX9-NEXT:    v_and_b32_e32 v1, 0xffff, v1
706; GFX9-NEXT:    v_lshl_or_b32 v1, s2, 16, v1
707; GFX9-NEXT:    global_store_dword v0, v1, s[0:1]
708; GFX9-NEXT:    s_endpgm
709;
710; VI-LABEL: v_insertelement_v2i16_1:
711; VI:       ; %bb.0:
712; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
713; VI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
714; VI-NEXT:    s_waitcnt lgkmcnt(0)
715; VI-NEXT:    v_mov_b32_e32 v1, s3
716; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v2
717; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
718; VI-NEXT:    flat_load_dword v0, v[0:1]
719; VI-NEXT:    v_mov_b32_e32 v1, 0x3e70000
720; VI-NEXT:    v_mov_b32_e32 v3, s1
721; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v2
722; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
723; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
724; VI-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
725; VI-NEXT:    flat_store_dword v[2:3], v0
726; VI-NEXT:    s_endpgm
727;
728; CI-LABEL: v_insertelement_v2i16_1:
729; CI:       ; %bb.0:
730; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
731; CI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
732; CI-NEXT:    s_waitcnt lgkmcnt(0)
733; CI-NEXT:    v_mov_b32_e32 v1, s3
734; CI-NEXT:    v_add_i32_e32 v0, vcc, s2, v2
735; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
736; CI-NEXT:    flat_load_dword v0, v[0:1]
737; CI-NEXT:    v_mov_b32_e32 v3, s1
738; CI-NEXT:    v_add_i32_e32 v2, vcc, s0, v2
739; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
740; CI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
741; CI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
742; CI-NEXT:    v_or_b32_e32 v0, 0x3e70000, v0
743; CI-NEXT:    flat_store_dword v[2:3], v0
744; CI-NEXT:    s_endpgm
745  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
746  %tid.ext = sext i32 %tid to i64
747  %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
748  %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
749  %vec = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
750  %vecins = insertelement <2 x i16> %vec, i16 999, i32 1
751  store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out.gep
752  ret void
753}
754
755define amdgpu_kernel void @v_insertelement_v2i16_1_inlineimm(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 {
756; GFX9-LABEL: v_insertelement_v2i16_1_inlineimm:
757; GFX9:       ; %bb.0:
758; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
759; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
760; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
761; GFX9-NEXT:    global_load_dword v1, v0, s[2:3]
762; GFX9-NEXT:    s_waitcnt vmcnt(0)
763; GFX9-NEXT:    v_and_b32_e32 v1, 0xffff, v1
764; GFX9-NEXT:    v_lshl_or_b32 v1, -15, 16, v1
765; GFX9-NEXT:    global_store_dword v0, v1, s[0:1]
766; GFX9-NEXT:    s_endpgm
767;
768; VI-LABEL: v_insertelement_v2i16_1_inlineimm:
769; VI:       ; %bb.0:
770; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
771; VI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
772; VI-NEXT:    s_waitcnt lgkmcnt(0)
773; VI-NEXT:    v_mov_b32_e32 v1, s3
774; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v2
775; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
776; VI-NEXT:    flat_load_dword v0, v[0:1]
777; VI-NEXT:    v_mov_b32_e32 v1, 0xfff10000
778; VI-NEXT:    v_mov_b32_e32 v3, s1
779; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v2
780; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
781; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
782; VI-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
783; VI-NEXT:    flat_store_dword v[2:3], v0
784; VI-NEXT:    s_endpgm
785;
786; CI-LABEL: v_insertelement_v2i16_1_inlineimm:
787; CI:       ; %bb.0:
788; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
789; CI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
790; CI-NEXT:    s_waitcnt lgkmcnt(0)
791; CI-NEXT:    v_mov_b32_e32 v1, s3
792; CI-NEXT:    v_add_i32_e32 v0, vcc, s2, v2
793; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
794; CI-NEXT:    flat_load_dword v0, v[0:1]
795; CI-NEXT:    v_mov_b32_e32 v3, s1
796; CI-NEXT:    v_add_i32_e32 v2, vcc, s0, v2
797; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
798; CI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
799; CI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
800; CI-NEXT:    v_or_b32_e32 v0, 0xfff10000, v0
801; CI-NEXT:    flat_store_dword v[2:3], v0
802; CI-NEXT:    s_endpgm
803  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
804  %tid.ext = sext i32 %tid to i64
805  %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
806  %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
807  %vec = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
808  %vecins = insertelement <2 x i16> %vec, i16 -15, i32 1
809  store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out.gep
810  ret void
811}
812
813define amdgpu_kernel void @v_insertelement_v2f16_0(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in) #0 {
814; GFX9-LABEL: v_insertelement_v2f16_0:
815; GFX9:       ; %bb.0:
816; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
817; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
818; GFX9-NEXT:    v_mov_b32_e32 v2, 0x4500
819; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
820; GFX9-NEXT:    global_load_dword v1, v0, s[2:3]
821; GFX9-NEXT:    s_waitcnt vmcnt(0)
822; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
823; GFX9-NEXT:    v_lshl_or_b32 v1, v1, 16, v2
824; GFX9-NEXT:    global_store_dword v0, v1, s[0:1]
825; GFX9-NEXT:    s_endpgm
826;
827; VI-LABEL: v_insertelement_v2f16_0:
828; VI:       ; %bb.0:
829; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
830; VI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
831; VI-NEXT:    s_waitcnt lgkmcnt(0)
832; VI-NEXT:    v_mov_b32_e32 v1, s3
833; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v2
834; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
835; VI-NEXT:    flat_load_dword v0, v[0:1]
836; VI-NEXT:    v_mov_b32_e32 v3, s1
837; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v2
838; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
839; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
840; VI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
841; VI-NEXT:    v_or_b32_e32 v0, 0x4500, v0
842; VI-NEXT:    flat_store_dword v[2:3], v0
843; VI-NEXT:    s_endpgm
844;
845; CI-LABEL: v_insertelement_v2f16_0:
846; CI:       ; %bb.0:
847; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
848; CI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
849; CI-NEXT:    s_waitcnt lgkmcnt(0)
850; CI-NEXT:    v_mov_b32_e32 v1, s3
851; CI-NEXT:    v_add_i32_e32 v0, vcc, s2, v2
852; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
853; CI-NEXT:    flat_load_dword v0, v[0:1]
854; CI-NEXT:    v_mov_b32_e32 v3, s1
855; CI-NEXT:    v_add_i32_e32 v2, vcc, s0, v2
856; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
857; CI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
858; CI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
859; CI-NEXT:    v_or_b32_e32 v0, 0x4500, v0
860; CI-NEXT:    flat_store_dword v[2:3], v0
861; CI-NEXT:    s_endpgm
862  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
863  %tid.ext = sext i32 %tid to i64
864  %in.gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %in, i64 %tid.ext
865  %out.gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %out, i64 %tid.ext
866  %vec = load <2 x half>, <2 x half> addrspace(1)* %in.gep
867  %vecins = insertelement <2 x half> %vec, half 5.000000e+00, i32 0
868  store <2 x half> %vecins, <2 x half> addrspace(1)* %out.gep
869  ret void
870}
871
872define amdgpu_kernel void @v_insertelement_v2f16_0_inlineimm(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in) #0 {
873; GFX9-LABEL: v_insertelement_v2f16_0_inlineimm:
874; GFX9:       ; %bb.0:
875; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
876; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
877; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
878; GFX9-NEXT:    global_load_dword v1, v0, s[2:3]
879; GFX9-NEXT:    s_waitcnt vmcnt(0)
880; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
881; GFX9-NEXT:    v_lshl_or_b32 v1, v1, 16, 53
882; GFX9-NEXT:    global_store_dword v0, v1, s[0:1]
883; GFX9-NEXT:    s_endpgm
884;
885; VI-LABEL: v_insertelement_v2f16_0_inlineimm:
886; VI:       ; %bb.0:
887; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
888; VI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
889; VI-NEXT:    s_waitcnt lgkmcnt(0)
890; VI-NEXT:    v_mov_b32_e32 v1, s3
891; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v2
892; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
893; VI-NEXT:    flat_load_dword v0, v[0:1]
894; VI-NEXT:    v_mov_b32_e32 v3, s1
895; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v2
896; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
897; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
898; VI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
899; VI-NEXT:    v_or_b32_e32 v0, 53, v0
900; VI-NEXT:    flat_store_dword v[2:3], v0
901; VI-NEXT:    s_endpgm
902;
903; CI-LABEL: v_insertelement_v2f16_0_inlineimm:
904; CI:       ; %bb.0:
905; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
906; CI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
907; CI-NEXT:    s_waitcnt lgkmcnt(0)
908; CI-NEXT:    v_mov_b32_e32 v1, s3
909; CI-NEXT:    v_add_i32_e32 v0, vcc, s2, v2
910; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
911; CI-NEXT:    flat_load_dword v0, v[0:1]
912; CI-NEXT:    v_mov_b32_e32 v3, s1
913; CI-NEXT:    v_add_i32_e32 v2, vcc, s0, v2
914; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
915; CI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
916; CI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
917; CI-NEXT:    v_or_b32_e32 v0, 53, v0
918; CI-NEXT:    flat_store_dword v[2:3], v0
919; CI-NEXT:    s_endpgm
920  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
921  %tid.ext = sext i32 %tid to i64
922  %in.gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %in, i64 %tid.ext
923  %out.gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %out, i64 %tid.ext
924  %vec = load <2 x half>, <2 x half> addrspace(1)* %in.gep
925  %vecins = insertelement <2 x half> %vec, half 0xH0035, i32 0
926  store <2 x half> %vecins, <2 x half> addrspace(1)* %out.gep
927  ret void
928}
929
930define amdgpu_kernel void @v_insertelement_v2f16_1(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in) #0 {
931; GFX9-LABEL: v_insertelement_v2f16_1:
932; GFX9:       ; %bb.0:
933; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
934; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
935; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
936; GFX9-NEXT:    global_load_dword v1, v0, s[2:3]
937; GFX9-NEXT:    s_movk_i32 s2, 0x4500
938; GFX9-NEXT:    s_waitcnt vmcnt(0)
939; GFX9-NEXT:    v_and_b32_e32 v1, 0xffff, v1
940; GFX9-NEXT:    v_lshl_or_b32 v1, s2, 16, v1
941; GFX9-NEXT:    global_store_dword v0, v1, s[0:1]
942; GFX9-NEXT:    s_endpgm
943;
944; VI-LABEL: v_insertelement_v2f16_1:
945; VI:       ; %bb.0:
946; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
947; VI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
948; VI-NEXT:    s_waitcnt lgkmcnt(0)
949; VI-NEXT:    v_mov_b32_e32 v1, s3
950; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v2
951; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
952; VI-NEXT:    flat_load_dword v0, v[0:1]
953; VI-NEXT:    v_mov_b32_e32 v1, 0x45000000
954; VI-NEXT:    v_mov_b32_e32 v3, s1
955; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v2
956; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
957; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
958; VI-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
959; VI-NEXT:    flat_store_dword v[2:3], v0
960; VI-NEXT:    s_endpgm
961;
962; CI-LABEL: v_insertelement_v2f16_1:
963; CI:       ; %bb.0:
964; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
965; CI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
966; CI-NEXT:    s_waitcnt lgkmcnt(0)
967; CI-NEXT:    v_mov_b32_e32 v1, s3
968; CI-NEXT:    v_add_i32_e32 v0, vcc, s2, v2
969; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
970; CI-NEXT:    flat_load_dword v0, v[0:1]
971; CI-NEXT:    v_mov_b32_e32 v3, s1
972; CI-NEXT:    v_add_i32_e32 v2, vcc, s0, v2
973; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
974; CI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
975; CI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
976; CI-NEXT:    v_or_b32_e32 v0, 0x45000000, v0
977; CI-NEXT:    flat_store_dword v[2:3], v0
978; CI-NEXT:    s_endpgm
979  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
980  %tid.ext = sext i32 %tid to i64
981  %in.gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %in, i64 %tid.ext
982  %out.gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %out, i64 %tid.ext
983  %vec = load <2 x half>, <2 x half> addrspace(1)* %in.gep
984  %vecins = insertelement <2 x half> %vec, half 5.000000e+00, i32 1
985  store <2 x half> %vecins, <2 x half> addrspace(1)* %out.gep
986  ret void
987}
988
989define amdgpu_kernel void @v_insertelement_v2f16_1_inlineimm(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in) #0 {
990; GFX9-LABEL: v_insertelement_v2f16_1_inlineimm:
991; GFX9:       ; %bb.0:
992; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
993; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
994; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
995; GFX9-NEXT:    global_load_dword v1, v0, s[2:3]
996; GFX9-NEXT:    s_waitcnt vmcnt(0)
997; GFX9-NEXT:    v_and_b32_e32 v1, 0xffff, v1
998; GFX9-NEXT:    v_lshl_or_b32 v1, 35, 16, v1
999; GFX9-NEXT:    global_store_dword v0, v1, s[0:1]
1000; GFX9-NEXT:    s_endpgm
1001;
1002; VI-LABEL: v_insertelement_v2f16_1_inlineimm:
1003; VI:       ; %bb.0:
1004; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
1005; VI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
1006; VI-NEXT:    s_waitcnt lgkmcnt(0)
1007; VI-NEXT:    v_mov_b32_e32 v1, s3
1008; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v2
1009; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1010; VI-NEXT:    flat_load_dword v0, v[0:1]
1011; VI-NEXT:    v_mov_b32_e32 v1, 0x230000
1012; VI-NEXT:    v_mov_b32_e32 v3, s1
1013; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v2
1014; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
1015; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
1016; VI-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
1017; VI-NEXT:    flat_store_dword v[2:3], v0
1018; VI-NEXT:    s_endpgm
1019;
1020; CI-LABEL: v_insertelement_v2f16_1_inlineimm:
1021; CI:       ; %bb.0:
1022; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
1023; CI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
1024; CI-NEXT:    s_waitcnt lgkmcnt(0)
1025; CI-NEXT:    v_mov_b32_e32 v1, s3
1026; CI-NEXT:    v_add_i32_e32 v0, vcc, s2, v2
1027; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1028; CI-NEXT:    flat_load_dword v0, v[0:1]
1029; CI-NEXT:    v_mov_b32_e32 v3, s1
1030; CI-NEXT:    v_add_i32_e32 v2, vcc, s0, v2
1031; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
1032; CI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
1033; CI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
1034; CI-NEXT:    v_or_b32_e32 v0, 0x230000, v0
1035; CI-NEXT:    flat_store_dword v[2:3], v0
1036; CI-NEXT:    s_endpgm
1037  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
1038  %tid.ext = sext i32 %tid to i64
1039  %in.gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %in, i64 %tid.ext
1040  %out.gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %out, i64 %tid.ext
1041  %vec = load <2 x half>, <2 x half> addrspace(1)* %in.gep
1042  %vecins = insertelement <2 x half> %vec, half 0xH0023, i32 1
1043  store <2 x half> %vecins, <2 x half> addrspace(1)* %out.gep
1044  ret void
1045}
1046
1047; FIXME: Enable for others when argument load not split
1048define amdgpu_kernel void @s_insertelement_v2i16_dynamic(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(4)* %vec.ptr, i32 addrspace(4)* %idx.ptr) #0 {
1049; GFX9-LABEL: s_insertelement_v2i16_dynamic:
1050; GFX9:       ; %bb.0:
1051; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
1052; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x10
1053; GFX9-NEXT:    v_mov_b32_e32 v2, 0x3e703e7
1054; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
1055; GFX9-NEXT:    v_mov_b32_e32 v0, s0
1056; GFX9-NEXT:    s_load_dword s4, s[4:5], 0x0
1057; GFX9-NEXT:    s_load_dword s2, s[2:3], 0x0
1058; GFX9-NEXT:    v_mov_b32_e32 v1, s1
1059; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
1060; GFX9-NEXT:    s_lshl_b32 s0, s4, 4
1061; GFX9-NEXT:    s_lshl_b32 s0, 0xffff, s0
1062; GFX9-NEXT:    v_mov_b32_e32 v3, s2
1063; GFX9-NEXT:    v_bfi_b32 v2, s0, v2, v3
1064; GFX9-NEXT:    global_store_dword v[0:1], v2, off
1065; GFX9-NEXT:    s_endpgm
1066;
1067; VI-LABEL: s_insertelement_v2i16_dynamic:
1068; VI:       ; %bb.0:
1069; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
1070; VI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x10
1071; VI-NEXT:    v_mov_b32_e32 v2, 0x3e703e7
1072; VI-NEXT:    s_waitcnt lgkmcnt(0)
1073; VI-NEXT:    v_mov_b32_e32 v0, s0
1074; VI-NEXT:    s_load_dword s4, s[4:5], 0x0
1075; VI-NEXT:    s_load_dword s2, s[2:3], 0x0
1076; VI-NEXT:    v_mov_b32_e32 v1, s1
1077; VI-NEXT:    s_waitcnt lgkmcnt(0)
1078; VI-NEXT:    s_lshl_b32 s0, s4, 4
1079; VI-NEXT:    s_lshl_b32 s0, 0xffff, s0
1080; VI-NEXT:    v_mov_b32_e32 v3, s2
1081; VI-NEXT:    v_bfi_b32 v2, s0, v2, v3
1082; VI-NEXT:    flat_store_dword v[0:1], v2
1083; VI-NEXT:    s_endpgm
1084;
1085; CI-LABEL: s_insertelement_v2i16_dynamic:
1086; CI:       ; %bb.0:
1087; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
1088; CI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x4
1089; CI-NEXT:    v_mov_b32_e32 v2, 0x3e703e7
1090; CI-NEXT:    s_waitcnt lgkmcnt(0)
1091; CI-NEXT:    v_mov_b32_e32 v0, s0
1092; CI-NEXT:    s_load_dword s4, s[4:5], 0x0
1093; CI-NEXT:    s_load_dword s2, s[2:3], 0x0
1094; CI-NEXT:    v_mov_b32_e32 v1, s1
1095; CI-NEXT:    s_waitcnt lgkmcnt(0)
1096; CI-NEXT:    s_lshl_b32 s0, s4, 4
1097; CI-NEXT:    s_lshl_b32 s0, 0xffff, s0
1098; CI-NEXT:    v_mov_b32_e32 v3, s2
1099; CI-NEXT:    v_bfi_b32 v2, s0, v2, v3
1100; CI-NEXT:    flat_store_dword v[0:1], v2
1101; CI-NEXT:    s_endpgm
1102  %idx = load volatile i32, i32 addrspace(4)* %idx.ptr
1103  %vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr
1104  %vecins = insertelement <2 x i16> %vec, i16 999, i32 %idx
1105  store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out
1106  ret void
1107}
1108
1109define amdgpu_kernel void @v_insertelement_v2i16_dynamic_sgpr(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in, i32 %idx) #0 {
1110; GFX9-LABEL: v_insertelement_v2i16_dynamic_sgpr:
1111; GFX9:       ; %bb.0:
1112; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
1113; GFX9-NEXT:    s_load_dword s4, s[4:5], 0x10
1114; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
1115; GFX9-NEXT:    v_mov_b32_e32 v2, 0x3e703e7
1116; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
1117; GFX9-NEXT:    global_load_dword v1, v0, s[2:3]
1118; GFX9-NEXT:    s_lshl_b32 s2, s4, 4
1119; GFX9-NEXT:    s_lshl_b32 s2, 0xffff, s2
1120; GFX9-NEXT:    s_waitcnt vmcnt(0)
1121; GFX9-NEXT:    v_bfi_b32 v1, s2, v2, v1
1122; GFX9-NEXT:    global_store_dword v0, v1, s[0:1]
1123; GFX9-NEXT:    s_endpgm
1124;
1125; VI-LABEL: v_insertelement_v2i16_dynamic_sgpr:
1126; VI:       ; %bb.0:
1127; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
1128; VI-NEXT:    s_load_dword s4, s[4:5], 0x10
1129; VI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
1130; VI-NEXT:    s_waitcnt lgkmcnt(0)
1131; VI-NEXT:    v_mov_b32_e32 v1, s3
1132; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v2
1133; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1134; VI-NEXT:    flat_load_dword v0, v[0:1]
1135; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v2
1136; VI-NEXT:    s_lshl_b32 s0, s4, 4
1137; VI-NEXT:    v_mov_b32_e32 v3, s1
1138; VI-NEXT:    s_lshl_b32 s0, 0xffff, s0
1139; VI-NEXT:    v_mov_b32_e32 v1, 0x3e703e7
1140; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
1141; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
1142; VI-NEXT:    v_bfi_b32 v0, s0, v1, v0
1143; VI-NEXT:    flat_store_dword v[2:3], v0
1144; VI-NEXT:    s_endpgm
1145;
1146; CI-LABEL: v_insertelement_v2i16_dynamic_sgpr:
1147; CI:       ; %bb.0:
1148; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
1149; CI-NEXT:    s_load_dword s4, s[4:5], 0x4
1150; CI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
1151; CI-NEXT:    s_waitcnt lgkmcnt(0)
1152; CI-NEXT:    v_mov_b32_e32 v1, s3
1153; CI-NEXT:    v_add_i32_e32 v0, vcc, s2, v2
1154; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1155; CI-NEXT:    flat_load_dword v0, v[0:1]
1156; CI-NEXT:    v_add_i32_e32 v2, vcc, s0, v2
1157; CI-NEXT:    s_lshl_b32 s0, s4, 4
1158; CI-NEXT:    v_mov_b32_e32 v3, s1
1159; CI-NEXT:    s_lshl_b32 s0, 0xffff, s0
1160; CI-NEXT:    v_mov_b32_e32 v1, 0x3e703e7
1161; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
1162; CI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
1163; CI-NEXT:    v_bfi_b32 v0, s0, v1, v0
1164; CI-NEXT:    flat_store_dword v[2:3], v0
1165; CI-NEXT:    s_endpgm
1166  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
1167  %tid.ext = sext i32 %tid to i64
1168  %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
1169  %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
1170  %vec = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
1171  %vecins = insertelement <2 x i16> %vec, i16 999, i32 %idx
1172  store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out.gep
1173  ret void
1174}
1175
1176define amdgpu_kernel void @v_insertelement_v2f16_dynamic_vgpr(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in, i32 addrspace(1)* %idx.ptr) #0 {
1177; GFX9-LABEL: v_insertelement_v2f16_dynamic_vgpr:
1178; GFX9:       ; %bb.0:
1179; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
1180; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x10
1181; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
1182; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
1183; GFX9-NEXT:    global_load_dword v1, v0, s[4:5]
1184; GFX9-NEXT:    global_load_dword v2, v0, s[2:3]
1185; GFX9-NEXT:    s_mov_b32 s2, 0xffff
1186; GFX9-NEXT:    s_waitcnt vmcnt(1)
1187; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 4, v1
1188; GFX9-NEXT:    v_lshlrev_b32_e64 v1, v1, s2
1189; GFX9-NEXT:    s_mov_b32 s2, 0x12341234
1190; GFX9-NEXT:    s_waitcnt vmcnt(0)
1191; GFX9-NEXT:    v_bfi_b32 v1, v1, s2, v2
1192; GFX9-NEXT:    global_store_dword v0, v1, s[0:1]
1193; GFX9-NEXT:    s_endpgm
1194;
1195; VI-LABEL: v_insertelement_v2f16_dynamic_vgpr:
1196; VI:       ; %bb.0:
1197; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
1198; VI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x10
1199; VI-NEXT:    v_lshlrev_b32_e32 v4, 2, v0
1200; VI-NEXT:    s_waitcnt lgkmcnt(0)
1201; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v4
1202; VI-NEXT:    v_mov_b32_e32 v1, s3
1203; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1204; VI-NEXT:    v_mov_b32_e32 v3, s5
1205; VI-NEXT:    v_add_u32_e32 v2, vcc, s4, v4
1206; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
1207; VI-NEXT:    flat_load_dword v2, v[2:3]
1208; VI-NEXT:    flat_load_dword v3, v[0:1]
1209; VI-NEXT:    s_mov_b32 s2, 0xffff
1210; VI-NEXT:    v_add_u32_e32 v0, vcc, s0, v4
1211; VI-NEXT:    v_mov_b32_e32 v1, s1
1212; VI-NEXT:    s_mov_b32 s0, 0x12341234
1213; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1214; VI-NEXT:    s_waitcnt vmcnt(1) lgkmcnt(1)
1215; VI-NEXT:    v_lshlrev_b32_e32 v2, 4, v2
1216; VI-NEXT:    v_lshlrev_b32_e64 v2, v2, s2
1217; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
1218; VI-NEXT:    v_bfi_b32 v2, v2, s0, v3
1219; VI-NEXT:    flat_store_dword v[0:1], v2
1220; VI-NEXT:    s_endpgm
1221;
1222; CI-LABEL: v_insertelement_v2f16_dynamic_vgpr:
1223; CI:       ; %bb.0:
1224; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
1225; CI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x4
1226; CI-NEXT:    v_lshlrev_b32_e32 v4, 2, v0
1227; CI-NEXT:    s_waitcnt lgkmcnt(0)
1228; CI-NEXT:    v_mov_b32_e32 v1, s3
1229; CI-NEXT:    v_add_i32_e32 v0, vcc, s2, v4
1230; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1231; CI-NEXT:    v_mov_b32_e32 v3, s5
1232; CI-NEXT:    v_add_i32_e32 v2, vcc, s4, v4
1233; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
1234; CI-NEXT:    flat_load_dword v2, v[2:3]
1235; CI-NEXT:    flat_load_dword v3, v[0:1]
1236; CI-NEXT:    v_add_i32_e32 v0, vcc, s0, v4
1237; CI-NEXT:    v_mov_b32_e32 v1, s1
1238; CI-NEXT:    s_mov_b32 s0, 0x12341234
1239; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1240; CI-NEXT:    s_waitcnt vmcnt(1) lgkmcnt(1)
1241; CI-NEXT:    v_lshlrev_b32_e32 v2, 4, v2
1242; CI-NEXT:    v_lshl_b32_e32 v2, 0xffff, v2
1243; CI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
1244; CI-NEXT:    v_bfi_b32 v2, v2, s0, v3
1245; CI-NEXT:    flat_store_dword v[0:1], v2
1246; CI-NEXT:    s_endpgm
1247  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
1248  %tid.ext = sext i32 %tid to i64
1249  %in.gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %in, i64 %tid.ext
1250  %idx.gep = getelementptr inbounds i32, i32 addrspace(1)* %idx.ptr, i64 %tid.ext
1251  %out.gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %out, i64 %tid.ext
1252  %idx = load i32, i32 addrspace(1)* %idx.gep
1253  %vec = load <2 x half>, <2 x half> addrspace(1)* %in.gep
1254  %vecins = insertelement <2 x half> %vec, half 0xH1234, i32 %idx
1255  store <2 x half> %vecins, <2 x half> addrspace(1)* %out.gep
1256  ret void
1257}
1258
1259define amdgpu_kernel void @v_insertelement_v4f16_0(<4 x half> addrspace(1)* %out, <4 x half> addrspace(1)* %in, [8 x i32], i32 %val) #0 {
1260; GFX9-LABEL: v_insertelement_v4f16_0:
1261; GFX9:       ; %bb.0:
1262; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
1263; GFX9-NEXT:    s_load_dword s4, s[4:5], 0x30
1264; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
1265; GFX9-NEXT:    v_mov_b32_e32 v3, 0xffff
1266; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
1267; GFX9-NEXT:    global_load_dwordx2 v[0:1], v2, s[2:3]
1268; GFX9-NEXT:    s_waitcnt vmcnt(0)
1269; GFX9-NEXT:    v_bfi_b32 v0, v3, s4, v0
1270; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
1271; GFX9-NEXT:    s_endpgm
1272;
1273; VI-LABEL: v_insertelement_v4f16_0:
1274; VI:       ; %bb.0:
1275; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
1276; VI-NEXT:    s_load_dword s4, s[4:5], 0x30
1277; VI-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
1278; VI-NEXT:    s_waitcnt lgkmcnt(0)
1279; VI-NEXT:    v_mov_b32_e32 v1, s3
1280; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v2
1281; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1282; VI-NEXT:    flat_load_dwordx2 v[0:1], v[0:1]
1283; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v2
1284; VI-NEXT:    v_mov_b32_e32 v3, s1
1285; VI-NEXT:    s_and_b32 s0, s4, 0xffff
1286; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
1287; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
1288; VI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
1289; VI-NEXT:    v_or_b32_e32 v0, s0, v0
1290; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
1291; VI-NEXT:    s_endpgm
1292;
1293; CI-LABEL: v_insertelement_v4f16_0:
1294; CI:       ; %bb.0:
1295; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
1296; CI-NEXT:    s_load_dword s4, s[4:5], 0xc
1297; CI-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
1298; CI-NEXT:    s_waitcnt lgkmcnt(0)
1299; CI-NEXT:    v_mov_b32_e32 v1, s3
1300; CI-NEXT:    v_add_i32_e32 v0, vcc, s2, v2
1301; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1302; CI-NEXT:    flat_load_dwordx2 v[0:1], v[0:1]
1303; CI-NEXT:    v_add_i32_e32 v2, vcc, s0, v2
1304; CI-NEXT:    v_mov_b32_e32 v3, s1
1305; CI-NEXT:    s_and_b32 s0, s4, 0xffff
1306; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
1307; CI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
1308; CI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
1309; CI-NEXT:    v_or_b32_e32 v0, s0, v0
1310; CI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
1311; CI-NEXT:    s_endpgm
1312  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
1313  %tid.ext = sext i32 %tid to i64
1314  %in.gep = getelementptr inbounds <4 x half>, <4 x half> addrspace(1)* %in, i64 %tid.ext
1315  %out.gep = getelementptr inbounds <4 x half>, <4 x half> addrspace(1)* %out, i64 %tid.ext
1316  %vec = load <4 x half>, <4 x half> addrspace(1)* %in.gep
1317  %val.trunc = trunc i32 %val to i16
1318  %val.cvt = bitcast i16 %val.trunc to half
1319  %vecins = insertelement <4 x half> %vec, half %val.cvt, i32 0
1320  store <4 x half> %vecins, <4 x half> addrspace(1)* %out.gep
1321  ret void
1322}
1323
1324define amdgpu_kernel void @v_insertelement_v4f16_1(<4 x half> addrspace(1)* %out, <4 x half> addrspace(1)* %in, i32 %val) #0 {
1325; GFX9-LABEL: v_insertelement_v4f16_1:
1326; GFX9:       ; %bb.0:
1327; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
1328; GFX9-NEXT:    s_load_dword s4, s[4:5], 0x10
1329; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
1330; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
1331; GFX9-NEXT:    global_load_dwordx2 v[0:1], v2, s[2:3]
1332; GFX9-NEXT:    s_waitcnt vmcnt(0)
1333; GFX9-NEXT:    v_and_b32_e32 v0, 0xffff, v0
1334; GFX9-NEXT:    v_lshl_or_b32 v0, s4, 16, v0
1335; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
1336; GFX9-NEXT:    s_endpgm
1337;
1338; VI-LABEL: v_insertelement_v4f16_1:
1339; VI:       ; %bb.0:
1340; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
1341; VI-NEXT:    s_load_dword s4, s[4:5], 0x10
1342; VI-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
1343; VI-NEXT:    s_waitcnt lgkmcnt(0)
1344; VI-NEXT:    v_mov_b32_e32 v1, s3
1345; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v2
1346; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1347; VI-NEXT:    flat_load_dwordx2 v[0:1], v[0:1]
1348; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v2
1349; VI-NEXT:    s_lshl_b32 s0, s4, 16
1350; VI-NEXT:    v_mov_b32_e32 v3, s1
1351; VI-NEXT:    v_mov_b32_e32 v4, s0
1352; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
1353; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
1354; VI-NEXT:    v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
1355; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
1356; VI-NEXT:    s_endpgm
1357;
1358; CI-LABEL: v_insertelement_v4f16_1:
1359; CI:       ; %bb.0:
1360; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
1361; CI-NEXT:    s_load_dword s4, s[4:5], 0x4
1362; CI-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
1363; CI-NEXT:    s_waitcnt lgkmcnt(0)
1364; CI-NEXT:    v_mov_b32_e32 v1, s3
1365; CI-NEXT:    v_add_i32_e32 v0, vcc, s2, v2
1366; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1367; CI-NEXT:    flat_load_dwordx2 v[0:1], v[0:1]
1368; CI-NEXT:    v_add_i32_e32 v2, vcc, s0, v2
1369; CI-NEXT:    v_mov_b32_e32 v3, s1
1370; CI-NEXT:    s_lshl_b32 s0, s4, 16
1371; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
1372; CI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
1373; CI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
1374; CI-NEXT:    v_or_b32_e32 v0, s0, v0
1375; CI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
1376; CI-NEXT:    s_endpgm
1377  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
1378  %tid.ext = sext i32 %tid to i64
1379  %in.gep = getelementptr inbounds <4 x half>, <4 x half> addrspace(1)* %in, i64 %tid.ext
1380  %out.gep = getelementptr inbounds <4 x half>, <4 x half> addrspace(1)* %out, i64 %tid.ext
1381  %vec = load <4 x half>, <4 x half> addrspace(1)* %in.gep
1382  %val.trunc = trunc i32 %val to i16
1383  %val.cvt = bitcast i16 %val.trunc to half
1384  %vecins = insertelement <4 x half> %vec, half %val.cvt, i32 1
1385  store <4 x half> %vecins, <4 x half> addrspace(1)* %out.gep
1386  ret void
1387}
1388
1389define amdgpu_kernel void @v_insertelement_v4f16_2(<4 x half> addrspace(1)* %out, <4 x half> addrspace(1)* %in, [8 x i32], i32 %val) #0 {
1390; GFX9-LABEL: v_insertelement_v4f16_2:
1391; GFX9:       ; %bb.0:
1392; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
1393; GFX9-NEXT:    s_load_dword s4, s[4:5], 0x30
1394; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
1395; GFX9-NEXT:    v_mov_b32_e32 v3, 0xffff
1396; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
1397; GFX9-NEXT:    global_load_dwordx2 v[0:1], v2, s[2:3]
1398; GFX9-NEXT:    s_waitcnt vmcnt(0)
1399; GFX9-NEXT:    v_bfi_b32 v1, v3, s4, v1
1400; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
1401; GFX9-NEXT:    s_endpgm
1402;
1403; VI-LABEL: v_insertelement_v4f16_2:
1404; VI:       ; %bb.0:
1405; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
1406; VI-NEXT:    s_load_dword s4, s[4:5], 0x30
1407; VI-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
1408; VI-NEXT:    s_waitcnt lgkmcnt(0)
1409; VI-NEXT:    v_mov_b32_e32 v1, s3
1410; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v2
1411; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1412; VI-NEXT:    flat_load_dwordx2 v[0:1], v[0:1]
1413; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v2
1414; VI-NEXT:    v_mov_b32_e32 v3, s1
1415; VI-NEXT:    s_and_b32 s0, s4, 0xffff
1416; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
1417; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
1418; VI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
1419; VI-NEXT:    v_or_b32_e32 v1, s0, v1
1420; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
1421; VI-NEXT:    s_endpgm
1422;
1423; CI-LABEL: v_insertelement_v4f16_2:
1424; CI:       ; %bb.0:
1425; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
1426; CI-NEXT:    s_load_dword s4, s[4:5], 0xc
1427; CI-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
1428; CI-NEXT:    s_waitcnt lgkmcnt(0)
1429; CI-NEXT:    v_mov_b32_e32 v1, s3
1430; CI-NEXT:    v_add_i32_e32 v0, vcc, s2, v2
1431; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1432; CI-NEXT:    flat_load_dwordx2 v[0:1], v[0:1]
1433; CI-NEXT:    v_add_i32_e32 v2, vcc, s0, v2
1434; CI-NEXT:    v_mov_b32_e32 v3, s1
1435; CI-NEXT:    s_and_b32 s0, s4, 0xffff
1436; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
1437; CI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
1438; CI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
1439; CI-NEXT:    v_or_b32_e32 v1, s0, v1
1440; CI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
1441; CI-NEXT:    s_endpgm
1442  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
1443  %tid.ext = sext i32 %tid to i64
1444  %in.gep = getelementptr inbounds <4 x half>, <4 x half> addrspace(1)* %in, i64 %tid.ext
1445  %out.gep = getelementptr inbounds <4 x half>, <4 x half> addrspace(1)* %out, i64 %tid.ext
1446  %vec = load <4 x half>, <4 x half> addrspace(1)* %in.gep
1447  %val.trunc = trunc i32 %val to i16
1448  %val.cvt = bitcast i16 %val.trunc to half
1449  %vecins = insertelement <4 x half> %vec, half %val.cvt, i32 2
1450  store <4 x half> %vecins, <4 x half> addrspace(1)* %out.gep
1451  ret void
1452}
1453
1454define amdgpu_kernel void @v_insertelement_v4f16_3(<4 x half> addrspace(1)* %out, <4 x half> addrspace(1)* %in, i32 %val) #0 {
1455; GFX9-LABEL: v_insertelement_v4f16_3:
1456; GFX9:       ; %bb.0:
1457; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
1458; GFX9-NEXT:    s_load_dword s4, s[4:5], 0x10
1459; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
1460; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
1461; GFX9-NEXT:    global_load_dwordx2 v[0:1], v2, s[2:3]
1462; GFX9-NEXT:    s_waitcnt vmcnt(0)
1463; GFX9-NEXT:    v_and_b32_e32 v1, 0xffff, v1
1464; GFX9-NEXT:    v_lshl_or_b32 v1, s4, 16, v1
1465; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
1466; GFX9-NEXT:    s_endpgm
1467;
1468; VI-LABEL: v_insertelement_v4f16_3:
1469; VI:       ; %bb.0:
1470; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
1471; VI-NEXT:    s_load_dword s4, s[4:5], 0x10
1472; VI-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
1473; VI-NEXT:    s_waitcnt lgkmcnt(0)
1474; VI-NEXT:    v_mov_b32_e32 v1, s3
1475; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v2
1476; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1477; VI-NEXT:    flat_load_dwordx2 v[0:1], v[0:1]
1478; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v2
1479; VI-NEXT:    s_lshl_b32 s0, s4, 16
1480; VI-NEXT:    v_mov_b32_e32 v3, s1
1481; VI-NEXT:    v_mov_b32_e32 v4, s0
1482; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
1483; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
1484; VI-NEXT:    v_or_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
1485; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
1486; VI-NEXT:    s_endpgm
1487;
1488; CI-LABEL: v_insertelement_v4f16_3:
1489; CI:       ; %bb.0:
1490; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
1491; CI-NEXT:    s_load_dword s4, s[4:5], 0x4
1492; CI-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
1493; CI-NEXT:    s_waitcnt lgkmcnt(0)
1494; CI-NEXT:    v_mov_b32_e32 v1, s3
1495; CI-NEXT:    v_add_i32_e32 v0, vcc, s2, v2
1496; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1497; CI-NEXT:    flat_load_dwordx2 v[0:1], v[0:1]
1498; CI-NEXT:    v_add_i32_e32 v2, vcc, s0, v2
1499; CI-NEXT:    v_mov_b32_e32 v3, s1
1500; CI-NEXT:    s_lshl_b32 s0, s4, 16
1501; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
1502; CI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
1503; CI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
1504; CI-NEXT:    v_or_b32_e32 v1, s0, v1
1505; CI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
1506; CI-NEXT:    s_endpgm
1507  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
1508  %tid.ext = sext i32 %tid to i64
1509  %in.gep = getelementptr inbounds <4 x half>, <4 x half> addrspace(1)* %in, i64 %tid.ext
1510  %out.gep = getelementptr inbounds <4 x half>, <4 x half> addrspace(1)* %out, i64 %tid.ext
1511  %vec = load <4 x half>, <4 x half> addrspace(1)* %in.gep
1512  %val.trunc = trunc i32 %val to i16
1513  %val.cvt = bitcast i16 %val.trunc to half
1514  %vecins = insertelement <4 x half> %vec, half %val.cvt, i32 3
1515  store <4 x half> %vecins, <4 x half> addrspace(1)* %out.gep
1516  ret void
1517}
1518
1519define amdgpu_kernel void @v_insertelement_v4i16_2(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in, i32 %val) #0 {
1520; GFX9-LABEL: v_insertelement_v4i16_2:
1521; GFX9:       ; %bb.0:
1522; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
1523; GFX9-NEXT:    s_load_dword s4, s[4:5], 0x10
1524; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
1525; GFX9-NEXT:    v_mov_b32_e32 v3, 0xffff
1526; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
1527; GFX9-NEXT:    global_load_dwordx2 v[0:1], v2, s[2:3]
1528; GFX9-NEXT:    s_waitcnt vmcnt(0)
1529; GFX9-NEXT:    v_bfi_b32 v1, v3, s4, v1
1530; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
1531; GFX9-NEXT:    s_endpgm
1532;
1533; VI-LABEL: v_insertelement_v4i16_2:
1534; VI:       ; %bb.0:
1535; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
1536; VI-NEXT:    s_load_dword s4, s[4:5], 0x10
1537; VI-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
1538; VI-NEXT:    s_waitcnt lgkmcnt(0)
1539; VI-NEXT:    v_mov_b32_e32 v1, s3
1540; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v2
1541; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1542; VI-NEXT:    flat_load_dwordx2 v[0:1], v[0:1]
1543; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v2
1544; VI-NEXT:    v_mov_b32_e32 v3, s1
1545; VI-NEXT:    s_and_b32 s0, s4, 0xffff
1546; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
1547; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
1548; VI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
1549; VI-NEXT:    v_or_b32_e32 v1, s0, v1
1550; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
1551; VI-NEXT:    s_endpgm
1552;
1553; CI-LABEL: v_insertelement_v4i16_2:
1554; CI:       ; %bb.0:
1555; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
1556; CI-NEXT:    s_load_dword s4, s[4:5], 0x4
1557; CI-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
1558; CI-NEXT:    s_waitcnt lgkmcnt(0)
1559; CI-NEXT:    v_mov_b32_e32 v1, s3
1560; CI-NEXT:    v_add_i32_e32 v0, vcc, s2, v2
1561; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1562; CI-NEXT:    flat_load_dwordx2 v[0:1], v[0:1]
1563; CI-NEXT:    v_add_i32_e32 v2, vcc, s0, v2
1564; CI-NEXT:    v_mov_b32_e32 v3, s1
1565; CI-NEXT:    s_and_b32 s0, s4, 0xffff
1566; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
1567; CI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
1568; CI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
1569; CI-NEXT:    v_or_b32_e32 v1, s0, v1
1570; CI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
1571; CI-NEXT:    s_endpgm
1572  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
1573  %tid.ext = sext i32 %tid to i64
1574  %in.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %in, i64 %tid.ext
1575  %out.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %out, i64 %tid.ext
1576  %vec = load <4 x i16>, <4 x i16> addrspace(1)* %in.gep
1577  %val.trunc = trunc i32 %val to i16
1578  %val.cvt = bitcast i16 %val.trunc to i16
1579  %vecins = insertelement <4 x i16> %vec, i16 %val.cvt, i32 2
1580  store <4 x i16> %vecins, <4 x i16> addrspace(1)* %out.gep
1581  ret void
1582}
1583
1584; FIXME: Better code on CI?
1585define amdgpu_kernel void @v_insertelement_v4i16_dynamic_vgpr(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in, i32 %val) #0 {
1586; GFX9-LABEL: v_insertelement_v4i16_dynamic_vgpr:
1587; GFX9:       ; %bb.0:
1588; GFX9-NEXT:    global_load_dword v2, v[0:1], off
1589; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
1590; GFX9-NEXT:    s_load_dword s4, s[4:5], 0x10
1591; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
1592; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
1593; GFX9-NEXT:    global_load_dwordx2 v[0:1], v4, s[2:3]
1594; GFX9-NEXT:    s_mov_b32 s3, 0
1595; GFX9-NEXT:    s_mov_b32 s2, 0xffff
1596; GFX9-NEXT:    s_waitcnt vmcnt(1)
1597; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 4, v2
1598; GFX9-NEXT:    v_lshlrev_b64 v[2:3], v2, s[2:3]
1599; GFX9-NEXT:    s_pack_ll_b32_b16 s2, s4, s4
1600; GFX9-NEXT:    s_waitcnt vmcnt(0)
1601; GFX9-NEXT:    v_bfi_b32 v1, v3, s2, v1
1602; GFX9-NEXT:    v_bfi_b32 v0, v2, s2, v0
1603; GFX9-NEXT:    global_store_dwordx2 v4, v[0:1], s[0:1]
1604; GFX9-NEXT:    s_endpgm
1605;
1606; VI-LABEL: v_insertelement_v4i16_dynamic_vgpr:
1607; VI:       ; %bb.0:
1608; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
1609; VI-NEXT:    s_load_dword s4, s[4:5], 0x10
1610; VI-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
1611; VI-NEXT:    s_waitcnt lgkmcnt(0)
1612; VI-NEXT:    v_mov_b32_e32 v1, s3
1613; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v2
1614; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1615; VI-NEXT:    flat_load_dword v4, v[0:1]
1616; VI-NEXT:    flat_load_dwordx2 v[0:1], v[0:1]
1617; VI-NEXT:    s_mov_b32 s2, 0xffff
1618; VI-NEXT:    v_mov_b32_e32 v3, s1
1619; VI-NEXT:    s_mov_b32 s3, 0
1620; VI-NEXT:    s_and_b32 s1, s4, s2
1621; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v2
1622; VI-NEXT:    s_lshl_b32 s0, s1, 16
1623; VI-NEXT:    s_or_b32 s0, s1, s0
1624; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
1625; VI-NEXT:    s_waitcnt vmcnt(1) lgkmcnt(1)
1626; VI-NEXT:    v_lshlrev_b32_e32 v4, 4, v4
1627; VI-NEXT:    v_lshlrev_b64 v[4:5], v4, s[2:3]
1628; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
1629; VI-NEXT:    v_bfi_b32 v1, v5, s0, v1
1630; VI-NEXT:    v_bfi_b32 v0, v4, s0, v0
1631; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
1632; VI-NEXT:    s_endpgm
1633;
1634; CI-LABEL: v_insertelement_v4i16_dynamic_vgpr:
1635; CI:       ; %bb.0:
1636; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
1637; CI-NEXT:    s_load_dword s4, s[4:5], 0x4
1638; CI-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
1639; CI-NEXT:    s_waitcnt lgkmcnt(0)
1640; CI-NEXT:    v_mov_b32_e32 v1, s3
1641; CI-NEXT:    v_add_i32_e32 v0, vcc, s2, v2
1642; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1643; CI-NEXT:    flat_load_dword v4, v[0:1]
1644; CI-NEXT:    flat_load_dwordx2 v[0:1], v[0:1]
1645; CI-NEXT:    s_mov_b32 s2, 0xffff
1646; CI-NEXT:    s_mov_b32 s3, 0
1647; CI-NEXT:    v_mov_b32_e32 v3, s1
1648; CI-NEXT:    s_lshl_b32 s1, s4, 16
1649; CI-NEXT:    s_and_b32 s4, s4, s2
1650; CI-NEXT:    v_add_i32_e32 v2, vcc, s0, v2
1651; CI-NEXT:    s_or_b32 s0, s4, s1
1652; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
1653; CI-NEXT:    s_waitcnt vmcnt(1) lgkmcnt(1)
1654; CI-NEXT:    v_lshlrev_b32_e32 v4, 4, v4
1655; CI-NEXT:    v_lshl_b64 v[4:5], s[2:3], v4
1656; CI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
1657; CI-NEXT:    v_bfi_b32 v1, v5, s0, v1
1658; CI-NEXT:    v_bfi_b32 v0, v4, s0, v0
1659; CI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
1660; CI-NEXT:    s_endpgm
1661  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
1662  %tid.ext = sext i32 %tid to i64
1663  %in.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %in, i64 %tid.ext
1664  %out.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %out, i64 %tid.ext
1665  %idx.val = load volatile i32, i32 addrspace(1)* undef
1666  %vec = load <4 x i16>, <4 x i16> addrspace(1)* %in.gep
1667  %val.trunc = trunc i32 %val to i16
1668  %val.cvt = bitcast i16 %val.trunc to i16
1669  %vecins = insertelement <4 x i16> %vec, i16 %val.cvt, i32 %idx.val
1670  store <4 x i16> %vecins, <4 x i16> addrspace(1)* %out.gep
1671  ret void
1672}
1673
1674define amdgpu_kernel void @v_insertelement_v4f16_dynamic_sgpr(<4 x half> addrspace(1)* %out, <4 x half> addrspace(1)* %in, i32 %val, i32 %idxval) #0 {
1675; GFX9-LABEL: v_insertelement_v4f16_dynamic_sgpr:
1676; GFX9:       ; %bb.0:
1677; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
1678; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x10
1679; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
1680; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
1681; GFX9-NEXT:    global_load_dwordx2 v[0:1], v2, s[2:3]
1682; GFX9-NEXT:    s_pack_ll_b32_b16 s4, s4, s4
1683; GFX9-NEXT:    s_mov_b32 s3, 0
1684; GFX9-NEXT:    s_mov_b32 s2, 0xffff
1685; GFX9-NEXT:    s_lshl_b32 s5, s5, 4
1686; GFX9-NEXT:    s_lshl_b64 s[2:3], s[2:3], s5
1687; GFX9-NEXT:    v_mov_b32_e32 v3, s4
1688; GFX9-NEXT:    v_mov_b32_e32 v4, s4
1689; GFX9-NEXT:    s_waitcnt vmcnt(0)
1690; GFX9-NEXT:    v_bfi_b32 v1, s3, v3, v1
1691; GFX9-NEXT:    v_bfi_b32 v0, s2, v4, v0
1692; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
1693; GFX9-NEXT:    s_endpgm
1694;
1695; VI-LABEL: v_insertelement_v4f16_dynamic_sgpr:
1696; VI:       ; %bb.0:
1697; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
1698; VI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x10
1699; VI-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
1700; VI-NEXT:    s_waitcnt lgkmcnt(0)
1701; VI-NEXT:    v_mov_b32_e32 v1, s3
1702; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v2
1703; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1704; VI-NEXT:    flat_load_dwordx2 v[0:1], v[0:1]
1705; VI-NEXT:    s_mov_b32 s2, 0xffff
1706; VI-NEXT:    v_mov_b32_e32 v3, s1
1707; VI-NEXT:    s_mov_b32 s3, 0
1708; VI-NEXT:    s_lshl_b32 s1, s5, 4
1709; VI-NEXT:    s_and_b32 s4, s4, s2
1710; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v2
1711; VI-NEXT:    s_lshl_b64 s[0:1], s[2:3], s1
1712; VI-NEXT:    s_lshl_b32 s2, s4, 16
1713; VI-NEXT:    s_or_b32 s2, s4, s2
1714; VI-NEXT:    v_mov_b32_e32 v4, s2
1715; VI-NEXT:    v_mov_b32_e32 v5, s2
1716; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
1717; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
1718; VI-NEXT:    v_bfi_b32 v1, s1, v4, v1
1719; VI-NEXT:    v_bfi_b32 v0, s0, v5, v0
1720; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
1721; VI-NEXT:    s_endpgm
1722;
1723; CI-LABEL: v_insertelement_v4f16_dynamic_sgpr:
1724; CI:       ; %bb.0:
1725; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
1726; CI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x4
1727; CI-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
1728; CI-NEXT:    s_waitcnt lgkmcnt(0)
1729; CI-NEXT:    v_mov_b32_e32 v1, s3
1730; CI-NEXT:    v_add_i32_e32 v0, vcc, s2, v2
1731; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1732; CI-NEXT:    flat_load_dwordx2 v[0:1], v[0:1]
1733; CI-NEXT:    s_mov_b32 s2, 0xffff
1734; CI-NEXT:    v_mov_b32_e32 v3, s1
1735; CI-NEXT:    s_and_b32 s6, s4, s2
1736; CI-NEXT:    s_mov_b32 s3, 0
1737; CI-NEXT:    s_lshl_b32 s1, s5, 4
1738; CI-NEXT:    s_lshl_b32 s4, s4, 16
1739; CI-NEXT:    v_add_i32_e32 v2, vcc, s0, v2
1740; CI-NEXT:    s_lshl_b64 s[0:1], s[2:3], s1
1741; CI-NEXT:    s_or_b32 s2, s6, s4
1742; CI-NEXT:    v_mov_b32_e32 v4, s2
1743; CI-NEXT:    v_mov_b32_e32 v5, s2
1744; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
1745; CI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
1746; CI-NEXT:    v_bfi_b32 v1, s1, v4, v1
1747; CI-NEXT:    v_bfi_b32 v0, s0, v5, v0
1748; CI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
1749; CI-NEXT:    s_endpgm
1750  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
1751  %tid.ext = sext i32 %tid to i64
1752  %in.gep = getelementptr inbounds <4 x half>, <4 x half> addrspace(1)* %in, i64 %tid.ext
1753  %out.gep = getelementptr inbounds <4 x half>, <4 x half> addrspace(1)* %out, i64 %tid.ext
1754  %vec = load <4 x half>, <4 x half> addrspace(1)* %in.gep
1755  %val.trunc = trunc i32 %val to i16
1756  %val.cvt = bitcast i16 %val.trunc to half
1757  %vecins = insertelement <4 x half> %vec, half %val.cvt, i32 %idxval
1758  store <4 x half> %vecins, <4 x half> addrspace(1)* %out.gep
1759  ret void
1760}
1761
1762declare i32 @llvm.amdgcn.workitem.id.x() #1
1763
1764attributes #0 = { nounwind }
1765attributes #1 = { nounwind readnone }
1766