1; RUN: llc -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI,GCN-NO-TONGA %s 2; RUN: llc -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,GCN-TONGA %s 3 4; FIXME: Broken on evergreen 5; FIXME: For some reason the 8 and 16 vectors are being stored as 6; individual elements instead of 128-bit stores. 7 8 9; FIXME: Why is the constant moved into the intermediate register and 10; not just directly into the vector component? 11 12; GCN-LABEL: {{^}}insertelement_v4f32_0: 13; GCN: s_load_dwordx4 14; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 15; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 16; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 17; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 18; GCN-DAG: s_mov_b32 [[CONSTREG:s[0-9]+]], 0x40a00000 19; GCN-DAG: v_mov_b32_e32 v[[LOW_REG:[0-9]+]], [[CONSTREG]] 20; GCN: buffer_store_dwordx4 v{{\[}}[[LOW_REG]]: 21define amdgpu_kernel void @insertelement_v4f32_0(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind { 22 %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 0 23 store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16 24 ret void 25} 26 27; GCN-LABEL: {{^}}insertelement_v4f32_1: 28define amdgpu_kernel void @insertelement_v4f32_1(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind { 29 %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 1 30 store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16 31 ret void 32} 33 34; GCN-LABEL: {{^}}insertelement_v4f32_2: 35define amdgpu_kernel void @insertelement_v4f32_2(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind { 36 %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 2 37 store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16 38 ret void 39} 40 41; GCN-LABEL: {{^}}insertelement_v4f32_3: 42define amdgpu_kernel void @insertelement_v4f32_3(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind { 43 %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 3 44 store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16 45 ret void 46} 47 48; GCN-LABEL: {{^}}insertelement_v4i32_0: 49define amdgpu_kernel void @insertelement_v4i32_0(<4 x i32> addrspace(1)* %out, <4 x i32> %a) nounwind { 50 %vecins = insertelement <4 x i32> %a, i32 999, i32 0 51 store <4 x i32> %vecins, <4 x i32> addrspace(1)* %out, align 16 52 ret void 53} 54 55; GCN-LABEL: {{^}}insertelement_v3f32_1: 56define amdgpu_kernel void @insertelement_v3f32_1(<3 x float> addrspace(1)* %out, <3 x float> %a) nounwind { 57 %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 1 58 store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16 59 ret void 60} 61 62; GCN-LABEL: {{^}}insertelement_v3f32_2: 63define amdgpu_kernel void @insertelement_v3f32_2(<3 x float> addrspace(1)* %out, <3 x float> %a) nounwind { 64 %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 2 65 store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16 66 ret void 67} 68 69; GCN-LABEL: {{^}}insertelement_v3f32_3: 70define amdgpu_kernel void @insertelement_v3f32_3(<3 x float> addrspace(1)* %out, <3 x float> %a) nounwind { 71 %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 3 72 store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16 73 ret void 74} 75 76; GCN-LABEL: {{^}}insertelement_to_sgpr: 77; GCN-NOT: v_readfirstlane 78define amdgpu_ps <4 x float> @insertelement_to_sgpr(<4 x i32> inreg %samp) nounwind { 79 %tmp1 = insertelement <4 x i32> %samp, i32 0, i32 0 80 %tmp2 = call <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f32(i32 1, float undef, float undef, <8 x i32> undef, <4 x i32> %tmp1, i1 0, i32 0, i32 0) 81 ret <4 x float> %tmp2 82} 83 84; GCN-LABEL: {{^}}dynamic_insertelement_v2f32: 85; GCN: v_mov_b32_e32 [[CONST:v[0-9]+]], 0x40a00000 86; GCN: v_movreld_b32_e32 v[[LOW_RESULT_REG:[0-9]+]], [[CONST]] 87; GCN: buffer_store_dwordx2 {{v\[}}[[LOW_RESULT_REG]]: 88define amdgpu_kernel void @dynamic_insertelement_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, i32 %b) nounwind { 89 %vecins = insertelement <2 x float> %a, float 5.000000e+00, i32 %b 90 store <2 x float> %vecins, <2 x float> addrspace(1)* %out, align 8 91 ret void 92} 93 94; GCN-LABEL: {{^}}dynamic_insertelement_v3f32: 95; GCN: v_mov_b32_e32 [[CONST:v[0-9]+]], 0x40a00000 96; GCN: v_movreld_b32_e32 v[[LOW_RESULT_REG:[0-9]+]], [[CONST]] 97; GCN-DAG: buffer_store_dwordx2 {{v\[}}[[LOW_RESULT_REG]]: 98; GCN-DAG: buffer_store_dword v 99define amdgpu_kernel void @dynamic_insertelement_v3f32(<3 x float> addrspace(1)* %out, <3 x float> %a, i32 %b) nounwind { 100 %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 %b 101 store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16 102 ret void 103} 104 105; GCN-LABEL: {{^}}dynamic_insertelement_v4f32: 106; GCN: v_mov_b32_e32 [[CONST:v[0-9]+]], 0x40a00000 107; GCN: v_movreld_b32_e32 v[[LOW_RESULT_REG:[0-9]+]], [[CONST]] 108; GCN: buffer_store_dwordx4 {{v\[}}[[LOW_RESULT_REG]]: 109define amdgpu_kernel void @dynamic_insertelement_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, i32 %b) nounwind { 110 %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 %b 111 store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16 112 ret void 113} 114 115; GCN-LABEL: {{^}}dynamic_insertelement_v8f32: 116; GCN: v_movreld_b32_e32 v{{[0-9]+}}, v{{[0-9]+}} 117; GCN: buffer_store_dwordx4 118; GCN: buffer_store_dwordx4 119define amdgpu_kernel void @dynamic_insertelement_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, i32 %b) nounwind { 120 %vecins = insertelement <8 x float> %a, float 5.000000e+00, i32 %b 121 store <8 x float> %vecins, <8 x float> addrspace(1)* %out, align 32 122 ret void 123} 124 125; GCN-LABEL: {{^}}dynamic_insertelement_v16f32: 126; GCN: v_movreld_b32_e32 v{{[0-9]+}}, v{{[0-9]+}} 127; GCN: buffer_store_dwordx4 128; GCN: buffer_store_dwordx4 129; GCN: buffer_store_dwordx4 130; GCN: buffer_store_dwordx4 131define amdgpu_kernel void @dynamic_insertelement_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %a, i32 %b) nounwind { 132 %vecins = insertelement <16 x float> %a, float 5.000000e+00, i32 %b 133 store <16 x float> %vecins, <16 x float> addrspace(1)* %out, align 64 134 ret void 135} 136 137; GCN-LABEL: {{^}}dynamic_insertelement_v2i32: 138; GCN: v_movreld_b32 139; GCN: buffer_store_dwordx2 140define amdgpu_kernel void @dynamic_insertelement_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, i32 %b) nounwind { 141 %vecins = insertelement <2 x i32> %a, i32 5, i32 %b 142 store <2 x i32> %vecins, <2 x i32> addrspace(1)* %out, align 8 143 ret void 144} 145 146; GCN-LABEL: {{^}}dynamic_insertelement_v3i32: 147; GCN: v_movreld_b32_e32 v[[LOW_RESULT_REG:[0-9]+]], 5 148; GCN-DAG: buffer_store_dwordx2 {{v\[}}[[LOW_RESULT_REG]]: 149; GCN-DAG: buffer_store_dword v 150define amdgpu_kernel void @dynamic_insertelement_v3i32(<3 x i32> addrspace(1)* %out, <3 x i32> %a, i32 %b) nounwind { 151 %vecins = insertelement <3 x i32> %a, i32 5, i32 %b 152 store <3 x i32> %vecins, <3 x i32> addrspace(1)* %out, align 16 153 ret void 154} 155 156; GCN-LABEL: {{^}}dynamic_insertelement_v4i32: 157; GCN: s_load_dword [[SVAL:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, {{0x12|0x48}} 158; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[SVAL]] 159; GCN: v_movreld_b32_e32 v{{[0-9]+}}, [[VVAL]] 160; GCN: buffer_store_dwordx4 161define amdgpu_kernel void @dynamic_insertelement_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, i32 %b, i32 %val) nounwind { 162 %vecins = insertelement <4 x i32> %a, i32 %val, i32 %b 163 store <4 x i32> %vecins, <4 x i32> addrspace(1)* %out, align 16 164 ret void 165} 166 167; GCN-LABEL: {{^}}dynamic_insertelement_v8i32: 168; GCN: v_movreld_b32 169; GCN: buffer_store_dwordx4 170; GCN: buffer_store_dwordx4 171define amdgpu_kernel void @dynamic_insertelement_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> %a, i32 %b) nounwind { 172 %vecins = insertelement <8 x i32> %a, i32 5, i32 %b 173 store <8 x i32> %vecins, <8 x i32> addrspace(1)* %out, align 32 174 ret void 175} 176 177; GCN-LABEL: {{^}}dynamic_insertelement_v16i32: 178; GCN: v_movreld_b32 179; GCN: buffer_store_dwordx4 180; GCN: buffer_store_dwordx4 181; GCN: buffer_store_dwordx4 182; GCN: buffer_store_dwordx4 183define amdgpu_kernel void @dynamic_insertelement_v16i32(<16 x i32> addrspace(1)* %out, <16 x i32> %a, i32 %b) nounwind { 184 %vecins = insertelement <16 x i32> %a, i32 5, i32 %b 185 store <16 x i32> %vecins, <16 x i32> addrspace(1)* %out, align 64 186 ret void 187} 188 189; GCN-LABEL: {{^}}dynamic_insertelement_v2i16: 190define amdgpu_kernel void @dynamic_insertelement_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %a, i32 %b) nounwind { 191 %vecins = insertelement <2 x i16> %a, i16 5, i32 %b 192 store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out, align 8 193 ret void 194} 195 196; GCN-LABEL: {{^}}dynamic_insertelement_v3i16: 197define amdgpu_kernel void @dynamic_insertelement_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %a, i32 %b) nounwind { 198 %vecins = insertelement <3 x i16> %a, i16 5, i32 %b 199 store <3 x i16> %vecins, <3 x i16> addrspace(1)* %out, align 8 200 ret void 201} 202 203; GCN-LABEL: {{^}}dynamic_insertelement_v2i8: 204; VI: s_load_dword [[LOAD:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c 205; VI-NEXT: s_load_dword [[IDX:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30 206; VI-NOT: _load 207; VI: s_lshr_b32 [[ELT1:s[0-9]+]], [[LOAD]], 8 208; VI: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 3 209; VI: v_lshlrev_b16_e64 [[ELT1_SHIFT:v[0-9]+]], 8, [[ELT1]] 210; VI: s_and_b32 [[ELT0:s[0-9]+]], [[LOAD]], 0xff{{$}} 211; VI: v_lshlrev_b16_e64 [[MASK:v[0-9]+]], [[SCALED_IDX]], -1 212 213; VI: v_xor_b32_e32 [[NOT:v[0-9]+]], -1, [[MASK]] 214; VI: v_or_b32_e32 [[BUILD_VECTOR:v[0-9]+]], [[ELT0]], [[ELT1_SHIFT]] 215 216; VI: v_and_b32_e32 [[AND1:v[0-9]+]], [[NOT]], [[BUILD_VECTOR]] 217; VI-DAG: v_and_b32_e32 [[INSERT:v[0-9]+]], 5, [[MASK]] 218; VI: v_or_b32_e32 [[OR:v[0-9]+]], [[INSERT]], [[BUILD_VECTOR]] 219; VI: buffer_store_short [[OR]] 220define amdgpu_kernel void @dynamic_insertelement_v2i8(<2 x i8> addrspace(1)* %out, <2 x i8> %a, i32 %b) nounwind { 221 %vecins = insertelement <2 x i8> %a, i8 5, i32 %b 222 store <2 x i8> %vecins, <2 x i8> addrspace(1)* %out, align 8 223 ret void 224} 225 226; FIXME: post legalize i16 and i32 shifts aren't merged because of 227; isTypeDesirableForOp in SimplifyDemandedBits 228 229; GCN-LABEL: {{^}}dynamic_insertelement_v3i8: 230; VI: s_load_dword [[LOAD:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c 231; VI-NEXT: s_load_dword [[IDX:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30 232; VI-NOT: _load 233 234; VI: s_lshr_b32 [[VEC_HI:s[0-9]+]], [[LOAD]], 8 235; VI: v_lshlrev_b16_e64 [[ELT2:v[0-9]+]], 8, [[VEC_HI]] 236; VI: s_and_b32 [[ELT0:s[0-9]+]], [[LOAD]], 0xff{{$}} 237; VI: v_or_b32_e32 [[BUILD_VEC:v[0-9]+]], [[VEC_HI]], [[ELT2]] 238; VI: s_and_b32 [[ELT2:s[0-9]+]], [[LOAD]], 0xff0000{{$}} 239 240; VI: s_mov_b32 [[MASK16:s[0-9]+]], 0xffff{{$}} 241; VI: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 3 242; VI: s_lshl_b32 [[SHIFTED_MASK:s[0-9]+]], [[MASK16]], [[SCALED_IDX]] 243 244; VI: v_mov_b32_e32 [[V_ELT2:v[0-9]+]], [[ELT2]] 245; VI: v_or_b32_sdwa [[SDWA:v[0-9]+]], [[BUILD_VEC]], [[V_ELT2]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 246; VI: s_not_b32 [[NOT_SHIFT_MASK:s[0-9]+]], [[SHIFTED_MASK]] 247; VI: v_and_b32_e32 [[AND_NOT_MASK:v[0-9]+]], [[NOT_SHIFT_MASK]], [[SDWA]] 248; VI: v_lshrrev_b32_e32 [[HI2:v[0-9]+]], 16, [[AND_NOT_MASK]] 249; VI: v_bfi_b32 [[BFI:v[0-9]+]], [[SCALED_IDX]], 5, [[SDWA]] 250; VI: buffer_store_short [[BFI]] 251; VI: buffer_store_byte [[HI2]] 252define amdgpu_kernel void @dynamic_insertelement_v3i8(<3 x i8> addrspace(1)* %out, <3 x i8> %a, i32 %b) nounwind { 253 %vecins = insertelement <3 x i8> %a, i8 5, i32 %b 254 store <3 x i8> %vecins, <3 x i8> addrspace(1)* %out, align 4 255 ret void 256} 257 258; GCN-LABEL: {{^}}dynamic_insertelement_v4i8: 259; VI: s_load_dword [[VEC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c 260; VI-NEXT: s_load_dword [[IDX:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30 261; VI-NOT: _load 262 263; VI: s_lshr_b32 [[ELT1:s[0-9]+]], [[VEC]], 8 264; VI: v_lshlrev_b16_e64 [[ELT2:v[0-9]+]], 8, [[ELT1]] 265; VI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0xff{{$}} 266 267 268; VI: s_lshr_b32 [[ELT3:s[0-9]+]], [[VEC]], 24 269; VI: s_lshr_b32 [[ELT2:s[0-9]+]], [[VEC]], 16 270; VI: v_lshlrev_b16_e64 v{{[0-9]+}}, 8, [[ELT3]] 271; VI: v_or_b32_e32 272; VI: v_or_b32_sdwa 273; VI-DAG: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 3 274; VI: v_or_b32_sdwa 275; VI: s_lshl_b32 276; VI: v_bfi_b32 277define amdgpu_kernel void @dynamic_insertelement_v4i8(<4 x i8> addrspace(1)* %out, <4 x i8> %a, i32 %b) nounwind { 278 %vecins = insertelement <4 x i8> %a, i8 5, i32 %b 279 store <4 x i8> %vecins, <4 x i8> addrspace(1)* %out, align 4 280 ret void 281} 282 283; GCN-LABEL: {{^}}s_dynamic_insertelement_v8i8: 284; VI-NOT: {{buffer|flat|global}} 285; VI: s_load_dword [[IDX:s[0-9]]] 286; VI-NOT: {{buffer|flat|global}} 287; VI: s_load_dwordx2 [[VEC:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0x0 288; VI-NOT: {{buffer|flat|global}} 289 290; VI-DAG: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 3 291; VI-DAG: s_mov_b32 s[[MASK_HI:[0-9]+]], 0 292; VI-DAG: s_mov_b32 s[[MASK_LO:[0-9]+]], 0xffff 293; VI: s_lshl_b64 s{{\[}}[[MASK_SHIFT_LO:[0-9]+]]:[[MASK_SHIFT_HI:[0-9]+]]{{\]}}, s{{\[}}[[MASK_LO]]:[[MASK_HI]]{{\]}}, [[SCALED_IDX]] 294; VI: s_not_b64 [[NOT_MASK:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[MASK_SHIFT_LO]]:[[MASK_SHIFT_HI]]{{\]}} 295; VI: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], [[NOT_MASK]], [[VEC]] 296; VI: s_and_b32 s[[INS:[0-9]+]], s[[MASK_SHIFT_LO]], 5 297; VI: s_or_b64 s{{\[}}[[RESULT0:[0-9]+]]:[[RESULT1:[0-9]+]]{{\]}}, s{{\[}}[[INS]]:[[MASK_HI]]{{\]}}, [[AND]] 298; VI: v_mov_b32_e32 v[[V_RESULT0:[0-9]+]], s[[RESULT0]] 299; VI: v_mov_b32_e32 v[[V_RESULT1:[0-9]+]], s[[RESULT1]] 300; VI: buffer_store_dwordx2 v{{\[}}[[V_RESULT0]]:[[V_RESULT1]]{{\]}} 301define amdgpu_kernel void @s_dynamic_insertelement_v8i8(<8 x i8> addrspace(1)* %out, <8 x i8> addrspace(4)* %a.ptr, i32 %b) nounwind { 302 %a = load <8 x i8>, <8 x i8> addrspace(4)* %a.ptr, align 4 303 %vecins = insertelement <8 x i8> %a, i8 5, i32 %b 304 store <8 x i8> %vecins, <8 x i8> addrspace(1)* %out, align 8 305 ret void 306} 307 308; GCN-LABEL: {{^}}dynamic_insertelement_v16i8: 309; GCN: s_load_dwordx2 310; GCN: s_load_dword s 311; GCN: s_load_dword s 312; GCN: s_load_dword s 313; GCN: s_load_dword s 314; GCN: s_load_dword s 315; GCN-NOT: _load_ 316 317 318; GCN: buffer_store_byte 319; GCN: buffer_store_byte 320; GCN: buffer_store_byte 321; GCN: buffer_store_byte 322; GCN: buffer_store_byte 323; GCN: buffer_store_byte 324; GCN: buffer_store_byte 325; GCN: buffer_store_byte 326; GCN: buffer_store_byte 327; GCN: buffer_store_byte 328; GCN: buffer_store_byte 329; GCN: buffer_store_byte 330; GCN: buffer_store_byte 331; GCN: buffer_store_byte 332; GCN: buffer_store_byte 333; GCN: buffer_store_byte 334 335; GCN: buffer_store_byte 336; GCN: buffer_store_dwordx4 337define amdgpu_kernel void @dynamic_insertelement_v16i8(<16 x i8> addrspace(1)* %out, <16 x i8> %a, i32 %b) nounwind { 338 %vecins = insertelement <16 x i8> %a, i8 5, i32 %b 339 store <16 x i8> %vecins, <16 x i8> addrspace(1)* %out, align 16 340 ret void 341} 342 343; This test requires handling INSERT_SUBREG in SIFixSGPRCopies. Check that 344; the compiler doesn't crash. 345; GCN-LABEL: {{^}}insert_split_bb: 346define amdgpu_kernel void @insert_split_bb(<2 x i32> addrspace(1)* %out, i32 addrspace(1)* %in, i32 %a, i32 %b) { 347entry: 348 %0 = insertelement <2 x i32> undef, i32 %a, i32 0 349 %1 = icmp eq i32 %a, 0 350 br i1 %1, label %if, label %else 351 352if: 353 %2 = load i32, i32 addrspace(1)* %in 354 %3 = insertelement <2 x i32> %0, i32 %2, i32 1 355 br label %endif 356 357else: 358 %4 = getelementptr i32, i32 addrspace(1)* %in, i32 1 359 %5 = load i32, i32 addrspace(1)* %4 360 %6 = insertelement <2 x i32> %0, i32 %5, i32 1 361 br label %endif 362 363endif: 364 %7 = phi <2 x i32> [%3, %if], [%6, %else] 365 store <2 x i32> %7, <2 x i32> addrspace(1)* %out 366 ret void 367} 368 369; GCN-LABEL: {{^}}dynamic_insertelement_v2f64: 370; GCN-DAG: s_load_dwordx4 s{{\[}}[[A_ELT0:[0-9]+]]:[[A_ELT3:[0-9]+]]{{\]}} 371; GCN-DAG: s_load_dword [[IDX:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, {{0x11|0x44}}{{$}} 372 373; GCN-DAG: s_lshl_b32 [[SCALEDIDX:s[0-9]+]], [[IDX]], 1{{$}} 374 375; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 376; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 377; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 378; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 379; GCN-DAG: v_mov_b32_e32 [[ELT1:v[0-9]+]], 0x40200000 380 381; GCN-DAG: s_mov_b32 m0, [[SCALEDIDX]] 382; GCN: v_movreld_b32_e32 v{{[0-9]+}}, 0 383 384; Increment to next element folded into base register, but FileCheck 385; can't do math expressions 386 387; FIXME: Should be able to manipulate m0 directly instead of s_lshl_b32 + copy to m0 388 389; GCN: v_movreld_b32_e32 v{{[0-9]+}}, [[ELT1]] 390 391; GCN: buffer_store_dwordx4 392; GCN: s_endpgm 393define amdgpu_kernel void @dynamic_insertelement_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %a, i32 %b) nounwind { 394 %vecins = insertelement <2 x double> %a, double 8.0, i32 %b 395 store <2 x double> %vecins, <2 x double> addrspace(1)* %out, align 16 396 ret void 397} 398 399; GCN-LABEL: {{^}}dynamic_insertelement_v2i64: 400 401; GCN-DAG: v_movreld_b32_e32 v{{[0-9]+}}, 5 402; GCN-DAG: v_movreld_b32_e32 v{{[0-9]+}}, 0 403 404; GCN: buffer_store_dwordx4 405; GCN: s_endpgm 406define amdgpu_kernel void @dynamic_insertelement_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %a, i32 %b) nounwind { 407 %vecins = insertelement <2 x i64> %a, i64 5, i32 %b 408 store <2 x i64> %vecins, <2 x i64> addrspace(1)* %out, align 8 409 ret void 410} 411 412; GCN-LABEL: {{^}}dynamic_insertelement_v3i64: 413define amdgpu_kernel void @dynamic_insertelement_v3i64(<3 x i64> addrspace(1)* %out, <3 x i64> %a, i32 %b) nounwind { 414 %vecins = insertelement <3 x i64> %a, i64 5, i32 %b 415 store <3 x i64> %vecins, <3 x i64> addrspace(1)* %out, align 32 416 ret void 417} 418 419; FIXME: Should be able to do without stack access. The used stack 420; space is also 2x what should be required. 421 422; GCN-LABEL: {{^}}dynamic_insertelement_v4f64: 423; GCN: SCRATCH_RSRC_DWORD 424 425; Stack store 426 427; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:32{{$}} 428; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:48{{$}} 429 430; Write element 431; GCN: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen{{$}} 432 433; Stack reload 434; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:32{{$}} 435; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:48{{$}} 436 437; Store result 438; GCN: buffer_store_dwordx4 439; GCN: buffer_store_dwordx4 440; GCN: s_endpgm 441; GCN: ScratchSize: 64 442 443define amdgpu_kernel void @dynamic_insertelement_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %a, i32 %b) nounwind { 444 %vecins = insertelement <4 x double> %a, double 8.0, i32 %b 445 store <4 x double> %vecins, <4 x double> addrspace(1)* %out, align 16 446 ret void 447} 448 449; GCN-LABEL: {{^}}dynamic_insertelement_v8f64: 450; GCN-DAG: SCRATCH_RSRC_DWORD 451 452; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:64{{$}} 453; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:80{{$}} 454; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:96{{$}} 455; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:112{{$}} 456 457; GCN: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen{{$}} 458 459; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:64{{$}} 460; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:80{{$}} 461; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:96{{$}} 462; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:112{{$}} 463 464; GCN: buffer_store_dwordx4 465; GCN: buffer_store_dwordx4 466; GCN: buffer_store_dwordx4 467; GCN: buffer_store_dwordx4 468; GCN: s_endpgm 469; GCN: ScratchSize: 128 470define amdgpu_kernel void @dynamic_insertelement_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %a, i32 %b) #0 { 471 %vecins = insertelement <8 x double> %a, double 8.0, i32 %b 472 store <8 x double> %vecins, <8 x double> addrspace(1)* %out, align 16 473 ret void 474} 475 476declare <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 477 478attributes #0 = { nounwind } 479attributes #1 = { nounwind readnone } 480