1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -mattr=-flat-for-global,+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI,GCN-NO-TONGA %s
3; RUN: llc -verify-machineinstrs -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -mattr=-flat-for-global -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,GCN-TONGA %s
4
5; FIXME: Broken on evergreen
6; FIXME: For some reason the 8 and 16 vectors are being stored as
7; individual elements instead of 128-bit stores.
8
9
10; FIXME: Why is the constant moved into the intermediate register and
11; not just directly into the vector component?
12define amdgpu_kernel void @insertelement_v4f32_0(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind {
13; SI-LABEL: insertelement_v4f32_0:
14; SI:       ; %bb.0:
15; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
16; SI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x4
17; SI-NEXT:    s_waitcnt lgkmcnt(0)
18; SI-NEXT:    s_mov_b32 s4, 0x40a00000
19; SI-NEXT:    s_mov_b32 s3, 0x100f000
20; SI-NEXT:    s_mov_b32 s2, -1
21; SI-NEXT:    v_mov_b32_e32 v0, s4
22; SI-NEXT:    v_mov_b32_e32 v1, s5
23; SI-NEXT:    v_mov_b32_e32 v2, s6
24; SI-NEXT:    v_mov_b32_e32 v3, s7
25; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
26; SI-NEXT:    s_endpgm
27;
28; VI-LABEL: insertelement_v4f32_0:
29; VI:       ; %bb.0:
30; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
31; VI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x10
32; VI-NEXT:    s_waitcnt lgkmcnt(0)
33; VI-NEXT:    s_mov_b32 s4, 0x40a00000
34; VI-NEXT:    s_mov_b32 s3, 0x1100f000
35; VI-NEXT:    s_mov_b32 s2, -1
36; VI-NEXT:    v_mov_b32_e32 v0, s4
37; VI-NEXT:    v_mov_b32_e32 v1, s5
38; VI-NEXT:    v_mov_b32_e32 v2, s6
39; VI-NEXT:    v_mov_b32_e32 v3, s7
40; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
41; VI-NEXT:    s_endpgm
42  %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 0
43  store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16
44  ret void
45}
46
47define amdgpu_kernel void @insertelement_v4f32_1(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind {
48; SI-LABEL: insertelement_v4f32_1:
49; SI:       ; %bb.0:
50; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
51; SI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x4
52; SI-NEXT:    s_waitcnt lgkmcnt(0)
53; SI-NEXT:    s_mov_b32 s5, 0x40a00000
54; SI-NEXT:    s_mov_b32 s3, 0x100f000
55; SI-NEXT:    s_mov_b32 s2, -1
56; SI-NEXT:    v_mov_b32_e32 v0, s4
57; SI-NEXT:    v_mov_b32_e32 v1, s5
58; SI-NEXT:    v_mov_b32_e32 v2, s6
59; SI-NEXT:    v_mov_b32_e32 v3, s7
60; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
61; SI-NEXT:    s_endpgm
62;
63; VI-LABEL: insertelement_v4f32_1:
64; VI:       ; %bb.0:
65; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
66; VI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x10
67; VI-NEXT:    s_waitcnt lgkmcnt(0)
68; VI-NEXT:    s_mov_b32 s5, 0x40a00000
69; VI-NEXT:    s_mov_b32 s3, 0x1100f000
70; VI-NEXT:    s_mov_b32 s2, -1
71; VI-NEXT:    v_mov_b32_e32 v0, s4
72; VI-NEXT:    v_mov_b32_e32 v1, s5
73; VI-NEXT:    v_mov_b32_e32 v2, s6
74; VI-NEXT:    v_mov_b32_e32 v3, s7
75; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
76; VI-NEXT:    s_endpgm
77  %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 1
78  store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16
79  ret void
80}
81
82define amdgpu_kernel void @insertelement_v4f32_2(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind {
83; SI-LABEL: insertelement_v4f32_2:
84; SI:       ; %bb.0:
85; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
86; SI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x4
87; SI-NEXT:    s_waitcnt lgkmcnt(0)
88; SI-NEXT:    s_mov_b32 s6, 0x40a00000
89; SI-NEXT:    s_mov_b32 s3, 0x100f000
90; SI-NEXT:    s_mov_b32 s2, -1
91; SI-NEXT:    v_mov_b32_e32 v0, s4
92; SI-NEXT:    v_mov_b32_e32 v1, s5
93; SI-NEXT:    v_mov_b32_e32 v2, s6
94; SI-NEXT:    v_mov_b32_e32 v3, s7
95; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
96; SI-NEXT:    s_endpgm
97;
98; VI-LABEL: insertelement_v4f32_2:
99; VI:       ; %bb.0:
100; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
101; VI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x10
102; VI-NEXT:    s_waitcnt lgkmcnt(0)
103; VI-NEXT:    s_mov_b32 s6, 0x40a00000
104; VI-NEXT:    s_mov_b32 s3, 0x1100f000
105; VI-NEXT:    s_mov_b32 s2, -1
106; VI-NEXT:    v_mov_b32_e32 v0, s4
107; VI-NEXT:    v_mov_b32_e32 v1, s5
108; VI-NEXT:    v_mov_b32_e32 v2, s6
109; VI-NEXT:    v_mov_b32_e32 v3, s7
110; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
111; VI-NEXT:    s_endpgm
112  %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 2
113  store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16
114  ret void
115}
116
117define amdgpu_kernel void @insertelement_v4f32_3(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind {
118; SI-LABEL: insertelement_v4f32_3:
119; SI:       ; %bb.0:
120; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
121; SI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x4
122; SI-NEXT:    s_waitcnt lgkmcnt(0)
123; SI-NEXT:    s_mov_b32 s7, 0x40a00000
124; SI-NEXT:    s_mov_b32 s3, 0x100f000
125; SI-NEXT:    s_mov_b32 s2, -1
126; SI-NEXT:    v_mov_b32_e32 v0, s4
127; SI-NEXT:    v_mov_b32_e32 v1, s5
128; SI-NEXT:    v_mov_b32_e32 v2, s6
129; SI-NEXT:    v_mov_b32_e32 v3, s7
130; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
131; SI-NEXT:    s_endpgm
132;
133; VI-LABEL: insertelement_v4f32_3:
134; VI:       ; %bb.0:
135; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
136; VI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x10
137; VI-NEXT:    s_waitcnt lgkmcnt(0)
138; VI-NEXT:    s_mov_b32 s7, 0x40a00000
139; VI-NEXT:    s_mov_b32 s3, 0x1100f000
140; VI-NEXT:    s_mov_b32 s2, -1
141; VI-NEXT:    v_mov_b32_e32 v0, s4
142; VI-NEXT:    v_mov_b32_e32 v1, s5
143; VI-NEXT:    v_mov_b32_e32 v2, s6
144; VI-NEXT:    v_mov_b32_e32 v3, s7
145; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
146; VI-NEXT:    s_endpgm
147  %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 3
148  store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16
149  ret void
150}
151
152define amdgpu_kernel void @insertelement_v4i32_0(<4 x i32> addrspace(1)* %out, <4 x i32> %a) nounwind {
153; SI-LABEL: insertelement_v4i32_0:
154; SI:       ; %bb.0:
155; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
156; SI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x4
157; SI-NEXT:    s_waitcnt lgkmcnt(0)
158; SI-NEXT:    s_movk_i32 s4, 0x3e7
159; SI-NEXT:    s_mov_b32 s3, 0x100f000
160; SI-NEXT:    s_mov_b32 s2, -1
161; SI-NEXT:    v_mov_b32_e32 v0, s4
162; SI-NEXT:    v_mov_b32_e32 v1, s5
163; SI-NEXT:    v_mov_b32_e32 v2, s6
164; SI-NEXT:    v_mov_b32_e32 v3, s7
165; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
166; SI-NEXT:    s_endpgm
167;
168; VI-LABEL: insertelement_v4i32_0:
169; VI:       ; %bb.0:
170; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
171; VI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x10
172; VI-NEXT:    s_waitcnt lgkmcnt(0)
173; VI-NEXT:    s_movk_i32 s4, 0x3e7
174; VI-NEXT:    s_mov_b32 s3, 0x1100f000
175; VI-NEXT:    s_mov_b32 s2, -1
176; VI-NEXT:    v_mov_b32_e32 v0, s4
177; VI-NEXT:    v_mov_b32_e32 v1, s5
178; VI-NEXT:    v_mov_b32_e32 v2, s6
179; VI-NEXT:    v_mov_b32_e32 v3, s7
180; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
181; VI-NEXT:    s_endpgm
182  %vecins = insertelement <4 x i32> %a, i32 999, i32 0
183  store <4 x i32> %vecins, <4 x i32> addrspace(1)* %out, align 16
184  ret void
185}
186
187define amdgpu_kernel void @insertelement_v3f32_1(<3 x float> addrspace(1)* %out, <3 x float> %a) nounwind {
188; SI-LABEL: insertelement_v3f32_1:
189; SI:       ; %bb.0:
190; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
191; SI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x4
192; SI-NEXT:    s_mov_b32 s3, 0x100f000
193; SI-NEXT:    s_mov_b32 s2, -1
194; SI-NEXT:    v_mov_b32_e32 v1, 0x40a00000
195; SI-NEXT:    s_waitcnt lgkmcnt(0)
196; SI-NEXT:    v_mov_b32_e32 v0, s4
197; SI-NEXT:    v_mov_b32_e32 v2, s6
198; SI-NEXT:    buffer_store_dwordx3 v[0:2], off, s[0:3], 0
199; SI-NEXT:    s_endpgm
200;
201; VI-LABEL: insertelement_v3f32_1:
202; VI:       ; %bb.0:
203; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
204; VI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x10
205; VI-NEXT:    s_mov_b32 s3, 0x1100f000
206; VI-NEXT:    s_mov_b32 s2, -1
207; VI-NEXT:    v_mov_b32_e32 v1, 0x40a00000
208; VI-NEXT:    s_waitcnt lgkmcnt(0)
209; VI-NEXT:    v_mov_b32_e32 v0, s4
210; VI-NEXT:    v_mov_b32_e32 v2, s6
211; VI-NEXT:    buffer_store_dwordx3 v[0:2], off, s[0:3], 0
212; VI-NEXT:    s_endpgm
213  %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 1
214  store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16
215  ret void
216}
217
218define amdgpu_kernel void @insertelement_v3f32_2(<3 x float> addrspace(1)* %out, <3 x float> %a) nounwind {
219; SI-LABEL: insertelement_v3f32_2:
220; SI:       ; %bb.0:
221; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
222; SI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x4
223; SI-NEXT:    s_mov_b32 s3, 0x100f000
224; SI-NEXT:    s_mov_b32 s2, -1
225; SI-NEXT:    v_mov_b32_e32 v2, 0x40a00000
226; SI-NEXT:    s_waitcnt lgkmcnt(0)
227; SI-NEXT:    v_mov_b32_e32 v0, s4
228; SI-NEXT:    v_mov_b32_e32 v1, s5
229; SI-NEXT:    buffer_store_dwordx3 v[0:2], off, s[0:3], 0
230; SI-NEXT:    s_endpgm
231;
232; VI-LABEL: insertelement_v3f32_2:
233; VI:       ; %bb.0:
234; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
235; VI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x10
236; VI-NEXT:    s_mov_b32 s3, 0x1100f000
237; VI-NEXT:    s_mov_b32 s2, -1
238; VI-NEXT:    v_mov_b32_e32 v2, 0x40a00000
239; VI-NEXT:    s_waitcnt lgkmcnt(0)
240; VI-NEXT:    v_mov_b32_e32 v0, s4
241; VI-NEXT:    v_mov_b32_e32 v1, s5
242; VI-NEXT:    buffer_store_dwordx3 v[0:2], off, s[0:3], 0
243; VI-NEXT:    s_endpgm
244  %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 2
245  store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16
246  ret void
247}
248
249define amdgpu_kernel void @insertelement_v3f32_3(<3 x float> addrspace(1)* %out, <3 x float> %a) nounwind {
250; GCN-LABEL: insertelement_v3f32_3:
251; GCN:       ; %bb.0:
252; GCN-NEXT:    s_endpgm
253  %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 3
254  store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16
255  ret void
256}
257
258define <4 x float> @insertelement_to_sgpr() nounwind {
259; GCN-LABEL: insertelement_to_sgpr:
260; GCN:       ; %bb.0:
261; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
262; GCN-NEXT:    s_load_dwordx4 s[12:15], s[4:5], 0x0
263; GCN-NEXT:    s_waitcnt lgkmcnt(0)
264; GCN-NEXT:    s_mov_b32 s12, 0
265; GCN-NEXT:    s_mov_b32 s4, s12
266; GCN-NEXT:    s_mov_b32 s5, s12
267; GCN-NEXT:    s_mov_b32 s6, s12
268; GCN-NEXT:    s_mov_b32 s7, s12
269; GCN-NEXT:    s_mov_b32 s8, s12
270; GCN-NEXT:    s_mov_b32 s9, s12
271; GCN-NEXT:    s_mov_b32 s10, s12
272; GCN-NEXT:    s_mov_b32 s11, s12
273; GCN-NEXT:    image_gather4_lz v[0:3], v[0:1], s[4:11], s[12:15] dmask:0x1
274; GCN-NEXT:    s_setpc_b64 s[30:31]
275  %tmp = load <4 x i32>, <4 x i32> addrspace(4)* undef
276  %tmp1 = insertelement <4 x i32> %tmp, i32 0, i32 0
277  %tmp2 = call <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f32(i32 1, float undef, float undef, <8 x i32> undef, <4 x i32> %tmp1, i1 0, i32 0, i32 0)
278  ret <4 x float> %tmp2
279}
280
281define amdgpu_kernel void @dynamic_insertelement_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, i32 %b) nounwind {
282; SI-LABEL: dynamic_insertelement_v2f32:
283; SI:       ; %bb.0:
284; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
285; SI-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x2
286; SI-NEXT:    s_load_dword s4, s[4:5], 0x4
287; SI-NEXT:    v_mov_b32_e32 v0, 0x40a00000
288; SI-NEXT:    s_mov_b32 s3, 0x100f000
289; SI-NEXT:    s_mov_b32 s2, -1
290; SI-NEXT:    s_waitcnt lgkmcnt(0)
291; SI-NEXT:    v_mov_b32_e32 v1, s7
292; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 1
293; SI-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
294; SI-NEXT:    v_mov_b32_e32 v2, s6
295; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 0
296; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
297; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
298; SI-NEXT:    s_endpgm
299;
300; VI-LABEL: dynamic_insertelement_v2f32:
301; VI:       ; %bb.0:
302; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
303; VI-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x8
304; VI-NEXT:    s_load_dword s4, s[4:5], 0x10
305; VI-NEXT:    v_mov_b32_e32 v0, 0x40a00000
306; VI-NEXT:    s_mov_b32 s3, 0x1100f000
307; VI-NEXT:    s_mov_b32 s2, -1
308; VI-NEXT:    s_waitcnt lgkmcnt(0)
309; VI-NEXT:    v_mov_b32_e32 v1, s7
310; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 1
311; VI-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
312; VI-NEXT:    v_mov_b32_e32 v2, s6
313; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 0
314; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
315; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
316; VI-NEXT:    s_endpgm
317  %vecins = insertelement <2 x float> %a, float 5.000000e+00, i32 %b
318  store <2 x float> %vecins, <2 x float> addrspace(1)* %out, align 8
319  ret void
320}
321
322define amdgpu_kernel void @dynamic_insertelement_v3f32(<3 x float> addrspace(1)* %out, <3 x float> %a, i32 %b) nounwind {
323; SI-LABEL: dynamic_insertelement_v3f32:
324; SI:       ; %bb.0:
325; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
326; SI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x4
327; SI-NEXT:    s_load_dword s4, s[4:5], 0x8
328; SI-NEXT:    v_mov_b32_e32 v0, 0x40a00000
329; SI-NEXT:    s_mov_b32 s3, 0x100f000
330; SI-NEXT:    s_mov_b32 s2, -1
331; SI-NEXT:    s_waitcnt lgkmcnt(0)
332; SI-NEXT:    v_mov_b32_e32 v1, s10
333; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 2
334; SI-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
335; SI-NEXT:    v_mov_b32_e32 v1, s9
336; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 1
337; SI-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
338; SI-NEXT:    v_mov_b32_e32 v3, s8
339; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 0
340; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
341; SI-NEXT:    buffer_store_dwordx3 v[0:2], off, s[0:3], 0
342; SI-NEXT:    s_endpgm
343;
344; VI-LABEL: dynamic_insertelement_v3f32:
345; VI:       ; %bb.0:
346; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
347; VI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x10
348; VI-NEXT:    s_load_dword s4, s[4:5], 0x20
349; VI-NEXT:    v_mov_b32_e32 v0, 0x40a00000
350; VI-NEXT:    s_mov_b32 s3, 0x1100f000
351; VI-NEXT:    s_mov_b32 s2, -1
352; VI-NEXT:    s_waitcnt lgkmcnt(0)
353; VI-NEXT:    v_mov_b32_e32 v1, s10
354; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 2
355; VI-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
356; VI-NEXT:    v_mov_b32_e32 v1, s9
357; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 1
358; VI-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
359; VI-NEXT:    v_mov_b32_e32 v3, s8
360; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 0
361; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
362; VI-NEXT:    buffer_store_dwordx3 v[0:2], off, s[0:3], 0
363; VI-NEXT:    s_endpgm
364  %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 %b
365  store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16
366  ret void
367}
368
369define amdgpu_kernel void @dynamic_insertelement_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, i32 %b) nounwind {
370; SI-LABEL: dynamic_insertelement_v4f32:
371; SI:       ; %bb.0:
372; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
373; SI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x4
374; SI-NEXT:    s_load_dword s4, s[4:5], 0x8
375; SI-NEXT:    v_mov_b32_e32 v0, 0x40a00000
376; SI-NEXT:    s_mov_b32 s3, 0x100f000
377; SI-NEXT:    s_mov_b32 s2, -1
378; SI-NEXT:    s_waitcnt lgkmcnt(0)
379; SI-NEXT:    v_mov_b32_e32 v1, s11
380; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 3
381; SI-NEXT:    v_cndmask_b32_e32 v3, v0, v1, vcc
382; SI-NEXT:    v_mov_b32_e32 v1, s10
383; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 2
384; SI-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
385; SI-NEXT:    v_mov_b32_e32 v1, s9
386; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 1
387; SI-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
388; SI-NEXT:    v_mov_b32_e32 v4, s8
389; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 0
390; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
391; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
392; SI-NEXT:    s_endpgm
393;
394; VI-LABEL: dynamic_insertelement_v4f32:
395; VI:       ; %bb.0:
396; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
397; VI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x10
398; VI-NEXT:    s_load_dword s4, s[4:5], 0x20
399; VI-NEXT:    v_mov_b32_e32 v0, 0x40a00000
400; VI-NEXT:    s_mov_b32 s3, 0x1100f000
401; VI-NEXT:    s_mov_b32 s2, -1
402; VI-NEXT:    s_waitcnt lgkmcnt(0)
403; VI-NEXT:    v_mov_b32_e32 v1, s11
404; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 3
405; VI-NEXT:    v_cndmask_b32_e32 v3, v0, v1, vcc
406; VI-NEXT:    v_mov_b32_e32 v1, s10
407; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 2
408; VI-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
409; VI-NEXT:    v_mov_b32_e32 v1, s9
410; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 1
411; VI-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
412; VI-NEXT:    v_mov_b32_e32 v4, s8
413; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 0
414; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
415; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
416; VI-NEXT:    s_endpgm
417  %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 %b
418  store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16
419  ret void
420}
421
422define amdgpu_kernel void @dynamic_insertelement_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, i32 %b) nounwind {
423; SI-LABEL: dynamic_insertelement_v8f32:
424; SI:       ; %bb.0:
425; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
426; SI-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x8
427; SI-NEXT:    s_load_dword s4, s[4:5], 0x10
428; SI-NEXT:    v_mov_b32_e32 v4, 0x40a00000
429; SI-NEXT:    s_mov_b32 s3, 0x100f000
430; SI-NEXT:    s_mov_b32 s2, -1
431; SI-NEXT:    s_waitcnt lgkmcnt(0)
432; SI-NEXT:    v_mov_b32_e32 v0, s11
433; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 3
434; SI-NEXT:    v_cndmask_b32_e32 v3, v4, v0, vcc
435; SI-NEXT:    v_mov_b32_e32 v0, s10
436; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 2
437; SI-NEXT:    v_cndmask_b32_e32 v2, v4, v0, vcc
438; SI-NEXT:    v_mov_b32_e32 v0, s9
439; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 1
440; SI-NEXT:    v_cndmask_b32_e32 v1, v4, v0, vcc
441; SI-NEXT:    v_mov_b32_e32 v0, s8
442; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 0
443; SI-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
444; SI-NEXT:    v_mov_b32_e32 v5, s15
445; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 7
446; SI-NEXT:    v_cndmask_b32_e32 v7, v4, v5, vcc
447; SI-NEXT:    v_mov_b32_e32 v5, s14
448; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 6
449; SI-NEXT:    v_cndmask_b32_e32 v6, v4, v5, vcc
450; SI-NEXT:    v_mov_b32_e32 v5, s13
451; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 5
452; SI-NEXT:    v_cndmask_b32_e32 v5, v4, v5, vcc
453; SI-NEXT:    v_mov_b32_e32 v8, s12
454; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 4
455; SI-NEXT:    v_cndmask_b32_e32 v4, v4, v8, vcc
456; SI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
457; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
458; SI-NEXT:    s_endpgm
459;
460; VI-LABEL: dynamic_insertelement_v8f32:
461; VI:       ; %bb.0:
462; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
463; VI-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x20
464; VI-NEXT:    s_load_dword s4, s[4:5], 0x40
465; VI-NEXT:    v_mov_b32_e32 v4, 0x40a00000
466; VI-NEXT:    s_mov_b32 s3, 0x1100f000
467; VI-NEXT:    s_mov_b32 s2, -1
468; VI-NEXT:    s_waitcnt lgkmcnt(0)
469; VI-NEXT:    v_mov_b32_e32 v0, s11
470; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 3
471; VI-NEXT:    v_cndmask_b32_e32 v3, v4, v0, vcc
472; VI-NEXT:    v_mov_b32_e32 v0, s10
473; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 2
474; VI-NEXT:    v_cndmask_b32_e32 v2, v4, v0, vcc
475; VI-NEXT:    v_mov_b32_e32 v0, s9
476; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 1
477; VI-NEXT:    v_cndmask_b32_e32 v1, v4, v0, vcc
478; VI-NEXT:    v_mov_b32_e32 v0, s8
479; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 0
480; VI-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
481; VI-NEXT:    v_mov_b32_e32 v5, s15
482; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 7
483; VI-NEXT:    v_cndmask_b32_e32 v7, v4, v5, vcc
484; VI-NEXT:    v_mov_b32_e32 v5, s14
485; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 6
486; VI-NEXT:    v_cndmask_b32_e32 v6, v4, v5, vcc
487; VI-NEXT:    v_mov_b32_e32 v5, s13
488; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 5
489; VI-NEXT:    v_cndmask_b32_e32 v5, v4, v5, vcc
490; VI-NEXT:    v_mov_b32_e32 v8, s12
491; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 4
492; VI-NEXT:    v_cndmask_b32_e32 v4, v4, v8, vcc
493; VI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
494; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
495; VI-NEXT:    s_endpgm
496  %vecins = insertelement <8 x float> %a, float 5.000000e+00, i32 %b
497  store <8 x float> %vecins, <8 x float> addrspace(1)* %out, align 32
498  ret void
499}
500
501define amdgpu_kernel void @dynamic_insertelement_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %a, i32 %b) nounwind {
502; SI-LABEL: dynamic_insertelement_v16f32:
503; SI:       ; %bb.0:
504; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
505; SI-NEXT:    s_load_dwordx16 s[8:23], s[4:5], 0x10
506; SI-NEXT:    s_load_dword s4, s[4:5], 0x20
507; SI-NEXT:    v_mov_b32_e32 v16, 0x40a00000
508; SI-NEXT:    s_mov_b32 s3, 0x100f000
509; SI-NEXT:    s_mov_b32 s2, -1
510; SI-NEXT:    s_waitcnt lgkmcnt(0)
511; SI-NEXT:    v_mov_b32_e32 v0, s8
512; SI-NEXT:    v_mov_b32_e32 v1, s9
513; SI-NEXT:    v_mov_b32_e32 v2, s10
514; SI-NEXT:    v_mov_b32_e32 v3, s11
515; SI-NEXT:    v_mov_b32_e32 v4, s12
516; SI-NEXT:    v_mov_b32_e32 v5, s13
517; SI-NEXT:    v_mov_b32_e32 v6, s14
518; SI-NEXT:    v_mov_b32_e32 v7, s15
519; SI-NEXT:    v_mov_b32_e32 v8, s16
520; SI-NEXT:    v_mov_b32_e32 v9, s17
521; SI-NEXT:    v_mov_b32_e32 v10, s18
522; SI-NEXT:    v_mov_b32_e32 v11, s19
523; SI-NEXT:    v_mov_b32_e32 v12, s20
524; SI-NEXT:    v_mov_b32_e32 v13, s21
525; SI-NEXT:    v_mov_b32_e32 v14, s22
526; SI-NEXT:    v_mov_b32_e32 v15, s23
527; SI-NEXT:    s_mov_b32 m0, s4
528; SI-NEXT:    v_movreld_b32_e32 v0, v16
529; SI-NEXT:    buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48
530; SI-NEXT:    buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32
531; SI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
532; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
533; SI-NEXT:    s_endpgm
534;
535; VI-LABEL: dynamic_insertelement_v16f32:
536; VI:       ; %bb.0:
537; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
538; VI-NEXT:    s_load_dwordx16 s[8:23], s[4:5], 0x40
539; VI-NEXT:    s_load_dword s4, s[4:5], 0x80
540; VI-NEXT:    v_mov_b32_e32 v16, 0x40a00000
541; VI-NEXT:    s_mov_b32 s3, 0x1100f000
542; VI-NEXT:    s_mov_b32 s2, -1
543; VI-NEXT:    s_waitcnt lgkmcnt(0)
544; VI-NEXT:    v_mov_b32_e32 v0, s8
545; VI-NEXT:    v_mov_b32_e32 v1, s9
546; VI-NEXT:    v_mov_b32_e32 v2, s10
547; VI-NEXT:    v_mov_b32_e32 v3, s11
548; VI-NEXT:    v_mov_b32_e32 v4, s12
549; VI-NEXT:    v_mov_b32_e32 v5, s13
550; VI-NEXT:    v_mov_b32_e32 v6, s14
551; VI-NEXT:    v_mov_b32_e32 v7, s15
552; VI-NEXT:    v_mov_b32_e32 v8, s16
553; VI-NEXT:    v_mov_b32_e32 v9, s17
554; VI-NEXT:    v_mov_b32_e32 v10, s18
555; VI-NEXT:    v_mov_b32_e32 v11, s19
556; VI-NEXT:    v_mov_b32_e32 v12, s20
557; VI-NEXT:    v_mov_b32_e32 v13, s21
558; VI-NEXT:    v_mov_b32_e32 v14, s22
559; VI-NEXT:    v_mov_b32_e32 v15, s23
560; VI-NEXT:    s_mov_b32 m0, s4
561; VI-NEXT:    v_movreld_b32_e32 v0, v16
562; VI-NEXT:    buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48
563; VI-NEXT:    buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32
564; VI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
565; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
566; VI-NEXT:    s_endpgm
567  %vecins = insertelement <16 x float> %a, float 5.000000e+00, i32 %b
568  store <16 x float> %vecins, <16 x float> addrspace(1)* %out, align 64
569  ret void
570}
571
572define amdgpu_kernel void @dynamic_insertelement_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, i32 %b) nounwind {
573; SI-LABEL: dynamic_insertelement_v2i32:
574; SI:       ; %bb.0:
575; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
576; SI-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x2
577; SI-NEXT:    s_load_dword s4, s[4:5], 0x4
578; SI-NEXT:    s_mov_b32 s3, 0x100f000
579; SI-NEXT:    s_mov_b32 s2, -1
580; SI-NEXT:    s_waitcnt lgkmcnt(0)
581; SI-NEXT:    v_mov_b32_e32 v0, s7
582; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 1
583; SI-NEXT:    v_cndmask_b32_e32 v1, 5, v0, vcc
584; SI-NEXT:    v_mov_b32_e32 v0, s6
585; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 0
586; SI-NEXT:    v_cndmask_b32_e32 v0, 5, v0, vcc
587; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
588; SI-NEXT:    s_endpgm
589;
590; VI-LABEL: dynamic_insertelement_v2i32:
591; VI:       ; %bb.0:
592; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
593; VI-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x8
594; VI-NEXT:    s_load_dword s4, s[4:5], 0x10
595; VI-NEXT:    s_mov_b32 s3, 0x1100f000
596; VI-NEXT:    s_mov_b32 s2, -1
597; VI-NEXT:    s_waitcnt lgkmcnt(0)
598; VI-NEXT:    s_cmp_lg_u32 s4, 1
599; VI-NEXT:    s_cselect_b32 s5, s7, 5
600; VI-NEXT:    s_cmp_lg_u32 s4, 0
601; VI-NEXT:    s_cselect_b32 s4, s6, 5
602; VI-NEXT:    v_mov_b32_e32 v0, s4
603; VI-NEXT:    v_mov_b32_e32 v1, s5
604; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
605; VI-NEXT:    s_endpgm
606  %vecins = insertelement <2 x i32> %a, i32 5, i32 %b
607  store <2 x i32> %vecins, <2 x i32> addrspace(1)* %out, align 8
608  ret void
609}
610
611define amdgpu_kernel void @dynamic_insertelement_v3i32(<3 x i32> addrspace(1)* %out, <3 x i32> %a, i32 %b) nounwind {
612; SI-LABEL: dynamic_insertelement_v3i32:
613; SI:       ; %bb.0:
614; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
615; SI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x4
616; SI-NEXT:    s_load_dword s4, s[4:5], 0x8
617; SI-NEXT:    s_mov_b32 s3, 0x100f000
618; SI-NEXT:    s_mov_b32 s2, -1
619; SI-NEXT:    s_waitcnt lgkmcnt(0)
620; SI-NEXT:    v_mov_b32_e32 v0, s10
621; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 2
622; SI-NEXT:    v_cndmask_b32_e32 v2, 5, v0, vcc
623; SI-NEXT:    v_mov_b32_e32 v0, s9
624; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 1
625; SI-NEXT:    v_cndmask_b32_e32 v1, 5, v0, vcc
626; SI-NEXT:    v_mov_b32_e32 v0, s8
627; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 0
628; SI-NEXT:    v_cndmask_b32_e32 v0, 5, v0, vcc
629; SI-NEXT:    buffer_store_dwordx3 v[0:2], off, s[0:3], 0
630; SI-NEXT:    s_endpgm
631;
632; VI-LABEL: dynamic_insertelement_v3i32:
633; VI:       ; %bb.0:
634; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
635; VI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x10
636; VI-NEXT:    s_load_dword s4, s[4:5], 0x20
637; VI-NEXT:    s_mov_b32 s3, 0x1100f000
638; VI-NEXT:    s_mov_b32 s2, -1
639; VI-NEXT:    s_waitcnt lgkmcnt(0)
640; VI-NEXT:    s_cmp_lg_u32 s4, 2
641; VI-NEXT:    s_cselect_b32 s5, s10, 5
642; VI-NEXT:    s_cmp_lg_u32 s4, 1
643; VI-NEXT:    s_cselect_b32 s6, s9, 5
644; VI-NEXT:    s_cmp_lg_u32 s4, 0
645; VI-NEXT:    s_cselect_b32 s4, s8, 5
646; VI-NEXT:    v_mov_b32_e32 v0, s4
647; VI-NEXT:    v_mov_b32_e32 v1, s6
648; VI-NEXT:    v_mov_b32_e32 v2, s5
649; VI-NEXT:    buffer_store_dwordx3 v[0:2], off, s[0:3], 0
650; VI-NEXT:    s_endpgm
651  %vecins = insertelement <3 x i32> %a, i32 5, i32 %b
652  store <3 x i32> %vecins, <3 x i32> addrspace(1)* %out, align 16
653  ret void
654}
655
656define amdgpu_kernel void @dynamic_insertelement_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, i32 %b, [8 x i32], i32 %val) nounwind {
657; SI-LABEL: dynamic_insertelement_v4i32:
658; SI:       ; %bb.0:
659; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
660; SI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x4
661; SI-NEXT:    s_load_dword s6, s[4:5], 0x8
662; SI-NEXT:    s_load_dword s4, s[4:5], 0x11
663; SI-NEXT:    s_mov_b32 s3, 0x100f000
664; SI-NEXT:    s_mov_b32 s2, -1
665; SI-NEXT:    s_waitcnt lgkmcnt(0)
666; SI-NEXT:    v_mov_b32_e32 v0, s11
667; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s6, 3
668; SI-NEXT:    v_mov_b32_e32 v4, s4
669; SI-NEXT:    v_cndmask_b32_e32 v3, v0, v4, vcc
670; SI-NEXT:    v_mov_b32_e32 v0, s10
671; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s6, 2
672; SI-NEXT:    v_cndmask_b32_e32 v2, v0, v4, vcc
673; SI-NEXT:    v_mov_b32_e32 v0, s9
674; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s6, 1
675; SI-NEXT:    v_cndmask_b32_e32 v1, v0, v4, vcc
676; SI-NEXT:    v_mov_b32_e32 v0, s8
677; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s6, 0
678; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
679; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
680; SI-NEXT:    s_endpgm
681;
682; VI-LABEL: dynamic_insertelement_v4i32:
683; VI:       ; %bb.0:
684; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
685; VI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x10
686; VI-NEXT:    s_load_dword s6, s[4:5], 0x20
687; VI-NEXT:    s_load_dword s4, s[4:5], 0x44
688; VI-NEXT:    s_mov_b32 s3, 0x1100f000
689; VI-NEXT:    s_mov_b32 s2, -1
690; VI-NEXT:    s_waitcnt lgkmcnt(0)
691; VI-NEXT:    s_cmp_eq_u32 s6, 3
692; VI-NEXT:    s_cselect_b32 s5, s4, s11
693; VI-NEXT:    s_cmp_eq_u32 s6, 2
694; VI-NEXT:    s_cselect_b32 s7, s4, s10
695; VI-NEXT:    s_cmp_eq_u32 s6, 1
696; VI-NEXT:    s_cselect_b32 s9, s4, s9
697; VI-NEXT:    s_cmp_eq_u32 s6, 0
698; VI-NEXT:    s_cselect_b32 s4, s4, s8
699; VI-NEXT:    v_mov_b32_e32 v0, s4
700; VI-NEXT:    v_mov_b32_e32 v1, s9
701; VI-NEXT:    v_mov_b32_e32 v2, s7
702; VI-NEXT:    v_mov_b32_e32 v3, s5
703; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
704; VI-NEXT:    s_endpgm
705  %vecins = insertelement <4 x i32> %a, i32 %val, i32 %b
706  store <4 x i32> %vecins, <4 x i32> addrspace(1)* %out, align 16
707  ret void
708}
709
710define amdgpu_kernel void @dynamic_insertelement_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> %a, i32 %b) nounwind {
711; SI-LABEL: dynamic_insertelement_v8i32:
712; SI:       ; %bb.0:
713; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
714; SI-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x8
715; SI-NEXT:    s_load_dword s4, s[4:5], 0x10
716; SI-NEXT:    s_mov_b32 s3, 0x100f000
717; SI-NEXT:    s_mov_b32 s2, -1
718; SI-NEXT:    s_waitcnt lgkmcnt(0)
719; SI-NEXT:    v_mov_b32_e32 v0, s11
720; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 3
721; SI-NEXT:    v_cndmask_b32_e32 v3, 5, v0, vcc
722; SI-NEXT:    v_mov_b32_e32 v0, s10
723; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 2
724; SI-NEXT:    v_cndmask_b32_e32 v2, 5, v0, vcc
725; SI-NEXT:    v_mov_b32_e32 v0, s9
726; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 1
727; SI-NEXT:    v_cndmask_b32_e32 v1, 5, v0, vcc
728; SI-NEXT:    v_mov_b32_e32 v0, s8
729; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 0
730; SI-NEXT:    v_cndmask_b32_e32 v0, 5, v0, vcc
731; SI-NEXT:    v_mov_b32_e32 v4, s15
732; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 7
733; SI-NEXT:    v_cndmask_b32_e32 v7, 5, v4, vcc
734; SI-NEXT:    v_mov_b32_e32 v4, s14
735; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 6
736; SI-NEXT:    v_cndmask_b32_e32 v6, 5, v4, vcc
737; SI-NEXT:    v_mov_b32_e32 v4, s13
738; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 5
739; SI-NEXT:    v_cndmask_b32_e32 v5, 5, v4, vcc
740; SI-NEXT:    v_mov_b32_e32 v4, s12
741; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 4
742; SI-NEXT:    v_cndmask_b32_e32 v4, 5, v4, vcc
743; SI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
744; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
745; SI-NEXT:    s_endpgm
746;
747; VI-LABEL: dynamic_insertelement_v8i32:
748; VI:       ; %bb.0:
749; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
750; VI-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x20
751; VI-NEXT:    s_load_dword s4, s[4:5], 0x40
752; VI-NEXT:    s_mov_b32 s3, 0x1100f000
753; VI-NEXT:    s_mov_b32 s2, -1
754; VI-NEXT:    s_waitcnt lgkmcnt(0)
755; VI-NEXT:    s_cmp_lg_u32 s4, 3
756; VI-NEXT:    s_cselect_b32 s5, s11, 5
757; VI-NEXT:    s_cmp_lg_u32 s4, 2
758; VI-NEXT:    s_cselect_b32 s6, s10, 5
759; VI-NEXT:    s_cmp_lg_u32 s4, 1
760; VI-NEXT:    s_cselect_b32 s7, s9, 5
761; VI-NEXT:    s_cmp_lg_u32 s4, 0
762; VI-NEXT:    s_cselect_b32 s8, s8, 5
763; VI-NEXT:    s_cmp_lg_u32 s4, 7
764; VI-NEXT:    s_cselect_b32 s9, s15, 5
765; VI-NEXT:    s_cmp_lg_u32 s4, 6
766; VI-NEXT:    s_cselect_b32 s10, s14, 5
767; VI-NEXT:    s_cmp_lg_u32 s4, 5
768; VI-NEXT:    s_cselect_b32 s11, s13, 5
769; VI-NEXT:    s_cmp_lg_u32 s4, 4
770; VI-NEXT:    s_cselect_b32 s4, s12, 5
771; VI-NEXT:    v_mov_b32_e32 v0, s4
772; VI-NEXT:    v_mov_b32_e32 v1, s11
773; VI-NEXT:    v_mov_b32_e32 v2, s10
774; VI-NEXT:    v_mov_b32_e32 v3, s9
775; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
776; VI-NEXT:    s_nop 0
777; VI-NEXT:    v_mov_b32_e32 v0, s8
778; VI-NEXT:    v_mov_b32_e32 v1, s7
779; VI-NEXT:    v_mov_b32_e32 v2, s6
780; VI-NEXT:    v_mov_b32_e32 v3, s5
781; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
782; VI-NEXT:    s_endpgm
783  %vecins = insertelement <8 x i32> %a, i32 5, i32 %b
784  store <8 x i32> %vecins, <8 x i32> addrspace(1)* %out, align 32
785  ret void
786}
787
788define amdgpu_kernel void @dynamic_insertelement_v16i32(<16 x i32> addrspace(1)* %out, <16 x i32> %a, i32 %b) nounwind {
789; SI-LABEL: dynamic_insertelement_v16i32:
790; SI:       ; %bb.0:
791; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
792; SI-NEXT:    s_load_dwordx16 s[8:23], s[4:5], 0x10
793; SI-NEXT:    s_load_dword s4, s[4:5], 0x20
794; SI-NEXT:    s_mov_b32 s3, 0x100f000
795; SI-NEXT:    s_mov_b32 s2, -1
796; SI-NEXT:    s_waitcnt lgkmcnt(0)
797; SI-NEXT:    v_mov_b32_e32 v0, s8
798; SI-NEXT:    v_mov_b32_e32 v1, s9
799; SI-NEXT:    v_mov_b32_e32 v2, s10
800; SI-NEXT:    v_mov_b32_e32 v3, s11
801; SI-NEXT:    v_mov_b32_e32 v4, s12
802; SI-NEXT:    v_mov_b32_e32 v5, s13
803; SI-NEXT:    v_mov_b32_e32 v6, s14
804; SI-NEXT:    v_mov_b32_e32 v7, s15
805; SI-NEXT:    v_mov_b32_e32 v8, s16
806; SI-NEXT:    v_mov_b32_e32 v9, s17
807; SI-NEXT:    v_mov_b32_e32 v10, s18
808; SI-NEXT:    v_mov_b32_e32 v11, s19
809; SI-NEXT:    v_mov_b32_e32 v12, s20
810; SI-NEXT:    v_mov_b32_e32 v13, s21
811; SI-NEXT:    v_mov_b32_e32 v14, s22
812; SI-NEXT:    v_mov_b32_e32 v15, s23
813; SI-NEXT:    s_mov_b32 m0, s4
814; SI-NEXT:    v_movreld_b32_e32 v0, 5
815; SI-NEXT:    buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48
816; SI-NEXT:    buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32
817; SI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
818; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
819; SI-NEXT:    s_endpgm
820;
821; VI-LABEL: dynamic_insertelement_v16i32:
822; VI:       ; %bb.0:
823; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
824; VI-NEXT:    s_load_dwordx16 s[8:23], s[4:5], 0x40
825; VI-NEXT:    s_load_dword s4, s[4:5], 0x80
826; VI-NEXT:    s_mov_b32 s3, 0x1100f000
827; VI-NEXT:    s_mov_b32 s2, -1
828; VI-NEXT:    s_waitcnt lgkmcnt(0)
829; VI-NEXT:    v_mov_b32_e32 v0, s8
830; VI-NEXT:    v_mov_b32_e32 v1, s9
831; VI-NEXT:    v_mov_b32_e32 v2, s10
832; VI-NEXT:    v_mov_b32_e32 v3, s11
833; VI-NEXT:    v_mov_b32_e32 v4, s12
834; VI-NEXT:    v_mov_b32_e32 v5, s13
835; VI-NEXT:    v_mov_b32_e32 v6, s14
836; VI-NEXT:    v_mov_b32_e32 v7, s15
837; VI-NEXT:    v_mov_b32_e32 v8, s16
838; VI-NEXT:    v_mov_b32_e32 v9, s17
839; VI-NEXT:    v_mov_b32_e32 v10, s18
840; VI-NEXT:    v_mov_b32_e32 v11, s19
841; VI-NEXT:    v_mov_b32_e32 v12, s20
842; VI-NEXT:    v_mov_b32_e32 v13, s21
843; VI-NEXT:    v_mov_b32_e32 v14, s22
844; VI-NEXT:    v_mov_b32_e32 v15, s23
845; VI-NEXT:    s_mov_b32 m0, s4
846; VI-NEXT:    v_movreld_b32_e32 v0, 5
847; VI-NEXT:    buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48
848; VI-NEXT:    buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32
849; VI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
850; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
851; VI-NEXT:    s_endpgm
852  %vecins = insertelement <16 x i32> %a, i32 5, i32 %b
853  store <16 x i32> %vecins, <16 x i32> addrspace(1)* %out, align 64
854  ret void
855}
856
857define amdgpu_kernel void @dynamic_insertelement_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %a, i32 %b) nounwind {
858; SI-LABEL: dynamic_insertelement_v2i16:
859; SI:       ; %bb.0:
860; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
861; SI-NEXT:    s_load_dword s6, s[4:5], 0x2
862; SI-NEXT:    s_load_dword s4, s[4:5], 0x3
863; SI-NEXT:    v_mov_b32_e32 v0, 0x50005
864; SI-NEXT:    s_mov_b32 s3, 0x100f000
865; SI-NEXT:    s_mov_b32 s2, -1
866; SI-NEXT:    s_waitcnt lgkmcnt(0)
867; SI-NEXT:    v_mov_b32_e32 v1, s6
868; SI-NEXT:    s_lshl_b32 s4, s4, 4
869; SI-NEXT:    s_lshl_b32 s4, 0xffff, s4
870; SI-NEXT:    v_bfi_b32 v0, s4, v0, v1
871; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
872; SI-NEXT:    s_endpgm
873;
874; VI-LABEL: dynamic_insertelement_v2i16:
875; VI:       ; %bb.0:
876; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
877; VI-NEXT:    s_load_dword s6, s[4:5], 0x8
878; VI-NEXT:    s_load_dword s4, s[4:5], 0xc
879; VI-NEXT:    v_mov_b32_e32 v0, 0x50005
880; VI-NEXT:    s_mov_b32 s3, 0x1100f000
881; VI-NEXT:    s_mov_b32 s2, -1
882; VI-NEXT:    s_waitcnt lgkmcnt(0)
883; VI-NEXT:    v_mov_b32_e32 v1, s6
884; VI-NEXT:    s_lshl_b32 s4, s4, 4
885; VI-NEXT:    s_lshl_b32 s4, 0xffff, s4
886; VI-NEXT:    v_bfi_b32 v0, s4, v0, v1
887; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
888; VI-NEXT:    s_endpgm
889  %vecins = insertelement <2 x i16> %a, i16 5, i32 %b
890  store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out, align 8
891  ret void
892}
893
894define amdgpu_kernel void @dynamic_insertelement_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %a, i32 %b) nounwind {
895; SI-LABEL: dynamic_insertelement_v3i16:
896; SI:       ; %bb.0:
897; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
898; SI-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x2
899; SI-NEXT:    s_load_dword s4, s[4:5], 0x4
900; SI-NEXT:    s_mov_b32 s5, 0
901; SI-NEXT:    s_mov_b32 s3, 0x100f000
902; SI-NEXT:    s_mov_b32 s2, -1
903; SI-NEXT:    s_waitcnt lgkmcnt(0)
904; SI-NEXT:    s_lshl_b32 s8, s4, 4
905; SI-NEXT:    s_mov_b32 s4, 0xffff
906; SI-NEXT:    s_lshl_b64 s[4:5], s[4:5], s8
907; SI-NEXT:    s_mov_b32 s8, 0x50005
908; SI-NEXT:    s_and_b32 s9, s5, s8
909; SI-NEXT:    s_and_b32 s8, s4, s8
910; SI-NEXT:    s_andn2_b64 s[4:5], s[6:7], s[4:5]
911; SI-NEXT:    s_or_b64 s[4:5], s[8:9], s[4:5]
912; SI-NEXT:    v_mov_b32_e32 v0, s5
913; SI-NEXT:    buffer_store_short v0, off, s[0:3], 0 offset:4
914; SI-NEXT:    v_mov_b32_e32 v0, s4
915; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
916; SI-NEXT:    s_endpgm
917;
918; VI-LABEL: dynamic_insertelement_v3i16:
919; VI:       ; %bb.0:
920; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
921; VI-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x8
922; VI-NEXT:    s_load_dword s4, s[4:5], 0x10
923; VI-NEXT:    s_mov_b32 s5, 0
924; VI-NEXT:    s_mov_b32 s3, 0x1100f000
925; VI-NEXT:    s_mov_b32 s2, -1
926; VI-NEXT:    s_waitcnt lgkmcnt(0)
927; VI-NEXT:    v_mov_b32_e32 v1, s7
928; VI-NEXT:    s_lshl_b32 s8, s4, 4
929; VI-NEXT:    s_mov_b32 s4, 0xffff
930; VI-NEXT:    s_lshl_b64 s[4:5], s[4:5], s8
931; VI-NEXT:    s_mov_b32 s8, 0x50005
932; VI-NEXT:    v_mov_b32_e32 v0, s8
933; VI-NEXT:    v_bfi_b32 v0, s5, v0, v1
934; VI-NEXT:    v_mov_b32_e32 v1, s8
935; VI-NEXT:    v_mov_b32_e32 v2, s6
936; VI-NEXT:    v_bfi_b32 v1, s4, v1, v2
937; VI-NEXT:    buffer_store_short v0, off, s[0:3], 0 offset:4
938; VI-NEXT:    buffer_store_dword v1, off, s[0:3], 0
939; VI-NEXT:    s_endpgm
940  %vecins = insertelement <3 x i16> %a, i16 5, i32 %b
941  store <3 x i16> %vecins, <3 x i16> addrspace(1)* %out, align 8
942  ret void
943}
944
945define amdgpu_kernel void @dynamic_insertelement_v2i8(<2 x i8> addrspace(1)* %out, [8 x i32], <2 x i8> %a, [8 x i32], i32 %b) nounwind {
946; SI-LABEL: dynamic_insertelement_v2i8:
947; SI:       ; %bb.0:
948; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
949; SI-NEXT:    s_load_dword s6, s[4:5], 0xa
950; SI-NEXT:    s_load_dword s4, s[4:5], 0x13
951; SI-NEXT:    v_mov_b32_e32 v0, 0x505
952; SI-NEXT:    s_mov_b32 s3, 0x100f000
953; SI-NEXT:    s_mov_b32 s2, -1
954; SI-NEXT:    s_waitcnt lgkmcnt(0)
955; SI-NEXT:    v_mov_b32_e32 v1, s6
956; SI-NEXT:    s_lshl_b32 s4, s4, 3
957; SI-NEXT:    s_lshl_b32 s4, -1, s4
958; SI-NEXT:    v_bfi_b32 v0, s4, v0, v1
959; SI-NEXT:    buffer_store_short v0, off, s[0:3], 0
960; SI-NEXT:    s_endpgm
961;
962; VI-LABEL: dynamic_insertelement_v2i8:
963; VI:       ; %bb.0:
964; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
965; VI-NEXT:    s_load_dword s6, s[4:5], 0x28
966; VI-NEXT:    s_load_dword s4, s[4:5], 0x4c
967; VI-NEXT:    s_mov_b32 s3, 0x1100f000
968; VI-NEXT:    s_mov_b32 s2, -1
969; VI-NEXT:    s_waitcnt lgkmcnt(0)
970; VI-NEXT:    s_lshl_b32 s4, s4, 3
971; VI-NEXT:    v_lshlrev_b16_e64 v0, s4, -1
972; VI-NEXT:    v_not_b32_e32 v1, v0
973; VI-NEXT:    v_and_b32_e32 v1, s6, v1
974; VI-NEXT:    v_and_b32_e32 v0, 0x505, v0
975; VI-NEXT:    v_or_b32_e32 v0, v0, v1
976; VI-NEXT:    buffer_store_short v0, off, s[0:3], 0
977; VI-NEXT:    s_endpgm
978  %vecins = insertelement <2 x i8> %a, i8 5, i32 %b
979  store <2 x i8> %vecins, <2 x i8> addrspace(1)* %out, align 8
980  ret void
981}
982
983; FIXME: post legalize i16 and i32 shifts aren't merged because of
984; isTypeDesirableForOp in SimplifyDemandedBits
985define amdgpu_kernel void @dynamic_insertelement_v3i8(<3 x i8> addrspace(1)* %out, [8 x i32], <3 x i8> %a, [8 x i32], i32 %b) nounwind {
986; SI-LABEL: dynamic_insertelement_v3i8:
987; SI:       ; %bb.0:
988; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
989; SI-NEXT:    s_load_dword s6, s[4:5], 0xa
990; SI-NEXT:    s_load_dword s4, s[4:5], 0x13
991; SI-NEXT:    v_mov_b32_e32 v0, 0x5050505
992; SI-NEXT:    s_mov_b32 s3, 0x100f000
993; SI-NEXT:    s_mov_b32 s2, -1
994; SI-NEXT:    s_waitcnt lgkmcnt(0)
995; SI-NEXT:    v_mov_b32_e32 v1, s6
996; SI-NEXT:    s_lshl_b32 s4, s4, 3
997; SI-NEXT:    s_lshl_b32 s4, 0xffff, s4
998; SI-NEXT:    v_bfi_b32 v0, s4, v0, v1
999; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
1000; SI-NEXT:    buffer_store_short v0, off, s[0:3], 0
1001; SI-NEXT:    buffer_store_byte v1, off, s[0:3], 0 offset:2
1002; SI-NEXT:    s_endpgm
1003;
1004; VI-LABEL: dynamic_insertelement_v3i8:
1005; VI:       ; %bb.0:
1006; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
1007; VI-NEXT:    s_load_dword s6, s[4:5], 0x28
1008; VI-NEXT:    s_load_dword s4, s[4:5], 0x4c
1009; VI-NEXT:    v_mov_b32_e32 v0, 0x5050505
1010; VI-NEXT:    s_mov_b32 s3, 0x1100f000
1011; VI-NEXT:    s_mov_b32 s2, -1
1012; VI-NEXT:    s_waitcnt lgkmcnt(0)
1013; VI-NEXT:    v_mov_b32_e32 v1, s6
1014; VI-NEXT:    s_lshl_b32 s4, s4, 3
1015; VI-NEXT:    s_lshl_b32 s4, 0xffff, s4
1016; VI-NEXT:    v_bfi_b32 v0, s4, v0, v1
1017; VI-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
1018; VI-NEXT:    buffer_store_short v0, off, s[0:3], 0
1019; VI-NEXT:    buffer_store_byte v1, off, s[0:3], 0 offset:2
1020; VI-NEXT:    s_endpgm
1021  %vecins = insertelement <3 x i8> %a, i8 5, i32 %b
1022  store <3 x i8> %vecins, <3 x i8> addrspace(1)* %out, align 4
1023  ret void
1024}
1025
1026define amdgpu_kernel void @dynamic_insertelement_v4i8(<4 x i8> addrspace(1)* %out, [8 x i32], <4 x i8> %a, [8 x i32], i32 %b) nounwind {
1027; SI-LABEL: dynamic_insertelement_v4i8:
1028; SI:       ; %bb.0:
1029; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
1030; SI-NEXT:    s_load_dword s6, s[4:5], 0xa
1031; SI-NEXT:    s_load_dword s4, s[4:5], 0x13
1032; SI-NEXT:    v_mov_b32_e32 v0, 0x5050505
1033; SI-NEXT:    s_mov_b32 s3, 0x100f000
1034; SI-NEXT:    s_mov_b32 s2, -1
1035; SI-NEXT:    s_waitcnt lgkmcnt(0)
1036; SI-NEXT:    v_mov_b32_e32 v1, s6
1037; SI-NEXT:    s_lshl_b32 s4, s4, 3
1038; SI-NEXT:    s_lshl_b32 s4, 0xffff, s4
1039; SI-NEXT:    v_bfi_b32 v0, s4, v0, v1
1040; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
1041; SI-NEXT:    s_endpgm
1042;
1043; VI-LABEL: dynamic_insertelement_v4i8:
1044; VI:       ; %bb.0:
1045; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
1046; VI-NEXT:    s_load_dword s6, s[4:5], 0x28
1047; VI-NEXT:    s_load_dword s4, s[4:5], 0x4c
1048; VI-NEXT:    v_mov_b32_e32 v0, 0x5050505
1049; VI-NEXT:    s_mov_b32 s3, 0x1100f000
1050; VI-NEXT:    s_mov_b32 s2, -1
1051; VI-NEXT:    s_waitcnt lgkmcnt(0)
1052; VI-NEXT:    v_mov_b32_e32 v1, s6
1053; VI-NEXT:    s_lshl_b32 s4, s4, 3
1054; VI-NEXT:    s_lshl_b32 s4, 0xffff, s4
1055; VI-NEXT:    v_bfi_b32 v0, s4, v0, v1
1056; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
1057; VI-NEXT:    s_endpgm
1058  %vecins = insertelement <4 x i8> %a, i8 5, i32 %b
1059  store <4 x i8> %vecins, <4 x i8> addrspace(1)* %out, align 4
1060  ret void
1061}
1062
1063define amdgpu_kernel void @s_dynamic_insertelement_v8i8(<8 x i8> addrspace(1)* %out, <8 x i8> addrspace(4)* %a.ptr, i32 %b) nounwind {
1064; SI-LABEL: s_dynamic_insertelement_v8i8:
1065; SI:       ; %bb.0:
1066; SI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x0
1067; SI-NEXT:    s_load_dword s6, s[4:5], 0x4
1068; SI-NEXT:    s_mov_b32 s7, 0
1069; SI-NEXT:    s_mov_b32 s3, 0x100f000
1070; SI-NEXT:    s_mov_b32 s2, -1
1071; SI-NEXT:    s_waitcnt lgkmcnt(0)
1072; SI-NEXT:    s_load_dwordx2 s[4:5], s[10:11], 0x0
1073; SI-NEXT:    s_mov_b32 s0, s8
1074; SI-NEXT:    s_lshl_b32 s8, s6, 3
1075; SI-NEXT:    s_mov_b32 s6, 0xffff
1076; SI-NEXT:    s_lshl_b64 s[6:7], s[6:7], s8
1077; SI-NEXT:    s_mov_b32 s8, 0x5050505
1078; SI-NEXT:    s_mov_b32 s1, s9
1079; SI-NEXT:    s_and_b32 s9, s7, s8
1080; SI-NEXT:    s_and_b32 s8, s6, s8
1081; SI-NEXT:    s_waitcnt lgkmcnt(0)
1082; SI-NEXT:    s_andn2_b64 s[4:5], s[4:5], s[6:7]
1083; SI-NEXT:    s_or_b64 s[4:5], s[8:9], s[4:5]
1084; SI-NEXT:    v_mov_b32_e32 v0, s4
1085; SI-NEXT:    v_mov_b32_e32 v1, s5
1086; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1087; SI-NEXT:    s_endpgm
1088;
1089; VI-LABEL: s_dynamic_insertelement_v8i8:
1090; VI:       ; %bb.0:
1091; VI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x0
1092; VI-NEXT:    s_load_dword s6, s[4:5], 0x10
1093; VI-NEXT:    s_mov_b32 s7, 0
1094; VI-NEXT:    s_mov_b32 s3, 0x1100f000
1095; VI-NEXT:    s_mov_b32 s2, -1
1096; VI-NEXT:    s_waitcnt lgkmcnt(0)
1097; VI-NEXT:    s_load_dwordx2 s[4:5], s[10:11], 0x0
1098; VI-NEXT:    s_mov_b32 s0, s8
1099; VI-NEXT:    s_lshl_b32 s8, s6, 3
1100; VI-NEXT:    s_mov_b32 s6, 0xffff
1101; VI-NEXT:    s_lshl_b64 s[6:7], s[6:7], s8
1102; VI-NEXT:    s_mov_b32 s8, 0x5050505
1103; VI-NEXT:    s_mov_b32 s1, s9
1104; VI-NEXT:    s_and_b32 s9, s7, s8
1105; VI-NEXT:    s_and_b32 s8, s6, s8
1106; VI-NEXT:    s_waitcnt lgkmcnt(0)
1107; VI-NEXT:    s_andn2_b64 s[4:5], s[4:5], s[6:7]
1108; VI-NEXT:    s_or_b64 s[4:5], s[8:9], s[4:5]
1109; VI-NEXT:    v_mov_b32_e32 v0, s4
1110; VI-NEXT:    v_mov_b32_e32 v1, s5
1111; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1112; VI-NEXT:    s_endpgm
1113  %a = load <8 x i8>, <8 x i8> addrspace(4)* %a.ptr, align 4
1114  %vecins = insertelement <8 x i8> %a, i8 5, i32 %b
1115  store <8 x i8> %vecins, <8 x i8> addrspace(1)* %out, align 8
1116  ret void
1117}
1118
1119define amdgpu_kernel void @dynamic_insertelement_v16i8(<16 x i8> addrspace(1)* %out, <16 x i8> %a, i32 %b) nounwind {
1120; SI-LABEL: dynamic_insertelement_v16i8:
1121; SI:       ; %bb.0:
1122; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
1123; SI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x4
1124; SI-NEXT:    s_load_dword s4, s[4:5], 0x8
1125; SI-NEXT:    s_mov_b32 s3, 0x100f000
1126; SI-NEXT:    s_mov_b32 s2, -1
1127; SI-NEXT:    s_waitcnt lgkmcnt(0)
1128; SI-NEXT:    s_lshr_b32 s5, s11, 24
1129; SI-NEXT:    v_mov_b32_e32 v0, s5
1130; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 15
1131; SI-NEXT:    s_lshr_b32 s5, s11, 16
1132; SI-NEXT:    v_cndmask_b32_e32 v0, 5, v0, vcc
1133; SI-NEXT:    v_mov_b32_e32 v1, s5
1134; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 14
1135; SI-NEXT:    v_cndmask_b32_e32 v1, 5, v1, vcc
1136; SI-NEXT:    s_movk_i32 s5, 0xff
1137; SI-NEXT:    v_lshlrev_b32_e32 v0, 8, v0
1138; SI-NEXT:    v_and_b32_e32 v1, s5, v1
1139; SI-NEXT:    s_lshr_b32 s6, s11, 8
1140; SI-NEXT:    v_or_b32_e32 v0, v1, v0
1141; SI-NEXT:    v_mov_b32_e32 v1, s6
1142; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 13
1143; SI-NEXT:    v_cndmask_b32_e32 v1, 5, v1, vcc
1144; SI-NEXT:    v_mov_b32_e32 v2, s11
1145; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 12
1146; SI-NEXT:    v_cndmask_b32_e32 v2, 5, v2, vcc
1147; SI-NEXT:    v_lshlrev_b32_e32 v1, 8, v1
1148; SI-NEXT:    v_and_b32_e32 v2, s5, v2
1149; SI-NEXT:    v_or_b32_e32 v1, v2, v1
1150; SI-NEXT:    s_mov_b32 s6, 0xffff
1151; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
1152; SI-NEXT:    v_and_b32_e32 v1, s6, v1
1153; SI-NEXT:    s_lshr_b32 s7, s10, 24
1154; SI-NEXT:    v_or_b32_e32 v3, v1, v0
1155; SI-NEXT:    v_mov_b32_e32 v0, s7
1156; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 11
1157; SI-NEXT:    s_lshr_b32 s7, s10, 16
1158; SI-NEXT:    v_cndmask_b32_e32 v0, 5, v0, vcc
1159; SI-NEXT:    v_mov_b32_e32 v1, s7
1160; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 10
1161; SI-NEXT:    v_cndmask_b32_e32 v1, 5, v1, vcc
1162; SI-NEXT:    v_lshlrev_b32_e32 v0, 8, v0
1163; SI-NEXT:    v_and_b32_e32 v1, s5, v1
1164; SI-NEXT:    s_lshr_b32 s7, s10, 8
1165; SI-NEXT:    v_or_b32_e32 v0, v1, v0
1166; SI-NEXT:    v_mov_b32_e32 v1, s7
1167; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 9
1168; SI-NEXT:    v_cndmask_b32_e32 v1, 5, v1, vcc
1169; SI-NEXT:    v_mov_b32_e32 v2, s10
1170; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 8
1171; SI-NEXT:    v_cndmask_b32_e32 v2, 5, v2, vcc
1172; SI-NEXT:    v_lshlrev_b32_e32 v1, 8, v1
1173; SI-NEXT:    v_and_b32_e32 v2, s5, v2
1174; SI-NEXT:    v_or_b32_e32 v1, v2, v1
1175; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
1176; SI-NEXT:    v_and_b32_e32 v1, s6, v1
1177; SI-NEXT:    s_lshr_b32 s7, s9, 24
1178; SI-NEXT:    v_or_b32_e32 v2, v1, v0
1179; SI-NEXT:    v_mov_b32_e32 v0, s7
1180; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 7
1181; SI-NEXT:    s_lshr_b32 s7, s9, 16
1182; SI-NEXT:    v_cndmask_b32_e32 v0, 5, v0, vcc
1183; SI-NEXT:    v_mov_b32_e32 v1, s7
1184; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 6
1185; SI-NEXT:    v_cndmask_b32_e32 v1, 5, v1, vcc
1186; SI-NEXT:    v_lshlrev_b32_e32 v0, 8, v0
1187; SI-NEXT:    v_and_b32_e32 v1, s5, v1
1188; SI-NEXT:    s_lshr_b32 s7, s9, 8
1189; SI-NEXT:    v_or_b32_e32 v0, v1, v0
1190; SI-NEXT:    v_mov_b32_e32 v1, s7
1191; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 5
1192; SI-NEXT:    v_cndmask_b32_e32 v1, 5, v1, vcc
1193; SI-NEXT:    v_mov_b32_e32 v4, s9
1194; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 4
1195; SI-NEXT:    v_cndmask_b32_e32 v4, 5, v4, vcc
1196; SI-NEXT:    v_lshlrev_b32_e32 v1, 8, v1
1197; SI-NEXT:    v_and_b32_e32 v4, s5, v4
1198; SI-NEXT:    v_or_b32_e32 v1, v4, v1
1199; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
1200; SI-NEXT:    v_and_b32_e32 v1, s6, v1
1201; SI-NEXT:    s_lshr_b32 s7, s8, 24
1202; SI-NEXT:    v_or_b32_e32 v1, v1, v0
1203; SI-NEXT:    v_mov_b32_e32 v0, s7
1204; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 3
1205; SI-NEXT:    s_lshr_b32 s7, s8, 16
1206; SI-NEXT:    v_cndmask_b32_e32 v0, 5, v0, vcc
1207; SI-NEXT:    v_mov_b32_e32 v4, s7
1208; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 2
1209; SI-NEXT:    v_cndmask_b32_e32 v4, 5, v4, vcc
1210; SI-NEXT:    v_lshlrev_b32_e32 v0, 8, v0
1211; SI-NEXT:    v_and_b32_e32 v4, s5, v4
1212; SI-NEXT:    s_lshr_b32 s7, s8, 8
1213; SI-NEXT:    v_or_b32_e32 v0, v4, v0
1214; SI-NEXT:    v_mov_b32_e32 v4, s7
1215; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 1
1216; SI-NEXT:    v_cndmask_b32_e32 v4, 5, v4, vcc
1217; SI-NEXT:    v_mov_b32_e32 v5, s8
1218; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 0
1219; SI-NEXT:    v_cndmask_b32_e32 v5, 5, v5, vcc
1220; SI-NEXT:    v_lshlrev_b32_e32 v4, 8, v4
1221; SI-NEXT:    v_and_b32_e32 v5, s5, v5
1222; SI-NEXT:    v_or_b32_e32 v4, v5, v4
1223; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
1224; SI-NEXT:    v_and_b32_e32 v4, s6, v4
1225; SI-NEXT:    v_or_b32_e32 v0, v4, v0
1226; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
1227; SI-NEXT:    s_endpgm
1228;
1229; VI-LABEL: dynamic_insertelement_v16i8:
1230; VI:       ; %bb.0:
1231; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
1232; VI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x10
1233; VI-NEXT:    s_load_dword s4, s[4:5], 0x20
1234; VI-NEXT:    s_mov_b32 s3, 0x1100f000
1235; VI-NEXT:    s_mov_b32 s2, -1
1236; VI-NEXT:    s_waitcnt lgkmcnt(0)
1237; VI-NEXT:    s_lshr_b32 s5, s11, 24
1238; VI-NEXT:    v_mov_b32_e32 v0, s5
1239; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 15
1240; VI-NEXT:    s_lshr_b32 s5, s11, 16
1241; VI-NEXT:    v_cndmask_b32_e32 v0, 5, v0, vcc
1242; VI-NEXT:    v_mov_b32_e32 v1, s5
1243; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 14
1244; VI-NEXT:    v_cndmask_b32_e32 v1, 5, v1, vcc
1245; VI-NEXT:    v_lshlrev_b16_e32 v0, 8, v0
1246; VI-NEXT:    s_lshr_b32 s5, s11, 8
1247; VI-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
1248; VI-NEXT:    v_mov_b32_e32 v1, s5
1249; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 13
1250; VI-NEXT:    v_cndmask_b32_e32 v1, 5, v1, vcc
1251; VI-NEXT:    v_mov_b32_e32 v2, s11
1252; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 12
1253; VI-NEXT:    v_cndmask_b32_e32 v2, 5, v2, vcc
1254; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v1
1255; VI-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
1256; VI-NEXT:    s_lshr_b32 s5, s10, 24
1257; VI-NEXT:    v_or_b32_sdwa v3, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
1258; VI-NEXT:    v_mov_b32_e32 v0, s5
1259; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 11
1260; VI-NEXT:    s_lshr_b32 s5, s10, 16
1261; VI-NEXT:    v_cndmask_b32_e32 v0, 5, v0, vcc
1262; VI-NEXT:    v_mov_b32_e32 v1, s5
1263; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 10
1264; VI-NEXT:    v_cndmask_b32_e32 v1, 5, v1, vcc
1265; VI-NEXT:    v_lshlrev_b16_e32 v0, 8, v0
1266; VI-NEXT:    s_lshr_b32 s5, s10, 8
1267; VI-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
1268; VI-NEXT:    v_mov_b32_e32 v1, s5
1269; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 9
1270; VI-NEXT:    v_cndmask_b32_e32 v1, 5, v1, vcc
1271; VI-NEXT:    v_mov_b32_e32 v2, s10
1272; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 8
1273; VI-NEXT:    v_cndmask_b32_e32 v2, 5, v2, vcc
1274; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v1
1275; VI-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
1276; VI-NEXT:    s_lshr_b32 s5, s9, 24
1277; VI-NEXT:    v_or_b32_sdwa v2, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
1278; VI-NEXT:    v_mov_b32_e32 v0, s5
1279; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 7
1280; VI-NEXT:    s_lshr_b32 s5, s9, 16
1281; VI-NEXT:    v_cndmask_b32_e32 v0, 5, v0, vcc
1282; VI-NEXT:    v_mov_b32_e32 v1, s5
1283; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 6
1284; VI-NEXT:    v_cndmask_b32_e32 v1, 5, v1, vcc
1285; VI-NEXT:    v_lshlrev_b16_e32 v0, 8, v0
1286; VI-NEXT:    s_lshr_b32 s5, s9, 8
1287; VI-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
1288; VI-NEXT:    v_mov_b32_e32 v1, s5
1289; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 5
1290; VI-NEXT:    v_cndmask_b32_e32 v1, 5, v1, vcc
1291; VI-NEXT:    v_mov_b32_e32 v4, s9
1292; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 4
1293; VI-NEXT:    v_cndmask_b32_e32 v4, 5, v4, vcc
1294; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v1
1295; VI-NEXT:    v_or_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
1296; VI-NEXT:    s_lshr_b32 s5, s8, 24
1297; VI-NEXT:    v_or_b32_sdwa v1, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
1298; VI-NEXT:    v_mov_b32_e32 v0, s5
1299; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 3
1300; VI-NEXT:    s_lshr_b32 s5, s8, 16
1301; VI-NEXT:    v_cndmask_b32_e32 v0, 5, v0, vcc
1302; VI-NEXT:    v_mov_b32_e32 v4, s5
1303; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 2
1304; VI-NEXT:    v_cndmask_b32_e32 v4, 5, v4, vcc
1305; VI-NEXT:    v_lshlrev_b16_e32 v0, 8, v0
1306; VI-NEXT:    s_lshr_b32 s5, s8, 8
1307; VI-NEXT:    v_or_b32_sdwa v0, v4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
1308; VI-NEXT:    v_mov_b32_e32 v4, s5
1309; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 1
1310; VI-NEXT:    v_cndmask_b32_e32 v4, 5, v4, vcc
1311; VI-NEXT:    v_mov_b32_e32 v5, s8
1312; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 0
1313; VI-NEXT:    v_lshlrev_b16_e32 v4, 8, v4
1314; VI-NEXT:    v_cndmask_b32_e32 v5, 5, v5, vcc
1315; VI-NEXT:    v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
1316; VI-NEXT:    v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
1317; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
1318; VI-NEXT:    s_endpgm
1319  %vecins = insertelement <16 x i8> %a, i8 5, i32 %b
1320  store <16 x i8> %vecins, <16 x i8> addrspace(1)* %out, align 16
1321  ret void
1322}
1323
1324; This test requires handling INSERT_SUBREG in SIFixSGPRCopies.  Check that
1325; the compiler doesn't crash.
1326define amdgpu_kernel void @insert_split_bb(<2 x i32> addrspace(1)* %out, i32 addrspace(1)* %in, i32 %a, i32 %b) {
1327; SI-LABEL: insert_split_bb:
1328; SI:       ; %bb.0: ; %entry
1329; SI-NEXT:    s_load_dword s0, s[4:5], 0x4
1330; SI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
1331; SI-NEXT:    s_waitcnt lgkmcnt(0)
1332; SI-NEXT:    s_cmp_lg_u32 s0, 0
1333; SI-NEXT:    s_cbranch_scc0 BB26_2
1334; SI-NEXT:  ; %bb.1: ; %else
1335; SI-NEXT:    s_load_dword s1, s[6:7], 0x1
1336; SI-NEXT:    s_mov_b64 s[2:3], 0
1337; SI-NEXT:    s_andn2_b64 vcc, exec, s[2:3]
1338; SI-NEXT:    s_waitcnt lgkmcnt(0)
1339; SI-NEXT:    s_mov_b64 vcc, vcc
1340; SI-NEXT:    s_cbranch_vccz BB26_3
1341; SI-NEXT:    s_branch BB26_4
1342; SI-NEXT:  BB26_2:
1343; SI-NEXT:  BB26_3: ; %if
1344; SI-NEXT:    s_load_dword s1, s[6:7], 0x0
1345; SI-NEXT:  BB26_4: ; %endif
1346; SI-NEXT:    s_waitcnt lgkmcnt(0)
1347; SI-NEXT:    v_mov_b32_e32 v0, s0
1348; SI-NEXT:    s_mov_b32 s7, 0x100f000
1349; SI-NEXT:    s_mov_b32 s6, -1
1350; SI-NEXT:    v_mov_b32_e32 v1, s1
1351; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1352; SI-NEXT:    s_endpgm
1353;
1354; VI-LABEL: insert_split_bb:
1355; VI:       ; %bb.0: ; %entry
1356; VI-NEXT:    s_load_dword s0, s[4:5], 0x10
1357; VI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
1358; VI-NEXT:    s_waitcnt lgkmcnt(0)
1359; VI-NEXT:    s_cmp_lg_u32 s0, 0
1360; VI-NEXT:    s_cbranch_scc0 BB26_2
1361; VI-NEXT:  ; %bb.1: ; %else
1362; VI-NEXT:    s_load_dword s1, s[6:7], 0x4
1363; VI-NEXT:    s_cbranch_execz BB26_3
1364; VI-NEXT:    s_branch BB26_4
1365; VI-NEXT:  BB26_2:
1366; VI-NEXT:  BB26_3: ; %if
1367; VI-NEXT:    s_waitcnt lgkmcnt(0)
1368; VI-NEXT:    s_load_dword s1, s[6:7], 0x0
1369; VI-NEXT:  BB26_4: ; %endif
1370; VI-NEXT:    s_waitcnt lgkmcnt(0)
1371; VI-NEXT:    v_mov_b32_e32 v0, s0
1372; VI-NEXT:    s_mov_b32 s7, 0x1100f000
1373; VI-NEXT:    s_mov_b32 s6, -1
1374; VI-NEXT:    v_mov_b32_e32 v1, s1
1375; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1376; VI-NEXT:    s_endpgm
1377entry:
1378  %0 = insertelement <2 x i32> undef, i32 %a, i32 0
1379  %1 = icmp eq i32 %a, 0
1380  br i1 %1, label %if, label %else
1381
1382if:
1383  %2 = load i32, i32 addrspace(1)* %in
1384  %3 = insertelement <2 x i32> %0, i32 %2, i32 1
1385  br label %endif
1386
1387else:
1388  %4 = getelementptr i32, i32 addrspace(1)* %in, i32 1
1389  %5 = load i32, i32 addrspace(1)* %4
1390  %6 = insertelement <2 x i32> %0, i32 %5, i32 1
1391  br label %endif
1392
1393endif:
1394  %7 = phi <2 x i32> [%3, %if], [%6, %else]
1395  store <2 x i32> %7, <2 x i32> addrspace(1)* %out
1396  ret void
1397}
1398
1399define amdgpu_kernel void @dynamic_insertelement_v2f64(<2 x double> addrspace(1)* %out, [8 x i32], <2 x double> %a, [8 x i32], i32 %b) nounwind {
1400; SI-LABEL: dynamic_insertelement_v2f64:
1401; SI:       ; %bb.0:
1402; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
1403; SI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0xc
1404; SI-NEXT:    s_load_dword s4, s[4:5], 0x18
1405; SI-NEXT:    v_mov_b32_e32 v1, 0x40200000
1406; SI-NEXT:    s_mov_b32 s3, 0x100f000
1407; SI-NEXT:    s_mov_b32 s2, -1
1408; SI-NEXT:    s_waitcnt lgkmcnt(0)
1409; SI-NEXT:    v_mov_b32_e32 v0, s11
1410; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s4, 1
1411; SI-NEXT:    v_cndmask_b32_e32 v3, v0, v1, vcc
1412; SI-NEXT:    v_mov_b32_e32 v0, s10
1413; SI-NEXT:    v_cndmask_b32_e64 v2, v0, 0, vcc
1414; SI-NEXT:    v_mov_b32_e32 v0, s9
1415; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s4, 0
1416; SI-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
1417; SI-NEXT:    v_mov_b32_e32 v0, s8
1418; SI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc
1419; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
1420; SI-NEXT:    s_endpgm
1421;
1422; VI-LABEL: dynamic_insertelement_v2f64:
1423; VI:       ; %bb.0:
1424; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
1425; VI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x30
1426; VI-NEXT:    s_load_dword s4, s[4:5], 0x60
1427; VI-NEXT:    v_mov_b32_e32 v1, 0x40200000
1428; VI-NEXT:    s_mov_b32 s3, 0x1100f000
1429; VI-NEXT:    s_mov_b32 s2, -1
1430; VI-NEXT:    s_waitcnt lgkmcnt(0)
1431; VI-NEXT:    v_mov_b32_e32 v0, s11
1432; VI-NEXT:    v_cmp_eq_u32_e64 vcc, s4, 1
1433; VI-NEXT:    v_cndmask_b32_e32 v3, v0, v1, vcc
1434; VI-NEXT:    v_mov_b32_e32 v0, s10
1435; VI-NEXT:    v_cndmask_b32_e64 v2, v0, 0, vcc
1436; VI-NEXT:    v_mov_b32_e32 v0, s9
1437; VI-NEXT:    v_cmp_eq_u32_e64 vcc, s4, 0
1438; VI-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
1439; VI-NEXT:    v_mov_b32_e32 v0, s8
1440; VI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc
1441; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
1442; VI-NEXT:    s_endpgm
1443  %vecins = insertelement <2 x double> %a, double 8.0, i32 %b
1444  store <2 x double> %vecins, <2 x double> addrspace(1)* %out, align 16
1445  ret void
1446}
1447
1448define amdgpu_kernel void @dynamic_insertelement_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %a, i32 %b) nounwind {
1449; SI-LABEL: dynamic_insertelement_v2i64:
1450; SI:       ; %bb.0:
1451; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
1452; SI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x4
1453; SI-NEXT:    s_load_dword s6, s[4:5], 0x8
1454; SI-NEXT:    s_mov_b32 s3, 0x100f000
1455; SI-NEXT:    s_mov_b32 s2, -1
1456; SI-NEXT:    s_waitcnt lgkmcnt(0)
1457; SI-NEXT:    v_mov_b32_e32 v0, s11
1458; SI-NEXT:    v_cmp_eq_u32_e64 s[4:5], s6, 1
1459; SI-NEXT:    v_cndmask_b32_e64 v3, v0, 0, s[4:5]
1460; SI-NEXT:    v_mov_b32_e32 v0, s10
1461; SI-NEXT:    v_cndmask_b32_e64 v2, v0, 5, s[4:5]
1462; SI-NEXT:    v_mov_b32_e32 v0, s9
1463; SI-NEXT:    v_cmp_eq_u32_e64 s[4:5], s6, 0
1464; SI-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[4:5]
1465; SI-NEXT:    v_mov_b32_e32 v0, s8
1466; SI-NEXT:    v_cndmask_b32_e64 v0, v0, 5, s[4:5]
1467; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
1468; SI-NEXT:    s_endpgm
1469;
1470; VI-LABEL: dynamic_insertelement_v2i64:
1471; VI:       ; %bb.0:
1472; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
1473; VI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x10
1474; VI-NEXT:    s_load_dword s6, s[4:5], 0x20
1475; VI-NEXT:    s_mov_b32 s3, 0x1100f000
1476; VI-NEXT:    s_mov_b32 s2, -1
1477; VI-NEXT:    s_waitcnt lgkmcnt(0)
1478; VI-NEXT:    v_mov_b32_e32 v0, s11
1479; VI-NEXT:    v_cmp_eq_u32_e64 s[4:5], s6, 1
1480; VI-NEXT:    v_cndmask_b32_e64 v3, v0, 0, s[4:5]
1481; VI-NEXT:    v_mov_b32_e32 v0, s10
1482; VI-NEXT:    v_cndmask_b32_e64 v2, v0, 5, s[4:5]
1483; VI-NEXT:    v_mov_b32_e32 v0, s9
1484; VI-NEXT:    v_cmp_eq_u32_e64 s[4:5], s6, 0
1485; VI-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[4:5]
1486; VI-NEXT:    v_mov_b32_e32 v0, s8
1487; VI-NEXT:    v_cndmask_b32_e64 v0, v0, 5, s[4:5]
1488; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
1489; VI-NEXT:    s_endpgm
1490  %vecins = insertelement <2 x i64> %a, i64 5, i32 %b
1491  store <2 x i64> %vecins, <2 x i64> addrspace(1)* %out, align 8
1492  ret void
1493}
1494
1495define amdgpu_kernel void @dynamic_insertelement_v3i64(<3 x i64> addrspace(1)* %out, <3 x i64> %a, i32 %b) nounwind {
1496; SI-LABEL: dynamic_insertelement_v3i64:
1497; SI:       ; %bb.0:
1498; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
1499; SI-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x8
1500; SI-NEXT:    s_load_dword s6, s[4:5], 0x10
1501; SI-NEXT:    s_mov_b32 s3, 0x100f000
1502; SI-NEXT:    s_mov_b32 s2, -1
1503; SI-NEXT:    s_waitcnt lgkmcnt(0)
1504; SI-NEXT:    v_mov_b32_e32 v0, s13
1505; SI-NEXT:    v_cmp_eq_u32_e64 s[4:5], s6, 2
1506; SI-NEXT:    v_cndmask_b32_e64 v5, v0, 0, s[4:5]
1507; SI-NEXT:    v_mov_b32_e32 v0, s12
1508; SI-NEXT:    v_cndmask_b32_e64 v4, v0, 5, s[4:5]
1509; SI-NEXT:    v_mov_b32_e32 v0, s11
1510; SI-NEXT:    v_cmp_eq_u32_e64 s[4:5], s6, 1
1511; SI-NEXT:    v_cndmask_b32_e64 v3, v0, 0, s[4:5]
1512; SI-NEXT:    v_mov_b32_e32 v0, s10
1513; SI-NEXT:    v_cndmask_b32_e64 v2, v0, 5, s[4:5]
1514; SI-NEXT:    v_mov_b32_e32 v0, s9
1515; SI-NEXT:    v_cmp_eq_u32_e64 s[4:5], s6, 0
1516; SI-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[4:5]
1517; SI-NEXT:    v_mov_b32_e32 v0, s8
1518; SI-NEXT:    v_cndmask_b32_e64 v0, v0, 5, s[4:5]
1519; SI-NEXT:    buffer_store_dwordx2 v[4:5], off, s[0:3], 0 offset:16
1520; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
1521; SI-NEXT:    s_endpgm
1522;
1523; VI-LABEL: dynamic_insertelement_v3i64:
1524; VI:       ; %bb.0:
1525; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
1526; VI-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x20
1527; VI-NEXT:    s_load_dword s6, s[4:5], 0x40
1528; VI-NEXT:    s_mov_b32 s3, 0x1100f000
1529; VI-NEXT:    s_mov_b32 s2, -1
1530; VI-NEXT:    s_waitcnt lgkmcnt(0)
1531; VI-NEXT:    v_mov_b32_e32 v0, s13
1532; VI-NEXT:    v_cmp_eq_u32_e64 s[4:5], s6, 2
1533; VI-NEXT:    v_cndmask_b32_e64 v5, v0, 0, s[4:5]
1534; VI-NEXT:    v_mov_b32_e32 v0, s12
1535; VI-NEXT:    v_cndmask_b32_e64 v4, v0, 5, s[4:5]
1536; VI-NEXT:    v_mov_b32_e32 v0, s11
1537; VI-NEXT:    v_cmp_eq_u32_e64 s[4:5], s6, 1
1538; VI-NEXT:    v_cndmask_b32_e64 v3, v0, 0, s[4:5]
1539; VI-NEXT:    v_mov_b32_e32 v0, s10
1540; VI-NEXT:    v_cndmask_b32_e64 v2, v0, 5, s[4:5]
1541; VI-NEXT:    v_mov_b32_e32 v0, s9
1542; VI-NEXT:    v_cmp_eq_u32_e64 s[4:5], s6, 0
1543; VI-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[4:5]
1544; VI-NEXT:    v_mov_b32_e32 v0, s8
1545; VI-NEXT:    v_cndmask_b32_e64 v0, v0, 5, s[4:5]
1546; VI-NEXT:    buffer_store_dwordx2 v[4:5], off, s[0:3], 0 offset:16
1547; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
1548; VI-NEXT:    s_endpgm
1549  %vecins = insertelement <3 x i64> %a, i64 5, i32 %b
1550  store <3 x i64> %vecins, <3 x i64> addrspace(1)* %out, align 32
1551  ret void
1552}
1553
1554define amdgpu_kernel void @dynamic_insertelement_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %a, i32 %b) nounwind {
1555; SI-LABEL: dynamic_insertelement_v4f64:
1556; SI:       ; %bb.0:
1557; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
1558; SI-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x8
1559; SI-NEXT:    s_load_dword s4, s[4:5], 0x10
1560; SI-NEXT:    v_mov_b32_e32 v4, 0x40200000
1561; SI-NEXT:    s_mov_b32 s3, 0x100f000
1562; SI-NEXT:    s_mov_b32 s2, -1
1563; SI-NEXT:    s_waitcnt lgkmcnt(0)
1564; SI-NEXT:    v_mov_b32_e32 v0, s11
1565; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s4, 1
1566; SI-NEXT:    v_cndmask_b32_e32 v3, v0, v4, vcc
1567; SI-NEXT:    v_mov_b32_e32 v0, s10
1568; SI-NEXT:    v_cndmask_b32_e64 v2, v0, 0, vcc
1569; SI-NEXT:    v_mov_b32_e32 v0, s9
1570; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s4, 0
1571; SI-NEXT:    v_cndmask_b32_e32 v1, v0, v4, vcc
1572; SI-NEXT:    v_mov_b32_e32 v0, s8
1573; SI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc
1574; SI-NEXT:    v_mov_b32_e32 v5, s15
1575; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s4, 3
1576; SI-NEXT:    v_cndmask_b32_e32 v7, v5, v4, vcc
1577; SI-NEXT:    v_mov_b32_e32 v5, s14
1578; SI-NEXT:    v_cndmask_b32_e64 v6, v5, 0, vcc
1579; SI-NEXT:    v_mov_b32_e32 v5, s13
1580; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s4, 2
1581; SI-NEXT:    v_cndmask_b32_e32 v5, v5, v4, vcc
1582; SI-NEXT:    v_mov_b32_e32 v4, s12
1583; SI-NEXT:    v_cndmask_b32_e64 v4, v4, 0, vcc
1584; SI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
1585; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
1586; SI-NEXT:    s_endpgm
1587;
1588; VI-LABEL: dynamic_insertelement_v4f64:
1589; VI:       ; %bb.0:
1590; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
1591; VI-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x20
1592; VI-NEXT:    s_load_dword s4, s[4:5], 0x40
1593; VI-NEXT:    v_mov_b32_e32 v4, 0x40200000
1594; VI-NEXT:    s_mov_b32 s3, 0x1100f000
1595; VI-NEXT:    s_mov_b32 s2, -1
1596; VI-NEXT:    s_waitcnt lgkmcnt(0)
1597; VI-NEXT:    v_mov_b32_e32 v0, s11
1598; VI-NEXT:    v_cmp_eq_u32_e64 vcc, s4, 1
1599; VI-NEXT:    v_cndmask_b32_e32 v3, v0, v4, vcc
1600; VI-NEXT:    v_mov_b32_e32 v0, s10
1601; VI-NEXT:    v_cndmask_b32_e64 v2, v0, 0, vcc
1602; VI-NEXT:    v_mov_b32_e32 v0, s9
1603; VI-NEXT:    v_cmp_eq_u32_e64 vcc, s4, 0
1604; VI-NEXT:    v_cndmask_b32_e32 v1, v0, v4, vcc
1605; VI-NEXT:    v_mov_b32_e32 v0, s8
1606; VI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc
1607; VI-NEXT:    v_mov_b32_e32 v5, s15
1608; VI-NEXT:    v_cmp_eq_u32_e64 vcc, s4, 3
1609; VI-NEXT:    v_cndmask_b32_e32 v7, v5, v4, vcc
1610; VI-NEXT:    v_mov_b32_e32 v5, s14
1611; VI-NEXT:    v_cndmask_b32_e64 v6, v5, 0, vcc
1612; VI-NEXT:    v_mov_b32_e32 v5, s13
1613; VI-NEXT:    v_cmp_eq_u32_e64 vcc, s4, 2
1614; VI-NEXT:    v_cndmask_b32_e32 v5, v5, v4, vcc
1615; VI-NEXT:    v_mov_b32_e32 v4, s12
1616; VI-NEXT:    v_cndmask_b32_e64 v4, v4, 0, vcc
1617; VI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
1618; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
1619; VI-NEXT:    s_endpgm
1620  %vecins = insertelement <4 x double> %a, double 8.0, i32 %b
1621  store <4 x double> %vecins, <4 x double> addrspace(1)* %out, align 16
1622  ret void
1623}
1624
1625define amdgpu_kernel void @dynamic_insertelement_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %a, i32 %b) #0 {
1626; SI-LABEL: dynamic_insertelement_v8f64:
1627; SI:       ; %bb.0:
1628; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
1629; SI-NEXT:    s_load_dwordx16 s[8:23], s[4:5], 0x10
1630; SI-NEXT:    s_load_dword s4, s[4:5], 0x20
1631; SI-NEXT:    v_mov_b32_e32 v16, 0x40200000
1632; SI-NEXT:    s_mov_b32 s3, 0x100f000
1633; SI-NEXT:    s_mov_b32 s2, -1
1634; SI-NEXT:    s_waitcnt lgkmcnt(0)
1635; SI-NEXT:    v_mov_b32_e32 v0, s8
1636; SI-NEXT:    s_lshl_b32 s4, s4, 1
1637; SI-NEXT:    v_mov_b32_e32 v1, s9
1638; SI-NEXT:    v_mov_b32_e32 v2, s10
1639; SI-NEXT:    v_mov_b32_e32 v3, s11
1640; SI-NEXT:    v_mov_b32_e32 v4, s12
1641; SI-NEXT:    v_mov_b32_e32 v5, s13
1642; SI-NEXT:    v_mov_b32_e32 v6, s14
1643; SI-NEXT:    v_mov_b32_e32 v7, s15
1644; SI-NEXT:    v_mov_b32_e32 v8, s16
1645; SI-NEXT:    v_mov_b32_e32 v9, s17
1646; SI-NEXT:    v_mov_b32_e32 v10, s18
1647; SI-NEXT:    v_mov_b32_e32 v11, s19
1648; SI-NEXT:    v_mov_b32_e32 v12, s20
1649; SI-NEXT:    v_mov_b32_e32 v13, s21
1650; SI-NEXT:    v_mov_b32_e32 v14, s22
1651; SI-NEXT:    v_mov_b32_e32 v15, s23
1652; SI-NEXT:    s_mov_b32 m0, s4
1653; SI-NEXT:    v_movreld_b32_e32 v0, 0
1654; SI-NEXT:    v_movreld_b32_e32 v1, v16
1655; SI-NEXT:    buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48
1656; SI-NEXT:    buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32
1657; SI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
1658; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
1659; SI-NEXT:    s_endpgm
1660;
1661; VI-LABEL: dynamic_insertelement_v8f64:
1662; VI:       ; %bb.0:
1663; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
1664; VI-NEXT:    s_load_dwordx16 s[8:23], s[4:5], 0x40
1665; VI-NEXT:    s_load_dword s4, s[4:5], 0x80
1666; VI-NEXT:    v_mov_b32_e32 v16, 0x40200000
1667; VI-NEXT:    s_mov_b32 s3, 0x1100f000
1668; VI-NEXT:    s_mov_b32 s2, -1
1669; VI-NEXT:    s_waitcnt lgkmcnt(0)
1670; VI-NEXT:    v_mov_b32_e32 v0, s8
1671; VI-NEXT:    s_lshl_b32 s4, s4, 1
1672; VI-NEXT:    v_mov_b32_e32 v1, s9
1673; VI-NEXT:    v_mov_b32_e32 v2, s10
1674; VI-NEXT:    v_mov_b32_e32 v3, s11
1675; VI-NEXT:    v_mov_b32_e32 v4, s12
1676; VI-NEXT:    v_mov_b32_e32 v5, s13
1677; VI-NEXT:    v_mov_b32_e32 v6, s14
1678; VI-NEXT:    v_mov_b32_e32 v7, s15
1679; VI-NEXT:    v_mov_b32_e32 v8, s16
1680; VI-NEXT:    v_mov_b32_e32 v9, s17
1681; VI-NEXT:    v_mov_b32_e32 v10, s18
1682; VI-NEXT:    v_mov_b32_e32 v11, s19
1683; VI-NEXT:    v_mov_b32_e32 v12, s20
1684; VI-NEXT:    v_mov_b32_e32 v13, s21
1685; VI-NEXT:    v_mov_b32_e32 v14, s22
1686; VI-NEXT:    v_mov_b32_e32 v15, s23
1687; VI-NEXT:    s_mov_b32 m0, s4
1688; VI-NEXT:    v_movreld_b32_e32 v0, 0
1689; VI-NEXT:    v_movreld_b32_e32 v1, v16
1690; VI-NEXT:    buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48
1691; VI-NEXT:    buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32
1692; VI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
1693; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
1694; VI-NEXT:    s_endpgm
1695  %vecins = insertelement <8 x double> %a, double 8.0, i32 %b
1696  store <8 x double> %vecins, <8 x double> addrspace(1)* %out, align 16
1697  ret void
1698}
1699
1700declare <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
1701
1702attributes #0 = { nounwind }
1703attributes #1 = { nounwind readnone }
1704