1; RUN: llc -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI,GCN-NO-TONGA %s 2; RUN: llc -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,GCN-TONGA %s 3 4; FIXME: Broken on evergreen 5; FIXME: For some reason the 8 and 16 vectors are being stored as 6; individual elements instead of 128-bit stores. 7 8 9; FIXME: Why is the constant moved into the intermediate register and 10; not just directly into the vector component? 11 12; GCN-LABEL: {{^}}insertelement_v4f32_0: 13; GCN: s_load_dwordx4 14; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 15; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 16; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 17; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 18; GCN-DAG: s_mov_b32 [[CONSTREG:s[0-9]+]], 0x40a00000 19; GCN-DAG: v_mov_b32_e32 v[[LOW_REG:[0-9]+]], [[CONSTREG]] 20; GCN: buffer_store_dwordx4 v{{\[}}[[LOW_REG]]: 21define amdgpu_kernel void @insertelement_v4f32_0(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind { 22 %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 0 23 store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16 24 ret void 25} 26 27; GCN-LABEL: {{^}}insertelement_v4f32_1: 28define amdgpu_kernel void @insertelement_v4f32_1(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind { 29 %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 1 30 store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16 31 ret void 32} 33 34; GCN-LABEL: {{^}}insertelement_v4f32_2: 35define amdgpu_kernel void @insertelement_v4f32_2(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind { 36 %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 2 37 store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16 38 ret void 39} 40 41; GCN-LABEL: {{^}}insertelement_v4f32_3: 42define amdgpu_kernel void @insertelement_v4f32_3(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind { 43 %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 3 44 store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16 45 ret void 46} 47 48; GCN-LABEL: {{^}}insertelement_v4i32_0: 49define amdgpu_kernel void @insertelement_v4i32_0(<4 x i32> addrspace(1)* %out, <4 x i32> %a) nounwind { 50 %vecins = insertelement <4 x i32> %a, i32 999, i32 0 51 store <4 x i32> %vecins, <4 x i32> addrspace(1)* %out, align 16 52 ret void 53} 54 55; GCN-LABEL: {{^}}insertelement_v3f32_1: 56define amdgpu_kernel void @insertelement_v3f32_1(<3 x float> addrspace(1)* %out, <3 x float> %a) nounwind { 57 %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 1 58 store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16 59 ret void 60} 61 62; GCN-LABEL: {{^}}insertelement_v3f32_2: 63define amdgpu_kernel void @insertelement_v3f32_2(<3 x float> addrspace(1)* %out, <3 x float> %a) nounwind { 64 %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 2 65 store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16 66 ret void 67} 68 69; GCN-LABEL: {{^}}insertelement_v3f32_3: 70define amdgpu_kernel void @insertelement_v3f32_3(<3 x float> addrspace(1)* %out, <3 x float> %a) nounwind { 71 %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 3 72 store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16 73 ret void 74} 75 76; GCN-LABEL: {{^}}insertelement_to_sgpr: 77; GCN-NOT: v_readfirstlane 78define amdgpu_ps <4 x float> @insertelement_to_sgpr() nounwind { 79 %tmp = load <4 x i32>, <4 x i32> addrspace(2)* undef 80 %tmp1 = insertelement <4 x i32> %tmp, i32 0, i32 0 81 %tmp2 = call <4 x float> @llvm.amdgcn.image.gather4.lz.v4f32.v2f32.v8i32(<2 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 false, i1 false, i1 false, i1 false, i1 true) 82 ret <4 x float> %tmp2 83} 84 85; GCN-LABEL: {{^}}dynamic_insertelement_v2f32: 86; GCN: v_mov_b32_e32 [[CONST:v[0-9]+]], 0x40a00000 87; GCN: v_movreld_b32_e32 v[[LOW_RESULT_REG:[0-9]+]], [[CONST]] 88; GCN: buffer_store_dwordx2 {{v\[}}[[LOW_RESULT_REG]]: 89define amdgpu_kernel void @dynamic_insertelement_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, i32 %b) nounwind { 90 %vecins = insertelement <2 x float> %a, float 5.000000e+00, i32 %b 91 store <2 x float> %vecins, <2 x float> addrspace(1)* %out, align 8 92 ret void 93} 94 95; GCN-LABEL: {{^}}dynamic_insertelement_v3f32: 96; GCN: v_mov_b32_e32 [[CONST:v[0-9]+]], 0x40a00000 97; GCN: v_movreld_b32_e32 v[[LOW_RESULT_REG:[0-9]+]], [[CONST]] 98; GCN-DAG: buffer_store_dwordx2 {{v\[}}[[LOW_RESULT_REG]]: 99; GCN-DAG: buffer_store_dword v 100define amdgpu_kernel void @dynamic_insertelement_v3f32(<3 x float> addrspace(1)* %out, <3 x float> %a, i32 %b) nounwind { 101 %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 %b 102 store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16 103 ret void 104} 105 106; GCN-LABEL: {{^}}dynamic_insertelement_v4f32: 107; GCN: v_mov_b32_e32 [[CONST:v[0-9]+]], 0x40a00000 108; GCN: v_movreld_b32_e32 v[[LOW_RESULT_REG:[0-9]+]], [[CONST]] 109; GCN: buffer_store_dwordx4 {{v\[}}[[LOW_RESULT_REG]]: 110define amdgpu_kernel void @dynamic_insertelement_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, i32 %b) nounwind { 111 %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 %b 112 store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16 113 ret void 114} 115 116; GCN-LABEL: {{^}}dynamic_insertelement_v8f32: 117; GCN: v_movreld_b32_e32 v{{[0-9]+}}, v{{[0-9]+}} 118; GCN: buffer_store_dwordx4 119; GCN: buffer_store_dwordx4 120define amdgpu_kernel void @dynamic_insertelement_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, i32 %b) nounwind { 121 %vecins = insertelement <8 x float> %a, float 5.000000e+00, i32 %b 122 store <8 x float> %vecins, <8 x float> addrspace(1)* %out, align 32 123 ret void 124} 125 126; GCN-LABEL: {{^}}dynamic_insertelement_v16f32: 127; GCN: v_movreld_b32_e32 v{{[0-9]+}}, v{{[0-9]+}} 128; GCN: buffer_store_dwordx4 129; GCN: buffer_store_dwordx4 130; GCN: buffer_store_dwordx4 131; GCN: buffer_store_dwordx4 132define amdgpu_kernel void @dynamic_insertelement_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %a, i32 %b) nounwind { 133 %vecins = insertelement <16 x float> %a, float 5.000000e+00, i32 %b 134 store <16 x float> %vecins, <16 x float> addrspace(1)* %out, align 64 135 ret void 136} 137 138; GCN-LABEL: {{^}}dynamic_insertelement_v2i32: 139; GCN: v_movreld_b32 140; GCN: buffer_store_dwordx2 141define amdgpu_kernel void @dynamic_insertelement_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, i32 %b) nounwind { 142 %vecins = insertelement <2 x i32> %a, i32 5, i32 %b 143 store <2 x i32> %vecins, <2 x i32> addrspace(1)* %out, align 8 144 ret void 145} 146 147; GCN-LABEL: {{^}}dynamic_insertelement_v3i32: 148; GCN: v_movreld_b32_e32 v[[LOW_RESULT_REG:[0-9]+]], 5 149; GCN-DAG: buffer_store_dwordx2 {{v\[}}[[LOW_RESULT_REG]]: 150; GCN-DAG: buffer_store_dword v 151define amdgpu_kernel void @dynamic_insertelement_v3i32(<3 x i32> addrspace(1)* %out, <3 x i32> %a, i32 %b) nounwind { 152 %vecins = insertelement <3 x i32> %a, i32 5, i32 %b 153 store <3 x i32> %vecins, <3 x i32> addrspace(1)* %out, align 16 154 ret void 155} 156 157; GCN-LABEL: {{^}}dynamic_insertelement_v4i32: 158; GCN: s_load_dword [[SVAL:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, {{0x12|0x48}} 159; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[SVAL]] 160; GCN: v_movreld_b32_e32 v{{[0-9]+}}, [[VVAL]] 161; GCN: buffer_store_dwordx4 162define amdgpu_kernel void @dynamic_insertelement_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, i32 %b, i32 %val) nounwind { 163 %vecins = insertelement <4 x i32> %a, i32 %val, i32 %b 164 store <4 x i32> %vecins, <4 x i32> addrspace(1)* %out, align 16 165 ret void 166} 167 168; GCN-LABEL: {{^}}dynamic_insertelement_v8i32: 169; GCN: v_movreld_b32 170; GCN: buffer_store_dwordx4 171; GCN: buffer_store_dwordx4 172define amdgpu_kernel void @dynamic_insertelement_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> %a, i32 %b) nounwind { 173 %vecins = insertelement <8 x i32> %a, i32 5, i32 %b 174 store <8 x i32> %vecins, <8 x i32> addrspace(1)* %out, align 32 175 ret void 176} 177 178; GCN-LABEL: {{^}}dynamic_insertelement_v16i32: 179; GCN: v_movreld_b32 180; GCN: buffer_store_dwordx4 181; GCN: buffer_store_dwordx4 182; GCN: buffer_store_dwordx4 183; GCN: buffer_store_dwordx4 184define amdgpu_kernel void @dynamic_insertelement_v16i32(<16 x i32> addrspace(1)* %out, <16 x i32> %a, i32 %b) nounwind { 185 %vecins = insertelement <16 x i32> %a, i32 5, i32 %b 186 store <16 x i32> %vecins, <16 x i32> addrspace(1)* %out, align 64 187 ret void 188} 189 190; GCN-LABEL: {{^}}dynamic_insertelement_v2i16: 191define amdgpu_kernel void @dynamic_insertelement_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %a, i32 %b) nounwind { 192 %vecins = insertelement <2 x i16> %a, i16 5, i32 %b 193 store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out, align 8 194 ret void 195} 196 197; GCN-LABEL: {{^}}dynamic_insertelement_v3i16: 198define amdgpu_kernel void @dynamic_insertelement_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %a, i32 %b) nounwind { 199 %vecins = insertelement <3 x i16> %a, i16 5, i32 %b 200 store <3 x i16> %vecins, <3 x i16> addrspace(1)* %out, align 8 201 ret void 202} 203 204; GCN-LABEL: {{^}}dynamic_insertelement_v2i8: 205; VI: s_load_dword [[LOAD:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c 206; VI-NEXT: s_load_dword [[IDX:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30 207; VI-NOT: _load 208; VI: s_lshr_b32 [[ELT1:s[0-9]+]], [[LOAD]], 8 209; VI: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 3 210; VI: v_lshlrev_b16_e64 [[ELT1_SHIFT:v[0-9]+]], 8, [[ELT1]] 211; VI: s_and_b32 [[ELT0:s[0-9]+]], [[LOAD]], 0xff{{$}} 212; VI: v_lshlrev_b16_e64 [[MASK:v[0-9]+]], [[SCALED_IDX]], -1 213 214; VI: v_xor_b32_e32 [[NOT:v[0-9]+]], -1, [[MASK]] 215; VI: v_or_b32_e32 [[BUILD_VECTOR:v[0-9]+]], [[ELT0]], [[ELT1_SHIFT]] 216 217; VI: v_and_b32_e32 [[AND1:v[0-9]+]], [[NOT]], [[BUILD_VECTOR]] 218; VI-DAG: v_and_b32_e32 [[INSERT:v[0-9]+]], 5, [[MASK]] 219; VI: v_or_b32_e32 [[OR:v[0-9]+]], [[INSERT]], [[BUILD_VECTOR]] 220; VI: buffer_store_short [[OR]] 221define amdgpu_kernel void @dynamic_insertelement_v2i8(<2 x i8> addrspace(1)* %out, <2 x i8> %a, i32 %b) nounwind { 222 %vecins = insertelement <2 x i8> %a, i8 5, i32 %b 223 store <2 x i8> %vecins, <2 x i8> addrspace(1)* %out, align 8 224 ret void 225} 226 227; FIXME: post legalize i16 and i32 shifts aren't merged because of 228; isTypeDesirableForOp in SimplifyDemandedBits 229 230; GCN-LABEL: {{^}}dynamic_insertelement_v3i8: 231; VI: s_load_dword [[LOAD:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c 232; VI-NEXT: s_load_dword [[IDX:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30 233; VI-NOT: _load 234 235; VI: s_lshr_b32 [[VEC_HI:s[0-9]+]], [[LOAD]], 8 236; VI: v_lshlrev_b16_e64 [[ELT2:v[0-9]+]], 8, [[VEC_HI]] 237; VI: s_and_b32 [[ELT0:s[0-9]+]], [[LOAD]], 0xff{{$}} 238; VI: v_or_b32_e32 [[BUILD_VEC:v[0-9]+]], [[VEC_HI]], [[ELT2]] 239; VI: s_and_b32 [[ELT2:s[0-9]+]], [[LOAD]], 0xff0000{{$}} 240 241; VI: s_mov_b32 [[MASK16:s[0-9]+]], 0xffff{{$}} 242; VI: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 3 243; VI: s_lshl_b32 [[SHIFTED_MASK:s[0-9]+]], [[MASK16]], [[SCALED_IDX]] 244 245; VI: v_mov_b32_e32 [[V_ELT2:v[0-9]+]], [[ELT2]] 246; VI: v_or_b32_sdwa [[SDWA:v[0-9]+]], [[BUILD_VEC]], [[V_ELT2]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 247; VI: s_not_b32 [[NOT_SHIFT_MASK:s[0-9]+]], [[SHIFTED_MASK]] 248; VI: v_and_b32_e32 [[AND_NOT_MASK:v[0-9]+]], [[NOT_SHIFT_MASK]], [[SDWA]] 249; VI: v_lshrrev_b32_e32 [[HI2:v[0-9]+]], 16, [[AND_NOT_MASK]] 250; VI: v_bfi_b32 [[BFI:v[0-9]+]], [[SCALED_IDX]], 5, [[SDWA]] 251; VI: buffer_store_short [[BFI]] 252; VI: buffer_store_byte [[HI2]] 253define amdgpu_kernel void @dynamic_insertelement_v3i8(<3 x i8> addrspace(1)* %out, <3 x i8> %a, i32 %b) nounwind { 254 %vecins = insertelement <3 x i8> %a, i8 5, i32 %b 255 store <3 x i8> %vecins, <3 x i8> addrspace(1)* %out, align 4 256 ret void 257} 258 259; GCN-LABEL: {{^}}dynamic_insertelement_v4i8: 260; VI: s_load_dword [[VEC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c 261; VI-NEXT: s_load_dword [[IDX:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30 262; VI-NOT: _load 263 264; VI: s_lshr_b32 [[ELT1:s[0-9]+]], [[VEC]], 8 265; VI: v_lshlrev_b16_e64 [[ELT2:v[0-9]+]], 8, [[ELT1]] 266; VI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0xff{{$}} 267 268 269; VI: s_lshr_b32 [[ELT3:s[0-9]+]], [[VEC]], 24 270; VI: s_lshr_b32 [[ELT2:s[0-9]+]], [[VEC]], 16 271; VI: v_lshlrev_b16_e64 v{{[0-9]+}}, 8, [[ELT3]] 272; VI: v_or_b32_e32 273; VI: v_or_b32_sdwa 274; VI-DAG: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 3 275; VI: v_or_b32_sdwa 276; VI: s_lshl_b32 277; VI: v_bfi_b32 278define amdgpu_kernel void @dynamic_insertelement_v4i8(<4 x i8> addrspace(1)* %out, <4 x i8> %a, i32 %b) nounwind { 279 %vecins = insertelement <4 x i8> %a, i8 5, i32 %b 280 store <4 x i8> %vecins, <4 x i8> addrspace(1)* %out, align 4 281 ret void 282} 283 284; GCN-LABEL: {{^}}s_dynamic_insertelement_v8i8: 285; VI-NOT: {{buffer|flat|global}} 286; VI: s_load_dword [[IDX:s[0-9]]] 287; VI-NOT: {{buffer|flat|global}} 288; VI: s_load_dwordx2 [[VEC:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0x0 289; VI-NOT: {{buffer|flat|global}} 290 291; VI-DAG: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 3 292; VI-DAG: s_mov_b32 s[[MASK_HI:[0-9]+]], 0 293; VI-DAG: s_mov_b32 s[[MASK_LO:[0-9]+]], 0xffff 294; VI: s_lshl_b64 s{{\[}}[[MASK_SHIFT_LO:[0-9]+]]:[[MASK_SHIFT_HI:[0-9]+]]{{\]}}, s{{\[}}[[MASK_LO]]:[[MASK_HI]]{{\]}}, [[SCALED_IDX]] 295; VI: s_not_b64 [[NOT_MASK:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[MASK_SHIFT_LO]]:[[MASK_SHIFT_HI]]{{\]}} 296; VI: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], [[NOT_MASK]], [[VEC]] 297; VI: s_and_b32 s[[INS:[0-9]+]], s[[MASK_SHIFT_LO]], 5 298; VI: s_or_b64 s{{\[}}[[RESULT0:[0-9]+]]:[[RESULT1:[0-9]+]]{{\]}}, s{{\[}}[[INS]]:[[MASK_HI]]{{\]}}, [[AND]] 299; VI: v_mov_b32_e32 v[[V_RESULT0:[0-9]+]], s[[RESULT0]] 300; VI: v_mov_b32_e32 v[[V_RESULT1:[0-9]+]], s[[RESULT1]] 301; VI: buffer_store_dwordx2 v{{\[}}[[V_RESULT0]]:[[V_RESULT1]]{{\]}} 302define amdgpu_kernel void @s_dynamic_insertelement_v8i8(<8 x i8> addrspace(1)* %out, <8 x i8> addrspace(4)* %a.ptr, i32 %b) nounwind { 303 %a = load <8 x i8>, <8 x i8> addrspace(4)* %a.ptr, align 4 304 %vecins = insertelement <8 x i8> %a, i8 5, i32 %b 305 store <8 x i8> %vecins, <8 x i8> addrspace(1)* %out, align 8 306 ret void 307} 308 309; GCN-LABEL: {{^}}dynamic_insertelement_v16i8: 310; GCN: s_load_dwordx2 311; GCN: s_load_dword s 312; GCN: s_load_dword s 313; GCN: s_load_dword s 314; GCN: s_load_dword s 315; GCN: s_load_dword s 316; GCN-NOT: _load_ 317 318 319; GCN: buffer_store_byte 320; GCN: buffer_store_byte 321; GCN: buffer_store_byte 322; GCN: buffer_store_byte 323; GCN: buffer_store_byte 324; GCN: buffer_store_byte 325; GCN: buffer_store_byte 326; GCN: buffer_store_byte 327; GCN: buffer_store_byte 328; GCN: buffer_store_byte 329; GCN: buffer_store_byte 330; GCN: buffer_store_byte 331; GCN: buffer_store_byte 332; GCN: buffer_store_byte 333; GCN: buffer_store_byte 334; GCN: buffer_store_byte 335 336; GCN: buffer_store_byte 337; GCN: buffer_store_dwordx4 338define amdgpu_kernel void @dynamic_insertelement_v16i8(<16 x i8> addrspace(1)* %out, <16 x i8> %a, i32 %b) nounwind { 339 %vecins = insertelement <16 x i8> %a, i8 5, i32 %b 340 store <16 x i8> %vecins, <16 x i8> addrspace(1)* %out, align 16 341 ret void 342} 343 344; This test requires handling INSERT_SUBREG in SIFixSGPRCopies. Check that 345; the compiler doesn't crash. 346; GCN-LABEL: {{^}}insert_split_bb: 347define amdgpu_kernel void @insert_split_bb(<2 x i32> addrspace(1)* %out, i32 addrspace(1)* %in, i32 %a, i32 %b) { 348entry: 349 %0 = insertelement <2 x i32> undef, i32 %a, i32 0 350 %1 = icmp eq i32 %a, 0 351 br i1 %1, label %if, label %else 352 353if: 354 %2 = load i32, i32 addrspace(1)* %in 355 %3 = insertelement <2 x i32> %0, i32 %2, i32 1 356 br label %endif 357 358else: 359 %4 = getelementptr i32, i32 addrspace(1)* %in, i32 1 360 %5 = load i32, i32 addrspace(1)* %4 361 %6 = insertelement <2 x i32> %0, i32 %5, i32 1 362 br label %endif 363 364endif: 365 %7 = phi <2 x i32> [%3, %if], [%6, %else] 366 store <2 x i32> %7, <2 x i32> addrspace(1)* %out 367 ret void 368} 369 370; GCN-LABEL: {{^}}dynamic_insertelement_v2f64: 371; GCN-DAG: s_load_dwordx4 s{{\[}}[[A_ELT0:[0-9]+]]:[[A_ELT3:[0-9]+]]{{\]}} 372; GCN-DAG: s_load_dword [[IDX:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, {{0x11|0x44}}{{$}} 373 374; GCN-DAG: s_lshl_b32 [[SCALEDIDX:s[0-9]+]], [[IDX]], 1{{$}} 375 376; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 377; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 378; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 379; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 380; GCN-DAG: v_mov_b32_e32 [[ELT1:v[0-9]+]], 0x40200000 381 382; GCN-DAG: s_mov_b32 m0, [[SCALEDIDX]] 383; GCN: v_movreld_b32_e32 v{{[0-9]+}}, 0 384 385; Increment to next element folded into base register, but FileCheck 386; can't do math expressions 387 388; FIXME: Should be able to manipulate m0 directly instead of s_lshl_b32 + copy to m0 389 390; GCN: v_movreld_b32_e32 v{{[0-9]+}}, [[ELT1]] 391 392; GCN: buffer_store_dwordx4 393; GCN: s_endpgm 394define amdgpu_kernel void @dynamic_insertelement_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %a, i32 %b) nounwind { 395 %vecins = insertelement <2 x double> %a, double 8.0, i32 %b 396 store <2 x double> %vecins, <2 x double> addrspace(1)* %out, align 16 397 ret void 398} 399 400; GCN-LABEL: {{^}}dynamic_insertelement_v2i64: 401 402; GCN-DAG: v_movreld_b32_e32 v{{[0-9]+}}, 5 403; GCN-DAG: v_movreld_b32_e32 v{{[0-9]+}}, 0 404 405; GCN: buffer_store_dwordx4 406; GCN: s_endpgm 407define amdgpu_kernel void @dynamic_insertelement_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %a, i32 %b) nounwind { 408 %vecins = insertelement <2 x i64> %a, i64 5, i32 %b 409 store <2 x i64> %vecins, <2 x i64> addrspace(1)* %out, align 8 410 ret void 411} 412 413; GCN-LABEL: {{^}}dynamic_insertelement_v3i64: 414define amdgpu_kernel void @dynamic_insertelement_v3i64(<3 x i64> addrspace(1)* %out, <3 x i64> %a, i32 %b) nounwind { 415 %vecins = insertelement <3 x i64> %a, i64 5, i32 %b 416 store <3 x i64> %vecins, <3 x i64> addrspace(1)* %out, align 32 417 ret void 418} 419 420; FIXME: Should be able to do without stack access. The used stack 421; space is also 2x what should be required. 422 423; GCN-LABEL: {{^}}dynamic_insertelement_v4f64: 424; GCN: SCRATCH_RSRC_DWORD 425 426; Stack store 427 428; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:32{{$}} 429; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:48{{$}} 430 431; Write element 432; GCN: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen{{$}} 433 434; Stack reload 435; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:32{{$}} 436; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:48{{$}} 437 438; Store result 439; GCN: buffer_store_dwordx4 440; GCN: buffer_store_dwordx4 441; GCN: s_endpgm 442; GCN: ScratchSize: 64 443 444define amdgpu_kernel void @dynamic_insertelement_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %a, i32 %b) nounwind { 445 %vecins = insertelement <4 x double> %a, double 8.0, i32 %b 446 store <4 x double> %vecins, <4 x double> addrspace(1)* %out, align 16 447 ret void 448} 449 450; GCN-LABEL: {{^}}dynamic_insertelement_v8f64: 451; GCN-DAG: SCRATCH_RSRC_DWORD 452 453; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:64{{$}} 454; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:80{{$}} 455; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:96{{$}} 456; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:112{{$}} 457 458; GCN: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen{{$}} 459 460; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:64{{$}} 461; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:80{{$}} 462; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:96{{$}} 463; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:112{{$}} 464 465; GCN: buffer_store_dwordx4 466; GCN: buffer_store_dwordx4 467; GCN: buffer_store_dwordx4 468; GCN: buffer_store_dwordx4 469; GCN: s_endpgm 470; GCN: ScratchSize: 128 471define amdgpu_kernel void @dynamic_insertelement_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %a, i32 %b) #0 { 472 %vecins = insertelement <8 x double> %a, double 8.0, i32 %b 473 store <8 x double> %vecins, <8 x double> addrspace(1)* %out, align 16 474 ret void 475} 476 477declare <4 x float> @llvm.amdgcn.image.gather4.lz.v4f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1 478 479attributes #0 = { nounwind } 480attributes #1 = { nounwind readnone } 481