1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -mattr=-flat-for-global,+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI,GCN-NO-TONGA %s
3; RUN: llc -verify-machineinstrs -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -mattr=-flat-for-global -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,GCN-TONGA %s
4
5; FIXME: Broken on evergreen
6; FIXME: For some reason the 8 and 16 vectors are being stored as
7; individual elements instead of 128-bit stores.
8
9
10; FIXME: Why is the constant moved into the intermediate register and
11; not just directly into the vector component?
12define amdgpu_kernel void @insertelement_v4f32_0(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind {
13; SI-LABEL: insertelement_v4f32_0:
14; SI:       ; %bb.0:
15; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
16; SI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x4
17; SI-NEXT:    s_waitcnt lgkmcnt(0)
18; SI-NEXT:    s_mov_b32 s4, 0x40a00000
19; SI-NEXT:    s_mov_b32 s3, 0x100f000
20; SI-NEXT:    s_mov_b32 s2, -1
21; SI-NEXT:    v_mov_b32_e32 v0, s4
22; SI-NEXT:    v_mov_b32_e32 v1, s5
23; SI-NEXT:    v_mov_b32_e32 v2, s6
24; SI-NEXT:    v_mov_b32_e32 v3, s7
25; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
26; SI-NEXT:    s_endpgm
27;
28; VI-LABEL: insertelement_v4f32_0:
29; VI:       ; %bb.0:
30; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
31; VI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x10
32; VI-NEXT:    s_waitcnt lgkmcnt(0)
33; VI-NEXT:    s_mov_b32 s4, 0x40a00000
34; VI-NEXT:    s_mov_b32 s3, 0x1100f000
35; VI-NEXT:    s_mov_b32 s2, -1
36; VI-NEXT:    v_mov_b32_e32 v0, s4
37; VI-NEXT:    v_mov_b32_e32 v1, s5
38; VI-NEXT:    v_mov_b32_e32 v2, s6
39; VI-NEXT:    v_mov_b32_e32 v3, s7
40; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
41; VI-NEXT:    s_endpgm
42  %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 0
43  store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16
44  ret void
45}
46
47define amdgpu_kernel void @insertelement_v4f32_1(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind {
48; SI-LABEL: insertelement_v4f32_1:
49; SI:       ; %bb.0:
50; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
51; SI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x4
52; SI-NEXT:    s_waitcnt lgkmcnt(0)
53; SI-NEXT:    s_mov_b32 s5, 0x40a00000
54; SI-NEXT:    s_mov_b32 s3, 0x100f000
55; SI-NEXT:    s_mov_b32 s2, -1
56; SI-NEXT:    v_mov_b32_e32 v0, s4
57; SI-NEXT:    v_mov_b32_e32 v1, s5
58; SI-NEXT:    v_mov_b32_e32 v2, s6
59; SI-NEXT:    v_mov_b32_e32 v3, s7
60; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
61; SI-NEXT:    s_endpgm
62;
63; VI-LABEL: insertelement_v4f32_1:
64; VI:       ; %bb.0:
65; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
66; VI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x10
67; VI-NEXT:    s_waitcnt lgkmcnt(0)
68; VI-NEXT:    s_mov_b32 s5, 0x40a00000
69; VI-NEXT:    s_mov_b32 s3, 0x1100f000
70; VI-NEXT:    s_mov_b32 s2, -1
71; VI-NEXT:    v_mov_b32_e32 v0, s4
72; VI-NEXT:    v_mov_b32_e32 v1, s5
73; VI-NEXT:    v_mov_b32_e32 v2, s6
74; VI-NEXT:    v_mov_b32_e32 v3, s7
75; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
76; VI-NEXT:    s_endpgm
77  %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 1
78  store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16
79  ret void
80}
81
82define amdgpu_kernel void @insertelement_v4f32_2(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind {
83; SI-LABEL: insertelement_v4f32_2:
84; SI:       ; %bb.0:
85; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
86; SI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x4
87; SI-NEXT:    s_waitcnt lgkmcnt(0)
88; SI-NEXT:    s_mov_b32 s6, 0x40a00000
89; SI-NEXT:    s_mov_b32 s3, 0x100f000
90; SI-NEXT:    s_mov_b32 s2, -1
91; SI-NEXT:    v_mov_b32_e32 v0, s4
92; SI-NEXT:    v_mov_b32_e32 v1, s5
93; SI-NEXT:    v_mov_b32_e32 v2, s6
94; SI-NEXT:    v_mov_b32_e32 v3, s7
95; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
96; SI-NEXT:    s_endpgm
97;
98; VI-LABEL: insertelement_v4f32_2:
99; VI:       ; %bb.0:
100; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
101; VI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x10
102; VI-NEXT:    s_waitcnt lgkmcnt(0)
103; VI-NEXT:    s_mov_b32 s6, 0x40a00000
104; VI-NEXT:    s_mov_b32 s3, 0x1100f000
105; VI-NEXT:    s_mov_b32 s2, -1
106; VI-NEXT:    v_mov_b32_e32 v0, s4
107; VI-NEXT:    v_mov_b32_e32 v1, s5
108; VI-NEXT:    v_mov_b32_e32 v2, s6
109; VI-NEXT:    v_mov_b32_e32 v3, s7
110; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
111; VI-NEXT:    s_endpgm
112  %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 2
113  store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16
114  ret void
115}
116
117define amdgpu_kernel void @insertelement_v4f32_3(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind {
118; SI-LABEL: insertelement_v4f32_3:
119; SI:       ; %bb.0:
120; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
121; SI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x4
122; SI-NEXT:    s_waitcnt lgkmcnt(0)
123; SI-NEXT:    s_mov_b32 s7, 0x40a00000
124; SI-NEXT:    s_mov_b32 s3, 0x100f000
125; SI-NEXT:    s_mov_b32 s2, -1
126; SI-NEXT:    v_mov_b32_e32 v0, s4
127; SI-NEXT:    v_mov_b32_e32 v1, s5
128; SI-NEXT:    v_mov_b32_e32 v2, s6
129; SI-NEXT:    v_mov_b32_e32 v3, s7
130; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
131; SI-NEXT:    s_endpgm
132;
133; VI-LABEL: insertelement_v4f32_3:
134; VI:       ; %bb.0:
135; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
136; VI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x10
137; VI-NEXT:    s_waitcnt lgkmcnt(0)
138; VI-NEXT:    s_mov_b32 s7, 0x40a00000
139; VI-NEXT:    s_mov_b32 s3, 0x1100f000
140; VI-NEXT:    s_mov_b32 s2, -1
141; VI-NEXT:    v_mov_b32_e32 v0, s4
142; VI-NEXT:    v_mov_b32_e32 v1, s5
143; VI-NEXT:    v_mov_b32_e32 v2, s6
144; VI-NEXT:    v_mov_b32_e32 v3, s7
145; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
146; VI-NEXT:    s_endpgm
147  %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 3
148  store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16
149  ret void
150}
151
152define amdgpu_kernel void @insertelement_v4i32_0(<4 x i32> addrspace(1)* %out, <4 x i32> %a) nounwind {
153; SI-LABEL: insertelement_v4i32_0:
154; SI:       ; %bb.0:
155; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
156; SI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x4
157; SI-NEXT:    s_waitcnt lgkmcnt(0)
158; SI-NEXT:    s_movk_i32 s4, 0x3e7
159; SI-NEXT:    s_mov_b32 s3, 0x100f000
160; SI-NEXT:    s_mov_b32 s2, -1
161; SI-NEXT:    v_mov_b32_e32 v0, s4
162; SI-NEXT:    v_mov_b32_e32 v1, s5
163; SI-NEXT:    v_mov_b32_e32 v2, s6
164; SI-NEXT:    v_mov_b32_e32 v3, s7
165; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
166; SI-NEXT:    s_endpgm
167;
168; VI-LABEL: insertelement_v4i32_0:
169; VI:       ; %bb.0:
170; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
171; VI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x10
172; VI-NEXT:    s_waitcnt lgkmcnt(0)
173; VI-NEXT:    s_movk_i32 s4, 0x3e7
174; VI-NEXT:    s_mov_b32 s3, 0x1100f000
175; VI-NEXT:    s_mov_b32 s2, -1
176; VI-NEXT:    v_mov_b32_e32 v0, s4
177; VI-NEXT:    v_mov_b32_e32 v1, s5
178; VI-NEXT:    v_mov_b32_e32 v2, s6
179; VI-NEXT:    v_mov_b32_e32 v3, s7
180; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
181; VI-NEXT:    s_endpgm
182  %vecins = insertelement <4 x i32> %a, i32 999, i32 0
183  store <4 x i32> %vecins, <4 x i32> addrspace(1)* %out, align 16
184  ret void
185}
186
187define amdgpu_kernel void @insertelement_v3f32_1(<3 x float> addrspace(1)* %out, <3 x float> %a) nounwind {
188; SI-LABEL: insertelement_v3f32_1:
189; SI:       ; %bb.0:
190; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
191; SI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x4
192; SI-NEXT:    s_mov_b32 s3, 0x100f000
193; SI-NEXT:    s_mov_b32 s2, -1
194; SI-NEXT:    v_mov_b32_e32 v1, 0x40a00000
195; SI-NEXT:    s_waitcnt lgkmcnt(0)
196; SI-NEXT:    v_mov_b32_e32 v0, s4
197; SI-NEXT:    v_mov_b32_e32 v2, s6
198; SI-NEXT:    buffer_store_dwordx3 v[0:2], off, s[0:3], 0
199; SI-NEXT:    s_endpgm
200;
201; VI-LABEL: insertelement_v3f32_1:
202; VI:       ; %bb.0:
203; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
204; VI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x10
205; VI-NEXT:    s_mov_b32 s3, 0x1100f000
206; VI-NEXT:    s_mov_b32 s2, -1
207; VI-NEXT:    v_mov_b32_e32 v1, 0x40a00000
208; VI-NEXT:    s_waitcnt lgkmcnt(0)
209; VI-NEXT:    v_mov_b32_e32 v0, s4
210; VI-NEXT:    v_mov_b32_e32 v2, s6
211; VI-NEXT:    buffer_store_dwordx3 v[0:2], off, s[0:3], 0
212; VI-NEXT:    s_endpgm
213  %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 1
214  store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16
215  ret void
216}
217
218define amdgpu_kernel void @insertelement_v3f32_2(<3 x float> addrspace(1)* %out, <3 x float> %a) nounwind {
219; SI-LABEL: insertelement_v3f32_2:
220; SI:       ; %bb.0:
221; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
222; SI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x4
223; SI-NEXT:    s_mov_b32 s3, 0x100f000
224; SI-NEXT:    s_mov_b32 s2, -1
225; SI-NEXT:    v_mov_b32_e32 v2, 0x40a00000
226; SI-NEXT:    s_waitcnt lgkmcnt(0)
227; SI-NEXT:    v_mov_b32_e32 v0, s4
228; SI-NEXT:    v_mov_b32_e32 v1, s5
229; SI-NEXT:    buffer_store_dwordx3 v[0:2], off, s[0:3], 0
230; SI-NEXT:    s_endpgm
231;
232; VI-LABEL: insertelement_v3f32_2:
233; VI:       ; %bb.0:
234; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
235; VI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x10
236; VI-NEXT:    s_mov_b32 s3, 0x1100f000
237; VI-NEXT:    s_mov_b32 s2, -1
238; VI-NEXT:    v_mov_b32_e32 v2, 0x40a00000
239; VI-NEXT:    s_waitcnt lgkmcnt(0)
240; VI-NEXT:    v_mov_b32_e32 v0, s4
241; VI-NEXT:    v_mov_b32_e32 v1, s5
242; VI-NEXT:    buffer_store_dwordx3 v[0:2], off, s[0:3], 0
243; VI-NEXT:    s_endpgm
244  %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 2
245  store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16
246  ret void
247}
248
249define amdgpu_kernel void @insertelement_v3f32_3(<3 x float> addrspace(1)* %out, <3 x float> %a) nounwind {
250; GCN-LABEL: insertelement_v3f32_3:
251; GCN:       ; %bb.0:
252; GCN-NEXT:    s_endpgm
253  %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 3
254  store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16
255  ret void
256}
257
258define <4 x float> @insertelement_to_sgpr() nounwind {
259; GCN-LABEL: insertelement_to_sgpr:
260; GCN:       ; %bb.0:
261; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
262; GCN-NEXT:    s_load_dwordx4 s[12:15], s[4:5], 0x0
263; GCN-NEXT:    s_waitcnt lgkmcnt(0)
264; GCN-NEXT:    s_mov_b32 s12, 0
265; GCN-NEXT:    s_mov_b32 s4, s12
266; GCN-NEXT:    s_mov_b32 s5, s12
267; GCN-NEXT:    s_mov_b32 s6, s12
268; GCN-NEXT:    s_mov_b32 s7, s12
269; GCN-NEXT:    s_mov_b32 s8, s12
270; GCN-NEXT:    s_mov_b32 s9, s12
271; GCN-NEXT:    s_mov_b32 s10, s12
272; GCN-NEXT:    s_mov_b32 s11, s12
273; GCN-NEXT:    image_gather4_lz v[0:3], v[0:1], s[4:11], s[12:15] dmask:0x1
274; GCN-NEXT:    s_waitcnt vmcnt(0)
275; GCN-NEXT:    s_setpc_b64 s[30:31]
276  %tmp = load <4 x i32>, <4 x i32> addrspace(4)* undef
277  %tmp1 = insertelement <4 x i32> %tmp, i32 0, i32 0
278  %tmp2 = call <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f32(i32 1, float undef, float undef, <8 x i32> undef, <4 x i32> %tmp1, i1 0, i32 0, i32 0)
279  ret <4 x float> %tmp2
280}
281
282define amdgpu_kernel void @dynamic_insertelement_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, i32 %b) nounwind {
283; SI-LABEL: dynamic_insertelement_v2f32:
284; SI:       ; %bb.0:
285; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
286; SI-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x2
287; SI-NEXT:    s_load_dword s4, s[4:5], 0x4
288; SI-NEXT:    v_mov_b32_e32 v0, 0x40a00000
289; SI-NEXT:    s_mov_b32 s3, 0x100f000
290; SI-NEXT:    s_mov_b32 s2, -1
291; SI-NEXT:    s_waitcnt lgkmcnt(0)
292; SI-NEXT:    v_mov_b32_e32 v1, s7
293; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 1
294; SI-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
295; SI-NEXT:    v_mov_b32_e32 v2, s6
296; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 0
297; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
298; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
299; SI-NEXT:    s_endpgm
300;
301; VI-LABEL: dynamic_insertelement_v2f32:
302; VI:       ; %bb.0:
303; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
304; VI-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x8
305; VI-NEXT:    s_load_dword s4, s[4:5], 0x10
306; VI-NEXT:    v_mov_b32_e32 v0, 0x40a00000
307; VI-NEXT:    s_mov_b32 s3, 0x1100f000
308; VI-NEXT:    s_mov_b32 s2, -1
309; VI-NEXT:    s_waitcnt lgkmcnt(0)
310; VI-NEXT:    v_mov_b32_e32 v1, s7
311; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 1
312; VI-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
313; VI-NEXT:    v_mov_b32_e32 v2, s6
314; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 0
315; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
316; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
317; VI-NEXT:    s_endpgm
318  %vecins = insertelement <2 x float> %a, float 5.000000e+00, i32 %b
319  store <2 x float> %vecins, <2 x float> addrspace(1)* %out, align 8
320  ret void
321}
322
323define amdgpu_kernel void @dynamic_insertelement_v3f32(<3 x float> addrspace(1)* %out, <3 x float> %a, i32 %b) nounwind {
324; SI-LABEL: dynamic_insertelement_v3f32:
325; SI:       ; %bb.0:
326; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
327; SI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x4
328; SI-NEXT:    s_load_dword s4, s[4:5], 0x8
329; SI-NEXT:    v_mov_b32_e32 v0, 0x40a00000
330; SI-NEXT:    s_mov_b32 s3, 0x100f000
331; SI-NEXT:    s_mov_b32 s2, -1
332; SI-NEXT:    s_waitcnt lgkmcnt(0)
333; SI-NEXT:    v_mov_b32_e32 v1, s10
334; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 2
335; SI-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
336; SI-NEXT:    v_mov_b32_e32 v1, s9
337; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 1
338; SI-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
339; SI-NEXT:    v_mov_b32_e32 v3, s8
340; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 0
341; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
342; SI-NEXT:    buffer_store_dwordx3 v[0:2], off, s[0:3], 0
343; SI-NEXT:    s_endpgm
344;
345; VI-LABEL: dynamic_insertelement_v3f32:
346; VI:       ; %bb.0:
347; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
348; VI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x10
349; VI-NEXT:    s_load_dword s4, s[4:5], 0x20
350; VI-NEXT:    v_mov_b32_e32 v0, 0x40a00000
351; VI-NEXT:    s_mov_b32 s3, 0x1100f000
352; VI-NEXT:    s_mov_b32 s2, -1
353; VI-NEXT:    s_waitcnt lgkmcnt(0)
354; VI-NEXT:    v_mov_b32_e32 v1, s10
355; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 2
356; VI-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
357; VI-NEXT:    v_mov_b32_e32 v1, s9
358; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 1
359; VI-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
360; VI-NEXT:    v_mov_b32_e32 v3, s8
361; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 0
362; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
363; VI-NEXT:    buffer_store_dwordx3 v[0:2], off, s[0:3], 0
364; VI-NEXT:    s_endpgm
365  %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 %b
366  store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16
367  ret void
368}
369
370define amdgpu_kernel void @dynamic_insertelement_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, i32 %b) nounwind {
371; SI-LABEL: dynamic_insertelement_v4f32:
372; SI:       ; %bb.0:
373; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
374; SI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x4
375; SI-NEXT:    s_load_dword s4, s[4:5], 0x8
376; SI-NEXT:    v_mov_b32_e32 v0, 0x40a00000
377; SI-NEXT:    s_mov_b32 s3, 0x100f000
378; SI-NEXT:    s_mov_b32 s2, -1
379; SI-NEXT:    s_waitcnt lgkmcnt(0)
380; SI-NEXT:    v_mov_b32_e32 v1, s11
381; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 3
382; SI-NEXT:    v_cndmask_b32_e32 v3, v0, v1, vcc
383; SI-NEXT:    v_mov_b32_e32 v1, s10
384; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 2
385; SI-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
386; SI-NEXT:    v_mov_b32_e32 v1, s9
387; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 1
388; SI-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
389; SI-NEXT:    v_mov_b32_e32 v4, s8
390; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 0
391; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
392; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
393; SI-NEXT:    s_endpgm
394;
395; VI-LABEL: dynamic_insertelement_v4f32:
396; VI:       ; %bb.0:
397; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
398; VI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x10
399; VI-NEXT:    s_load_dword s4, s[4:5], 0x20
400; VI-NEXT:    v_mov_b32_e32 v0, 0x40a00000
401; VI-NEXT:    s_mov_b32 s3, 0x1100f000
402; VI-NEXT:    s_mov_b32 s2, -1
403; VI-NEXT:    s_waitcnt lgkmcnt(0)
404; VI-NEXT:    v_mov_b32_e32 v1, s11
405; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 3
406; VI-NEXT:    v_cndmask_b32_e32 v3, v0, v1, vcc
407; VI-NEXT:    v_mov_b32_e32 v1, s10
408; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 2
409; VI-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
410; VI-NEXT:    v_mov_b32_e32 v1, s9
411; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 1
412; VI-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
413; VI-NEXT:    v_mov_b32_e32 v4, s8
414; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 0
415; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
416; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
417; VI-NEXT:    s_endpgm
418  %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 %b
419  store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16
420  ret void
421}
422
423define amdgpu_kernel void @dynamic_insertelement_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, i32 %b) nounwind {
424; SI-LABEL: dynamic_insertelement_v8f32:
425; SI:       ; %bb.0:
426; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
427; SI-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x8
428; SI-NEXT:    s_load_dword s4, s[4:5], 0x10
429; SI-NEXT:    v_mov_b32_e32 v4, 0x40a00000
430; SI-NEXT:    s_mov_b32 s3, 0x100f000
431; SI-NEXT:    s_mov_b32 s2, -1
432; SI-NEXT:    s_waitcnt lgkmcnt(0)
433; SI-NEXT:    v_mov_b32_e32 v0, s11
434; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 3
435; SI-NEXT:    v_cndmask_b32_e32 v3, v4, v0, vcc
436; SI-NEXT:    v_mov_b32_e32 v0, s10
437; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 2
438; SI-NEXT:    v_cndmask_b32_e32 v2, v4, v0, vcc
439; SI-NEXT:    v_mov_b32_e32 v0, s9
440; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 1
441; SI-NEXT:    v_cndmask_b32_e32 v1, v4, v0, vcc
442; SI-NEXT:    v_mov_b32_e32 v0, s8
443; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 0
444; SI-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
445; SI-NEXT:    v_mov_b32_e32 v5, s15
446; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 7
447; SI-NEXT:    v_cndmask_b32_e32 v7, v4, v5, vcc
448; SI-NEXT:    v_mov_b32_e32 v5, s14
449; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 6
450; SI-NEXT:    v_cndmask_b32_e32 v6, v4, v5, vcc
451; SI-NEXT:    v_mov_b32_e32 v5, s13
452; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 5
453; SI-NEXT:    v_cndmask_b32_e32 v5, v4, v5, vcc
454; SI-NEXT:    v_mov_b32_e32 v8, s12
455; SI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 4
456; SI-NEXT:    v_cndmask_b32_e32 v4, v4, v8, vcc
457; SI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
458; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
459; SI-NEXT:    s_endpgm
460;
461; VI-LABEL: dynamic_insertelement_v8f32:
462; VI:       ; %bb.0:
463; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
464; VI-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x20
465; VI-NEXT:    s_load_dword s4, s[4:5], 0x40
466; VI-NEXT:    v_mov_b32_e32 v4, 0x40a00000
467; VI-NEXT:    s_mov_b32 s3, 0x1100f000
468; VI-NEXT:    s_mov_b32 s2, -1
469; VI-NEXT:    s_waitcnt lgkmcnt(0)
470; VI-NEXT:    v_mov_b32_e32 v0, s11
471; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 3
472; VI-NEXT:    v_cndmask_b32_e32 v3, v4, v0, vcc
473; VI-NEXT:    v_mov_b32_e32 v0, s10
474; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 2
475; VI-NEXT:    v_cndmask_b32_e32 v2, v4, v0, vcc
476; VI-NEXT:    v_mov_b32_e32 v0, s9
477; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 1
478; VI-NEXT:    v_cndmask_b32_e32 v1, v4, v0, vcc
479; VI-NEXT:    v_mov_b32_e32 v0, s8
480; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 0
481; VI-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
482; VI-NEXT:    v_mov_b32_e32 v5, s15
483; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 7
484; VI-NEXT:    v_cndmask_b32_e32 v7, v4, v5, vcc
485; VI-NEXT:    v_mov_b32_e32 v5, s14
486; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 6
487; VI-NEXT:    v_cndmask_b32_e32 v6, v4, v5, vcc
488; VI-NEXT:    v_mov_b32_e32 v5, s13
489; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 5
490; VI-NEXT:    v_cndmask_b32_e32 v5, v4, v5, vcc
491; VI-NEXT:    v_mov_b32_e32 v8, s12
492; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 4
493; VI-NEXT:    v_cndmask_b32_e32 v4, v4, v8, vcc
494; VI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
495; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
496; VI-NEXT:    s_endpgm
497  %vecins = insertelement <8 x float> %a, float 5.000000e+00, i32 %b
498  store <8 x float> %vecins, <8 x float> addrspace(1)* %out, align 32
499  ret void
500}
501
502define amdgpu_kernel void @dynamic_insertelement_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %a, i32 %b) nounwind {
503; SI-LABEL: dynamic_insertelement_v16f32:
504; SI:       ; %bb.0:
505; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
506; SI-NEXT:    s_load_dwordx16 s[8:23], s[4:5], 0x10
507; SI-NEXT:    s_load_dword s4, s[4:5], 0x20
508; SI-NEXT:    v_mov_b32_e32 v16, 0x40a00000
509; SI-NEXT:    s_mov_b32 s3, 0x100f000
510; SI-NEXT:    s_mov_b32 s2, -1
511; SI-NEXT:    s_waitcnt lgkmcnt(0)
512; SI-NEXT:    v_mov_b32_e32 v0, s8
513; SI-NEXT:    v_mov_b32_e32 v1, s9
514; SI-NEXT:    v_mov_b32_e32 v2, s10
515; SI-NEXT:    v_mov_b32_e32 v3, s11
516; SI-NEXT:    v_mov_b32_e32 v4, s12
517; SI-NEXT:    v_mov_b32_e32 v5, s13
518; SI-NEXT:    v_mov_b32_e32 v6, s14
519; SI-NEXT:    v_mov_b32_e32 v7, s15
520; SI-NEXT:    v_mov_b32_e32 v8, s16
521; SI-NEXT:    v_mov_b32_e32 v9, s17
522; SI-NEXT:    v_mov_b32_e32 v10, s18
523; SI-NEXT:    v_mov_b32_e32 v11, s19
524; SI-NEXT:    v_mov_b32_e32 v12, s20
525; SI-NEXT:    v_mov_b32_e32 v13, s21
526; SI-NEXT:    v_mov_b32_e32 v14, s22
527; SI-NEXT:    v_mov_b32_e32 v15, s23
528; SI-NEXT:    s_mov_b32 m0, s4
529; SI-NEXT:    v_movreld_b32_e32 v0, v16
530; SI-NEXT:    buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48
531; SI-NEXT:    buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32
532; SI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
533; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
534; SI-NEXT:    s_endpgm
535;
536; VI-LABEL: dynamic_insertelement_v16f32:
537; VI:       ; %bb.0:
538; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
539; VI-NEXT:    s_load_dwordx16 s[8:23], s[4:5], 0x40
540; VI-NEXT:    s_load_dword s4, s[4:5], 0x80
541; VI-NEXT:    v_mov_b32_e32 v16, 0x40a00000
542; VI-NEXT:    s_mov_b32 s3, 0x1100f000
543; VI-NEXT:    s_mov_b32 s2, -1
544; VI-NEXT:    s_waitcnt lgkmcnt(0)
545; VI-NEXT:    v_mov_b32_e32 v0, s8
546; VI-NEXT:    v_mov_b32_e32 v1, s9
547; VI-NEXT:    v_mov_b32_e32 v2, s10
548; VI-NEXT:    v_mov_b32_e32 v3, s11
549; VI-NEXT:    v_mov_b32_e32 v4, s12
550; VI-NEXT:    v_mov_b32_e32 v5, s13
551; VI-NEXT:    v_mov_b32_e32 v6, s14
552; VI-NEXT:    v_mov_b32_e32 v7, s15
553; VI-NEXT:    v_mov_b32_e32 v8, s16
554; VI-NEXT:    v_mov_b32_e32 v9, s17
555; VI-NEXT:    v_mov_b32_e32 v10, s18
556; VI-NEXT:    v_mov_b32_e32 v11, s19
557; VI-NEXT:    v_mov_b32_e32 v12, s20
558; VI-NEXT:    v_mov_b32_e32 v13, s21
559; VI-NEXT:    v_mov_b32_e32 v14, s22
560; VI-NEXT:    v_mov_b32_e32 v15, s23
561; VI-NEXT:    s_mov_b32 m0, s4
562; VI-NEXT:    v_movreld_b32_e32 v0, v16
563; VI-NEXT:    buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48
564; VI-NEXT:    buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32
565; VI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
566; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
567; VI-NEXT:    s_endpgm
568  %vecins = insertelement <16 x float> %a, float 5.000000e+00, i32 %b
569  store <16 x float> %vecins, <16 x float> addrspace(1)* %out, align 64
570  ret void
571}
572
573define amdgpu_kernel void @dynamic_insertelement_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, i32 %b) nounwind {
574; SI-LABEL: dynamic_insertelement_v2i32:
575; SI:       ; %bb.0:
576; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
577; SI-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x2
578; SI-NEXT:    s_load_dword s4, s[4:5], 0x4
579; SI-NEXT:    s_mov_b32 s3, 0x100f000
580; SI-NEXT:    s_mov_b32 s2, -1
581; SI-NEXT:    s_waitcnt lgkmcnt(0)
582; SI-NEXT:    s_cmp_lg_u32 s4, 1
583; SI-NEXT:    s_cselect_b32 s5, s7, 5
584; SI-NEXT:    s_cmp_lg_u32 s4, 0
585; SI-NEXT:    s_cselect_b32 s4, s6, 5
586; SI-NEXT:    v_mov_b32_e32 v0, s4
587; SI-NEXT:    v_mov_b32_e32 v1, s5
588; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
589; SI-NEXT:    s_endpgm
590;
591; VI-LABEL: dynamic_insertelement_v2i32:
592; VI:       ; %bb.0:
593; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
594; VI-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x8
595; VI-NEXT:    s_load_dword s4, s[4:5], 0x10
596; VI-NEXT:    s_mov_b32 s3, 0x1100f000
597; VI-NEXT:    s_mov_b32 s2, -1
598; VI-NEXT:    s_waitcnt lgkmcnt(0)
599; VI-NEXT:    s_cmp_lg_u32 s4, 1
600; VI-NEXT:    s_cselect_b32 s5, s7, 5
601; VI-NEXT:    s_cmp_lg_u32 s4, 0
602; VI-NEXT:    s_cselect_b32 s4, s6, 5
603; VI-NEXT:    v_mov_b32_e32 v0, s4
604; VI-NEXT:    v_mov_b32_e32 v1, s5
605; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
606; VI-NEXT:    s_endpgm
607  %vecins = insertelement <2 x i32> %a, i32 5, i32 %b
608  store <2 x i32> %vecins, <2 x i32> addrspace(1)* %out, align 8
609  ret void
610}
611
612define amdgpu_kernel void @dynamic_insertelement_v3i32(<3 x i32> addrspace(1)* %out, <3 x i32> %a, i32 %b) nounwind {
613; SI-LABEL: dynamic_insertelement_v3i32:
614; SI:       ; %bb.0:
615; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
616; SI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x4
617; SI-NEXT:    s_load_dword s4, s[4:5], 0x8
618; SI-NEXT:    s_mov_b32 s3, 0x100f000
619; SI-NEXT:    s_mov_b32 s2, -1
620; SI-NEXT:    s_waitcnt lgkmcnt(0)
621; SI-NEXT:    s_cmp_lg_u32 s4, 2
622; SI-NEXT:    s_cselect_b32 s5, s10, 5
623; SI-NEXT:    s_cmp_lg_u32 s4, 1
624; SI-NEXT:    s_cselect_b32 s6, s9, 5
625; SI-NEXT:    s_cmp_lg_u32 s4, 0
626; SI-NEXT:    s_cselect_b32 s4, s8, 5
627; SI-NEXT:    v_mov_b32_e32 v0, s4
628; SI-NEXT:    v_mov_b32_e32 v1, s6
629; SI-NEXT:    v_mov_b32_e32 v2, s5
630; SI-NEXT:    buffer_store_dwordx3 v[0:2], off, s[0:3], 0
631; SI-NEXT:    s_endpgm
632;
633; VI-LABEL: dynamic_insertelement_v3i32:
634; VI:       ; %bb.0:
635; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
636; VI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x10
637; VI-NEXT:    s_load_dword s4, s[4:5], 0x20
638; VI-NEXT:    s_mov_b32 s3, 0x1100f000
639; VI-NEXT:    s_mov_b32 s2, -1
640; VI-NEXT:    s_waitcnt lgkmcnt(0)
641; VI-NEXT:    s_cmp_lg_u32 s4, 2
642; VI-NEXT:    s_cselect_b32 s5, s10, 5
643; VI-NEXT:    s_cmp_lg_u32 s4, 1
644; VI-NEXT:    s_cselect_b32 s6, s9, 5
645; VI-NEXT:    s_cmp_lg_u32 s4, 0
646; VI-NEXT:    s_cselect_b32 s4, s8, 5
647; VI-NEXT:    v_mov_b32_e32 v0, s4
648; VI-NEXT:    v_mov_b32_e32 v1, s6
649; VI-NEXT:    v_mov_b32_e32 v2, s5
650; VI-NEXT:    buffer_store_dwordx3 v[0:2], off, s[0:3], 0
651; VI-NEXT:    s_endpgm
652  %vecins = insertelement <3 x i32> %a, i32 5, i32 %b
653  store <3 x i32> %vecins, <3 x i32> addrspace(1)* %out, align 16
654  ret void
655}
656
657define amdgpu_kernel void @dynamic_insertelement_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, i32 %b, [8 x i32], i32 %val) nounwind {
658; SI-LABEL: dynamic_insertelement_v4i32:
659; SI:       ; %bb.0:
660; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
661; SI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x4
662; SI-NEXT:    s_load_dword s6, s[4:5], 0x8
663; SI-NEXT:    s_load_dword s4, s[4:5], 0x11
664; SI-NEXT:    s_mov_b32 s3, 0x100f000
665; SI-NEXT:    s_mov_b32 s2, -1
666; SI-NEXT:    s_waitcnt lgkmcnt(0)
667; SI-NEXT:    s_cmp_eq_u32 s6, 3
668; SI-NEXT:    s_cselect_b32 s5, s4, s11
669; SI-NEXT:    s_cmp_eq_u32 s6, 2
670; SI-NEXT:    s_cselect_b32 s7, s4, s10
671; SI-NEXT:    s_cmp_eq_u32 s6, 1
672; SI-NEXT:    s_cselect_b32 s9, s4, s9
673; SI-NEXT:    s_cmp_eq_u32 s6, 0
674; SI-NEXT:    s_cselect_b32 s4, s4, s8
675; SI-NEXT:    v_mov_b32_e32 v0, s4
676; SI-NEXT:    v_mov_b32_e32 v1, s9
677; SI-NEXT:    v_mov_b32_e32 v2, s7
678; SI-NEXT:    v_mov_b32_e32 v3, s5
679; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
680; SI-NEXT:    s_endpgm
681;
682; VI-LABEL: dynamic_insertelement_v4i32:
683; VI:       ; %bb.0:
684; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
685; VI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x10
686; VI-NEXT:    s_load_dword s6, s[4:5], 0x20
687; VI-NEXT:    s_load_dword s4, s[4:5], 0x44
688; VI-NEXT:    s_mov_b32 s3, 0x1100f000
689; VI-NEXT:    s_mov_b32 s2, -1
690; VI-NEXT:    s_waitcnt lgkmcnt(0)
691; VI-NEXT:    s_cmp_eq_u32 s6, 3
692; VI-NEXT:    s_cselect_b32 s5, s4, s11
693; VI-NEXT:    s_cmp_eq_u32 s6, 2
694; VI-NEXT:    s_cselect_b32 s7, s4, s10
695; VI-NEXT:    s_cmp_eq_u32 s6, 1
696; VI-NEXT:    s_cselect_b32 s9, s4, s9
697; VI-NEXT:    s_cmp_eq_u32 s6, 0
698; VI-NEXT:    s_cselect_b32 s4, s4, s8
699; VI-NEXT:    v_mov_b32_e32 v0, s4
700; VI-NEXT:    v_mov_b32_e32 v1, s9
701; VI-NEXT:    v_mov_b32_e32 v2, s7
702; VI-NEXT:    v_mov_b32_e32 v3, s5
703; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
704; VI-NEXT:    s_endpgm
705  %vecins = insertelement <4 x i32> %a, i32 %val, i32 %b
706  store <4 x i32> %vecins, <4 x i32> addrspace(1)* %out, align 16
707  ret void
708}
709
710define amdgpu_kernel void @dynamic_insertelement_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> %a, i32 %b) nounwind {
711; SI-LABEL: dynamic_insertelement_v8i32:
712; SI:       ; %bb.0:
713; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
714; SI-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x8
715; SI-NEXT:    s_load_dword s4, s[4:5], 0x10
716; SI-NEXT:    s_mov_b32 s3, 0x100f000
717; SI-NEXT:    s_mov_b32 s2, -1
718; SI-NEXT:    s_waitcnt lgkmcnt(0)
719; SI-NEXT:    s_cmp_lg_u32 s4, 3
720; SI-NEXT:    s_cselect_b32 s5, s11, 5
721; SI-NEXT:    s_cmp_lg_u32 s4, 2
722; SI-NEXT:    s_cselect_b32 s6, s10, 5
723; SI-NEXT:    s_cmp_lg_u32 s4, 1
724; SI-NEXT:    s_cselect_b32 s7, s9, 5
725; SI-NEXT:    s_cmp_lg_u32 s4, 0
726; SI-NEXT:    s_cselect_b32 s8, s8, 5
727; SI-NEXT:    s_cmp_lg_u32 s4, 7
728; SI-NEXT:    s_cselect_b32 s9, s15, 5
729; SI-NEXT:    s_cmp_lg_u32 s4, 6
730; SI-NEXT:    s_cselect_b32 s10, s14, 5
731; SI-NEXT:    s_cmp_lg_u32 s4, 5
732; SI-NEXT:    s_cselect_b32 s11, s13, 5
733; SI-NEXT:    s_cmp_lg_u32 s4, 4
734; SI-NEXT:    s_cselect_b32 s4, s12, 5
735; SI-NEXT:    v_mov_b32_e32 v0, s4
736; SI-NEXT:    v_mov_b32_e32 v1, s11
737; SI-NEXT:    v_mov_b32_e32 v2, s10
738; SI-NEXT:    v_mov_b32_e32 v3, s9
739; SI-NEXT:    v_mov_b32_e32 v4, s8
740; SI-NEXT:    v_mov_b32_e32 v5, s7
741; SI-NEXT:    v_mov_b32_e32 v6, s6
742; SI-NEXT:    v_mov_b32_e32 v7, s5
743; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
744; SI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[0:3], 0
745; SI-NEXT:    s_endpgm
746;
747; VI-LABEL: dynamic_insertelement_v8i32:
748; VI:       ; %bb.0:
749; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
750; VI-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x20
751; VI-NEXT:    s_load_dword s4, s[4:5], 0x40
752; VI-NEXT:    s_mov_b32 s3, 0x1100f000
753; VI-NEXT:    s_mov_b32 s2, -1
754; VI-NEXT:    s_waitcnt lgkmcnt(0)
755; VI-NEXT:    s_cmp_lg_u32 s4, 3
756; VI-NEXT:    s_cselect_b32 s5, s11, 5
757; VI-NEXT:    s_cmp_lg_u32 s4, 2
758; VI-NEXT:    s_cselect_b32 s6, s10, 5
759; VI-NEXT:    s_cmp_lg_u32 s4, 1
760; VI-NEXT:    s_cselect_b32 s7, s9, 5
761; VI-NEXT:    s_cmp_lg_u32 s4, 0
762; VI-NEXT:    s_cselect_b32 s8, s8, 5
763; VI-NEXT:    s_cmp_lg_u32 s4, 7
764; VI-NEXT:    s_cselect_b32 s9, s15, 5
765; VI-NEXT:    s_cmp_lg_u32 s4, 6
766; VI-NEXT:    s_cselect_b32 s10, s14, 5
767; VI-NEXT:    s_cmp_lg_u32 s4, 5
768; VI-NEXT:    s_cselect_b32 s11, s13, 5
769; VI-NEXT:    s_cmp_lg_u32 s4, 4
770; VI-NEXT:    s_cselect_b32 s4, s12, 5
771; VI-NEXT:    v_mov_b32_e32 v0, s4
772; VI-NEXT:    v_mov_b32_e32 v1, s11
773; VI-NEXT:    v_mov_b32_e32 v2, s10
774; VI-NEXT:    v_mov_b32_e32 v3, s9
775; VI-NEXT:    v_mov_b32_e32 v4, s8
776; VI-NEXT:    v_mov_b32_e32 v5, s7
777; VI-NEXT:    v_mov_b32_e32 v6, s6
778; VI-NEXT:    v_mov_b32_e32 v7, s5
779; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
780; VI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[0:3], 0
781; VI-NEXT:    s_endpgm
782  %vecins = insertelement <8 x i32> %a, i32 5, i32 %b
783  store <8 x i32> %vecins, <8 x i32> addrspace(1)* %out, align 32
784  ret void
785}
786
787define amdgpu_kernel void @dynamic_insertelement_v16i32(<16 x i32> addrspace(1)* %out, <16 x i32> %a, i32 %b) nounwind {
788; SI-LABEL: dynamic_insertelement_v16i32:
789; SI:       ; %bb.0:
790; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
791; SI-NEXT:    s_load_dwordx16 s[8:23], s[4:5], 0x10
792; SI-NEXT:    s_load_dword s4, s[4:5], 0x20
793; SI-NEXT:    s_mov_b32 s3, 0x100f000
794; SI-NEXT:    s_mov_b32 s2, -1
795; SI-NEXT:    s_waitcnt lgkmcnt(0)
796; SI-NEXT:    v_mov_b32_e32 v0, s8
797; SI-NEXT:    v_mov_b32_e32 v1, s9
798; SI-NEXT:    v_mov_b32_e32 v2, s10
799; SI-NEXT:    v_mov_b32_e32 v3, s11
800; SI-NEXT:    v_mov_b32_e32 v4, s12
801; SI-NEXT:    v_mov_b32_e32 v5, s13
802; SI-NEXT:    v_mov_b32_e32 v6, s14
803; SI-NEXT:    v_mov_b32_e32 v7, s15
804; SI-NEXT:    v_mov_b32_e32 v8, s16
805; SI-NEXT:    v_mov_b32_e32 v9, s17
806; SI-NEXT:    v_mov_b32_e32 v10, s18
807; SI-NEXT:    v_mov_b32_e32 v11, s19
808; SI-NEXT:    v_mov_b32_e32 v12, s20
809; SI-NEXT:    v_mov_b32_e32 v13, s21
810; SI-NEXT:    v_mov_b32_e32 v14, s22
811; SI-NEXT:    v_mov_b32_e32 v15, s23
812; SI-NEXT:    s_mov_b32 m0, s4
813; SI-NEXT:    v_movreld_b32_e32 v0, 5
814; SI-NEXT:    buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48
815; SI-NEXT:    buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32
816; SI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
817; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
818; SI-NEXT:    s_endpgm
819;
820; VI-LABEL: dynamic_insertelement_v16i32:
821; VI:       ; %bb.0:
822; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
823; VI-NEXT:    s_load_dwordx16 s[8:23], s[4:5], 0x40
824; VI-NEXT:    s_load_dword s4, s[4:5], 0x80
825; VI-NEXT:    s_mov_b32 s3, 0x1100f000
826; VI-NEXT:    s_mov_b32 s2, -1
827; VI-NEXT:    s_waitcnt lgkmcnt(0)
828; VI-NEXT:    v_mov_b32_e32 v0, s8
829; VI-NEXT:    v_mov_b32_e32 v1, s9
830; VI-NEXT:    v_mov_b32_e32 v2, s10
831; VI-NEXT:    v_mov_b32_e32 v3, s11
832; VI-NEXT:    v_mov_b32_e32 v4, s12
833; VI-NEXT:    v_mov_b32_e32 v5, s13
834; VI-NEXT:    v_mov_b32_e32 v6, s14
835; VI-NEXT:    v_mov_b32_e32 v7, s15
836; VI-NEXT:    v_mov_b32_e32 v8, s16
837; VI-NEXT:    v_mov_b32_e32 v9, s17
838; VI-NEXT:    v_mov_b32_e32 v10, s18
839; VI-NEXT:    v_mov_b32_e32 v11, s19
840; VI-NEXT:    v_mov_b32_e32 v12, s20
841; VI-NEXT:    v_mov_b32_e32 v13, s21
842; VI-NEXT:    v_mov_b32_e32 v14, s22
843; VI-NEXT:    v_mov_b32_e32 v15, s23
844; VI-NEXT:    s_mov_b32 m0, s4
845; VI-NEXT:    v_movreld_b32_e32 v0, 5
846; VI-NEXT:    buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48
847; VI-NEXT:    buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32
848; VI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
849; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
850; VI-NEXT:    s_endpgm
851  %vecins = insertelement <16 x i32> %a, i32 5, i32 %b
852  store <16 x i32> %vecins, <16 x i32> addrspace(1)* %out, align 64
853  ret void
854}
855
856define amdgpu_kernel void @dynamic_insertelement_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %a, i32 %b) nounwind {
857; SI-LABEL: dynamic_insertelement_v2i16:
858; SI:       ; %bb.0:
859; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
860; SI-NEXT:    s_load_dword s6, s[4:5], 0x2
861; SI-NEXT:    s_load_dword s4, s[4:5], 0x3
862; SI-NEXT:    v_mov_b32_e32 v0, 0x50005
863; SI-NEXT:    s_mov_b32 s3, 0x100f000
864; SI-NEXT:    s_mov_b32 s2, -1
865; SI-NEXT:    s_waitcnt lgkmcnt(0)
866; SI-NEXT:    v_mov_b32_e32 v1, s6
867; SI-NEXT:    s_lshl_b32 s4, s4, 4
868; SI-NEXT:    s_lshl_b32 s4, 0xffff, s4
869; SI-NEXT:    v_bfi_b32 v0, s4, v0, v1
870; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
871; SI-NEXT:    s_endpgm
872;
873; VI-LABEL: dynamic_insertelement_v2i16:
874; VI:       ; %bb.0:
875; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
876; VI-NEXT:    s_load_dword s6, s[4:5], 0x8
877; VI-NEXT:    s_load_dword s4, s[4:5], 0xc
878; VI-NEXT:    v_mov_b32_e32 v0, 0x50005
879; VI-NEXT:    s_mov_b32 s3, 0x1100f000
880; VI-NEXT:    s_mov_b32 s2, -1
881; VI-NEXT:    s_waitcnt lgkmcnt(0)
882; VI-NEXT:    v_mov_b32_e32 v1, s6
883; VI-NEXT:    s_lshl_b32 s4, s4, 4
884; VI-NEXT:    s_lshl_b32 s4, 0xffff, s4
885; VI-NEXT:    v_bfi_b32 v0, s4, v0, v1
886; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
887; VI-NEXT:    s_endpgm
888  %vecins = insertelement <2 x i16> %a, i16 5, i32 %b
889  store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out, align 8
890  ret void
891}
892
893define amdgpu_kernel void @dynamic_insertelement_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %a, i32 %b) nounwind {
894; SI-LABEL: dynamic_insertelement_v3i16:
895; SI:       ; %bb.0:
896; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
897; SI-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x2
898; SI-NEXT:    s_load_dword s4, s[4:5], 0x4
899; SI-NEXT:    s_mov_b32 s5, 0
900; SI-NEXT:    s_mov_b32 s3, 0x100f000
901; SI-NEXT:    s_mov_b32 s2, -1
902; SI-NEXT:    s_waitcnt lgkmcnt(0)
903; SI-NEXT:    s_lshl_b32 s8, s4, 4
904; SI-NEXT:    s_mov_b32 s4, 0xffff
905; SI-NEXT:    s_lshl_b64 s[4:5], s[4:5], s8
906; SI-NEXT:    s_mov_b32 s8, 0x50005
907; SI-NEXT:    s_and_b32 s9, s5, s8
908; SI-NEXT:    s_and_b32 s8, s4, s8
909; SI-NEXT:    s_andn2_b64 s[4:5], s[6:7], s[4:5]
910; SI-NEXT:    s_or_b64 s[4:5], s[8:9], s[4:5]
911; SI-NEXT:    v_mov_b32_e32 v0, s5
912; SI-NEXT:    v_mov_b32_e32 v1, s4
913; SI-NEXT:    buffer_store_short v0, off, s[0:3], 0 offset:4
914; SI-NEXT:    buffer_store_dword v1, off, s[0:3], 0
915; SI-NEXT:    s_endpgm
916;
917; VI-LABEL: dynamic_insertelement_v3i16:
918; VI:       ; %bb.0:
919; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
920; VI-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x8
921; VI-NEXT:    s_load_dword s4, s[4:5], 0x10
922; VI-NEXT:    s_mov_b32 s5, 0
923; VI-NEXT:    s_mov_b32 s3, 0x1100f000
924; VI-NEXT:    s_mov_b32 s2, -1
925; VI-NEXT:    s_waitcnt lgkmcnt(0)
926; VI-NEXT:    v_mov_b32_e32 v1, s7
927; VI-NEXT:    s_lshl_b32 s8, s4, 4
928; VI-NEXT:    s_mov_b32 s4, 0xffff
929; VI-NEXT:    s_lshl_b64 s[4:5], s[4:5], s8
930; VI-NEXT:    s_mov_b32 s8, 0x50005
931; VI-NEXT:    v_mov_b32_e32 v0, s8
932; VI-NEXT:    v_bfi_b32 v0, s5, v0, v1
933; VI-NEXT:    v_mov_b32_e32 v1, s8
934; VI-NEXT:    v_mov_b32_e32 v2, s6
935; VI-NEXT:    v_bfi_b32 v1, s4, v1, v2
936; VI-NEXT:    buffer_store_short v0, off, s[0:3], 0 offset:4
937; VI-NEXT:    buffer_store_dword v1, off, s[0:3], 0
938; VI-NEXT:    s_endpgm
939  %vecins = insertelement <3 x i16> %a, i16 5, i32 %b
940  store <3 x i16> %vecins, <3 x i16> addrspace(1)* %out, align 8
941  ret void
942}
943
944define amdgpu_kernel void @dynamic_insertelement_v2i8(<2 x i8> addrspace(1)* %out, [8 x i32], <2 x i8> %a, [8 x i32], i32 %b) nounwind {
945; SI-LABEL: dynamic_insertelement_v2i8:
946; SI:       ; %bb.0:
947; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
948; SI-NEXT:    s_load_dword s6, s[4:5], 0xa
949; SI-NEXT:    s_load_dword s4, s[4:5], 0x13
950; SI-NEXT:    v_mov_b32_e32 v0, 0x505
951; SI-NEXT:    s_mov_b32 s3, 0x100f000
952; SI-NEXT:    s_mov_b32 s2, -1
953; SI-NEXT:    s_waitcnt lgkmcnt(0)
954; SI-NEXT:    v_mov_b32_e32 v1, s6
955; SI-NEXT:    s_lshl_b32 s4, s4, 3
956; SI-NEXT:    s_lshl_b32 s4, -1, s4
957; SI-NEXT:    v_bfi_b32 v0, s4, v0, v1
958; SI-NEXT:    buffer_store_short v0, off, s[0:3], 0
959; SI-NEXT:    s_endpgm
960;
961; VI-LABEL: dynamic_insertelement_v2i8:
962; VI:       ; %bb.0:
963; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
964; VI-NEXT:    s_load_dword s6, s[4:5], 0x28
965; VI-NEXT:    s_load_dword s4, s[4:5], 0x4c
966; VI-NEXT:    s_mov_b32 s3, 0x1100f000
967; VI-NEXT:    s_mov_b32 s2, -1
968; VI-NEXT:    s_waitcnt lgkmcnt(0)
969; VI-NEXT:    s_lshl_b32 s4, s4, 3
970; VI-NEXT:    v_lshlrev_b16_e64 v0, s4, -1
971; VI-NEXT:    v_and_b32_e32 v1, 0x505, v0
972; VI-NEXT:    v_xor_b32_e32 v0, -1, v0
973; VI-NEXT:    v_and_b32_e32 v0, s6, v0
974; VI-NEXT:    v_or_b32_e32 v0, v1, v0
975; VI-NEXT:    buffer_store_short v0, off, s[0:3], 0
976; VI-NEXT:    s_endpgm
977  %vecins = insertelement <2 x i8> %a, i8 5, i32 %b
978  store <2 x i8> %vecins, <2 x i8> addrspace(1)* %out, align 8
979  ret void
980}
981
982; FIXME: post legalize i16 and i32 shifts aren't merged because of
983; isTypeDesirableForOp in SimplifyDemandedBits
984define amdgpu_kernel void @dynamic_insertelement_v3i8(<3 x i8> addrspace(1)* %out, [8 x i32], <3 x i8> %a, [8 x i32], i32 %b) nounwind {
985; SI-LABEL: dynamic_insertelement_v3i8:
986; SI:       ; %bb.0:
987; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
988; SI-NEXT:    s_load_dword s6, s[4:5], 0xa
989; SI-NEXT:    s_load_dword s4, s[4:5], 0x13
990; SI-NEXT:    v_mov_b32_e32 v0, 0x5050505
991; SI-NEXT:    s_mov_b32 s3, 0x100f000
992; SI-NEXT:    s_mov_b32 s2, -1
993; SI-NEXT:    s_waitcnt lgkmcnt(0)
994; SI-NEXT:    v_mov_b32_e32 v1, s6
995; SI-NEXT:    s_lshl_b32 s4, s4, 3
996; SI-NEXT:    s_lshl_b32 s4, 0xffff, s4
997; SI-NEXT:    v_bfi_b32 v0, s4, v0, v1
998; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
999; SI-NEXT:    buffer_store_short v0, off, s[0:3], 0
1000; SI-NEXT:    buffer_store_byte v1, off, s[0:3], 0 offset:2
1001; SI-NEXT:    s_endpgm
1002;
1003; VI-LABEL: dynamic_insertelement_v3i8:
1004; VI:       ; %bb.0:
1005; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
1006; VI-NEXT:    s_load_dword s6, s[4:5], 0x28
1007; VI-NEXT:    s_load_dword s4, s[4:5], 0x4c
1008; VI-NEXT:    v_mov_b32_e32 v0, 0x5050505
1009; VI-NEXT:    s_mov_b32 s3, 0x1100f000
1010; VI-NEXT:    s_mov_b32 s2, -1
1011; VI-NEXT:    s_waitcnt lgkmcnt(0)
1012; VI-NEXT:    v_mov_b32_e32 v1, s6
1013; VI-NEXT:    s_lshl_b32 s4, s4, 3
1014; VI-NEXT:    s_lshl_b32 s4, 0xffff, s4
1015; VI-NEXT:    v_bfi_b32 v0, s4, v0, v1
1016; VI-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
1017; VI-NEXT:    buffer_store_short v0, off, s[0:3], 0
1018; VI-NEXT:    buffer_store_byte v1, off, s[0:3], 0 offset:2
1019; VI-NEXT:    s_endpgm
1020  %vecins = insertelement <3 x i8> %a, i8 5, i32 %b
1021  store <3 x i8> %vecins, <3 x i8> addrspace(1)* %out, align 4
1022  ret void
1023}
1024
1025define amdgpu_kernel void @dynamic_insertelement_v4i8(<4 x i8> addrspace(1)* %out, [8 x i32], <4 x i8> %a, [8 x i32], i32 %b) nounwind {
1026; SI-LABEL: dynamic_insertelement_v4i8:
1027; SI:       ; %bb.0:
1028; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
1029; SI-NEXT:    s_load_dword s6, s[4:5], 0xa
1030; SI-NEXT:    s_load_dword s4, s[4:5], 0x13
1031; SI-NEXT:    v_mov_b32_e32 v0, 0x5050505
1032; SI-NEXT:    s_mov_b32 s3, 0x100f000
1033; SI-NEXT:    s_mov_b32 s2, -1
1034; SI-NEXT:    s_waitcnt lgkmcnt(0)
1035; SI-NEXT:    v_mov_b32_e32 v1, s6
1036; SI-NEXT:    s_lshl_b32 s4, s4, 3
1037; SI-NEXT:    s_lshl_b32 s4, 0xffff, s4
1038; SI-NEXT:    v_bfi_b32 v0, s4, v0, v1
1039; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
1040; SI-NEXT:    s_endpgm
1041;
1042; VI-LABEL: dynamic_insertelement_v4i8:
1043; VI:       ; %bb.0:
1044; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
1045; VI-NEXT:    s_load_dword s6, s[4:5], 0x28
1046; VI-NEXT:    s_load_dword s4, s[4:5], 0x4c
1047; VI-NEXT:    v_mov_b32_e32 v0, 0x5050505
1048; VI-NEXT:    s_mov_b32 s3, 0x1100f000
1049; VI-NEXT:    s_mov_b32 s2, -1
1050; VI-NEXT:    s_waitcnt lgkmcnt(0)
1051; VI-NEXT:    v_mov_b32_e32 v1, s6
1052; VI-NEXT:    s_lshl_b32 s4, s4, 3
1053; VI-NEXT:    s_lshl_b32 s4, 0xffff, s4
1054; VI-NEXT:    v_bfi_b32 v0, s4, v0, v1
1055; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
1056; VI-NEXT:    s_endpgm
1057  %vecins = insertelement <4 x i8> %a, i8 5, i32 %b
1058  store <4 x i8> %vecins, <4 x i8> addrspace(1)* %out, align 4
1059  ret void
1060}
1061
1062define amdgpu_kernel void @s_dynamic_insertelement_v8i8(<8 x i8> addrspace(1)* %out, <8 x i8> addrspace(4)* %a.ptr, i32 %b) nounwind {
1063; SI-LABEL: s_dynamic_insertelement_v8i8:
1064; SI:       ; %bb.0:
1065; SI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x0
1066; SI-NEXT:    s_load_dword s6, s[4:5], 0x4
1067; SI-NEXT:    s_mov_b32 s7, 0
1068; SI-NEXT:    s_mov_b32 s3, 0x100f000
1069; SI-NEXT:    s_mov_b32 s2, -1
1070; SI-NEXT:    s_waitcnt lgkmcnt(0)
1071; SI-NEXT:    s_load_dwordx2 s[4:5], s[10:11], 0x0
1072; SI-NEXT:    s_mov_b32 s0, s8
1073; SI-NEXT:    s_lshl_b32 s8, s6, 3
1074; SI-NEXT:    s_mov_b32 s6, 0xffff
1075; SI-NEXT:    s_lshl_b64 s[6:7], s[6:7], s8
1076; SI-NEXT:    s_mov_b32 s8, 0x5050505
1077; SI-NEXT:    s_mov_b32 s1, s9
1078; SI-NEXT:    s_and_b32 s9, s7, s8
1079; SI-NEXT:    s_and_b32 s8, s6, s8
1080; SI-NEXT:    s_waitcnt lgkmcnt(0)
1081; SI-NEXT:    s_andn2_b64 s[4:5], s[4:5], s[6:7]
1082; SI-NEXT:    s_or_b64 s[4:5], s[8:9], s[4:5]
1083; SI-NEXT:    v_mov_b32_e32 v0, s4
1084; SI-NEXT:    v_mov_b32_e32 v1, s5
1085; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1086; SI-NEXT:    s_endpgm
1087;
1088; VI-LABEL: s_dynamic_insertelement_v8i8:
1089; VI:       ; %bb.0:
1090; VI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x0
1091; VI-NEXT:    s_load_dword s6, s[4:5], 0x10
1092; VI-NEXT:    s_mov_b32 s7, 0
1093; VI-NEXT:    s_mov_b32 s3, 0x1100f000
1094; VI-NEXT:    s_mov_b32 s2, -1
1095; VI-NEXT:    s_waitcnt lgkmcnt(0)
1096; VI-NEXT:    s_load_dwordx2 s[4:5], s[10:11], 0x0
1097; VI-NEXT:    s_mov_b32 s0, s8
1098; VI-NEXT:    s_lshl_b32 s8, s6, 3
1099; VI-NEXT:    s_mov_b32 s6, 0xffff
1100; VI-NEXT:    s_lshl_b64 s[6:7], s[6:7], s8
1101; VI-NEXT:    s_mov_b32 s8, 0x5050505
1102; VI-NEXT:    s_mov_b32 s1, s9
1103; VI-NEXT:    s_and_b32 s9, s7, s8
1104; VI-NEXT:    s_and_b32 s8, s6, s8
1105; VI-NEXT:    s_waitcnt lgkmcnt(0)
1106; VI-NEXT:    s_andn2_b64 s[4:5], s[4:5], s[6:7]
1107; VI-NEXT:    s_or_b64 s[4:5], s[8:9], s[4:5]
1108; VI-NEXT:    v_mov_b32_e32 v0, s4
1109; VI-NEXT:    v_mov_b32_e32 v1, s5
1110; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1111; VI-NEXT:    s_endpgm
1112  %a = load <8 x i8>, <8 x i8> addrspace(4)* %a.ptr, align 4
1113  %vecins = insertelement <8 x i8> %a, i8 5, i32 %b
1114  store <8 x i8> %vecins, <8 x i8> addrspace(1)* %out, align 8
1115  ret void
1116}
1117
1118define amdgpu_kernel void @dynamic_insertelement_v16i8(<16 x i8> addrspace(1)* %out, <16 x i8> %a, i32 %b) nounwind {
1119; SI-LABEL: dynamic_insertelement_v16i8:
1120; SI:       ; %bb.0:
1121; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
1122; SI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x4
1123; SI-NEXT:    s_load_dword s4, s[4:5], 0x8
1124; SI-NEXT:    s_movk_i32 s7, 0xff
1125; SI-NEXT:    s_mov_b32 s3, 0x100f000
1126; SI-NEXT:    s_mov_b32 s2, -1
1127; SI-NEXT:    s_waitcnt lgkmcnt(0)
1128; SI-NEXT:    s_lshr_b32 s5, s11, 24
1129; SI-NEXT:    s_cmp_lg_u32 s4, 15
1130; SI-NEXT:    s_cselect_b32 s5, s5, 5
1131; SI-NEXT:    s_lshl_b32 s5, s5, 8
1132; SI-NEXT:    s_lshr_b32 s6, s11, 16
1133; SI-NEXT:    s_cmp_lg_u32 s4, 14
1134; SI-NEXT:    s_cselect_b32 s6, s6, 5
1135; SI-NEXT:    s_and_b32 s6, s6, s7
1136; SI-NEXT:    s_or_b32 s5, s6, s5
1137; SI-NEXT:    s_lshl_b32 s5, s5, 16
1138; SI-NEXT:    s_lshr_b32 s6, s11, 8
1139; SI-NEXT:    s_cmp_lg_u32 s4, 13
1140; SI-NEXT:    s_cselect_b32 s6, s6, 5
1141; SI-NEXT:    s_lshl_b32 s6, s6, 8
1142; SI-NEXT:    s_cmp_lg_u32 s4, 12
1143; SI-NEXT:    s_cselect_b32 s11, s11, 5
1144; SI-NEXT:    s_and_b32 s11, s11, s7
1145; SI-NEXT:    s_or_b32 s6, s11, s6
1146; SI-NEXT:    s_mov_b32 s11, 0xffff
1147; SI-NEXT:    s_and_b32 s6, s6, s11
1148; SI-NEXT:    s_or_b32 s5, s6, s5
1149; SI-NEXT:    s_lshr_b32 s6, s10, 24
1150; SI-NEXT:    s_cmp_lg_u32 s4, 11
1151; SI-NEXT:    s_cselect_b32 s6, s6, 5
1152; SI-NEXT:    s_lshl_b32 s6, s6, 8
1153; SI-NEXT:    s_lshr_b32 s12, s10, 16
1154; SI-NEXT:    s_cmp_lg_u32 s4, 10
1155; SI-NEXT:    s_cselect_b32 s12, s12, 5
1156; SI-NEXT:    s_and_b32 s12, s12, s7
1157; SI-NEXT:    s_or_b32 s6, s12, s6
1158; SI-NEXT:    s_lshl_b32 s6, s6, 16
1159; SI-NEXT:    s_lshr_b32 s12, s10, 8
1160; SI-NEXT:    s_cmp_lg_u32 s4, 9
1161; SI-NEXT:    s_cselect_b32 s12, s12, 5
1162; SI-NEXT:    s_lshl_b32 s12, s12, 8
1163; SI-NEXT:    s_cmp_lg_u32 s4, 8
1164; SI-NEXT:    s_cselect_b32 s10, s10, 5
1165; SI-NEXT:    s_and_b32 s10, s10, s7
1166; SI-NEXT:    s_or_b32 s10, s10, s12
1167; SI-NEXT:    s_and_b32 s10, s10, s11
1168; SI-NEXT:    s_or_b32 s6, s10, s6
1169; SI-NEXT:    s_lshr_b32 s10, s9, 24
1170; SI-NEXT:    s_cmp_lg_u32 s4, 7
1171; SI-NEXT:    s_cselect_b32 s10, s10, 5
1172; SI-NEXT:    s_lshl_b32 s10, s10, 8
1173; SI-NEXT:    s_lshr_b32 s12, s9, 16
1174; SI-NEXT:    s_cmp_lg_u32 s4, 6
1175; SI-NEXT:    s_cselect_b32 s12, s12, 5
1176; SI-NEXT:    s_and_b32 s12, s12, s7
1177; SI-NEXT:    s_or_b32 s10, s12, s10
1178; SI-NEXT:    s_lshl_b32 s10, s10, 16
1179; SI-NEXT:    s_lshr_b32 s12, s9, 8
1180; SI-NEXT:    s_cmp_lg_u32 s4, 5
1181; SI-NEXT:    s_cselect_b32 s12, s12, 5
1182; SI-NEXT:    s_lshl_b32 s12, s12, 8
1183; SI-NEXT:    s_cmp_lg_u32 s4, 4
1184; SI-NEXT:    s_cselect_b32 s9, s9, 5
1185; SI-NEXT:    s_and_b32 s9, s9, s7
1186; SI-NEXT:    s_or_b32 s9, s9, s12
1187; SI-NEXT:    s_and_b32 s9, s9, s11
1188; SI-NEXT:    s_or_b32 s9, s9, s10
1189; SI-NEXT:    s_lshr_b32 s10, s8, 24
1190; SI-NEXT:    s_cmp_lg_u32 s4, 3
1191; SI-NEXT:    s_cselect_b32 s10, s10, 5
1192; SI-NEXT:    s_lshl_b32 s10, s10, 8
1193; SI-NEXT:    s_lshr_b32 s12, s8, 16
1194; SI-NEXT:    s_cmp_lg_u32 s4, 2
1195; SI-NEXT:    s_cselect_b32 s12, s12, 5
1196; SI-NEXT:    s_and_b32 s12, s12, s7
1197; SI-NEXT:    s_or_b32 s10, s12, s10
1198; SI-NEXT:    s_lshl_b32 s10, s10, 16
1199; SI-NEXT:    s_lshr_b32 s12, s8, 8
1200; SI-NEXT:    s_cmp_lg_u32 s4, 1
1201; SI-NEXT:    s_cselect_b32 s12, s12, 5
1202; SI-NEXT:    s_lshl_b32 s12, s12, 8
1203; SI-NEXT:    s_cmp_lg_u32 s4, 0
1204; SI-NEXT:    s_cselect_b32 s4, s8, 5
1205; SI-NEXT:    s_and_b32 s4, s4, s7
1206; SI-NEXT:    s_or_b32 s4, s4, s12
1207; SI-NEXT:    s_and_b32 s4, s4, s11
1208; SI-NEXT:    s_or_b32 s4, s4, s10
1209; SI-NEXT:    v_mov_b32_e32 v0, s4
1210; SI-NEXT:    v_mov_b32_e32 v1, s9
1211; SI-NEXT:    v_mov_b32_e32 v2, s6
1212; SI-NEXT:    v_mov_b32_e32 v3, s5
1213; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
1214; SI-NEXT:    s_endpgm
1215;
1216; VI-LABEL: dynamic_insertelement_v16i8:
1217; VI:       ; %bb.0:
1218; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
1219; VI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x10
1220; VI-NEXT:    s_load_dword s4, s[4:5], 0x20
1221; VI-NEXT:    s_mov_b32 s3, 0x1100f000
1222; VI-NEXT:    s_mov_b32 s2, -1
1223; VI-NEXT:    s_waitcnt lgkmcnt(0)
1224; VI-NEXT:    s_lshr_b32 s5, s11, 24
1225; VI-NEXT:    v_mov_b32_e32 v0, s5
1226; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 15
1227; VI-NEXT:    s_lshr_b32 s5, s11, 16
1228; VI-NEXT:    v_cndmask_b32_e32 v0, 5, v0, vcc
1229; VI-NEXT:    v_mov_b32_e32 v1, s5
1230; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 14
1231; VI-NEXT:    v_cndmask_b32_e32 v1, 5, v1, vcc
1232; VI-NEXT:    v_lshlrev_b16_e32 v0, 8, v0
1233; VI-NEXT:    s_lshr_b32 s5, s11, 8
1234; VI-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
1235; VI-NEXT:    v_mov_b32_e32 v1, s5
1236; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 13
1237; VI-NEXT:    v_cndmask_b32_e32 v1, 5, v1, vcc
1238; VI-NEXT:    v_mov_b32_e32 v2, s11
1239; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 12
1240; VI-NEXT:    v_cndmask_b32_e32 v2, 5, v2, vcc
1241; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v1
1242; VI-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
1243; VI-NEXT:    s_lshr_b32 s5, s10, 24
1244; VI-NEXT:    v_or_b32_sdwa v3, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
1245; VI-NEXT:    v_mov_b32_e32 v0, s5
1246; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 11
1247; VI-NEXT:    s_lshr_b32 s5, s10, 16
1248; VI-NEXT:    v_cndmask_b32_e32 v0, 5, v0, vcc
1249; VI-NEXT:    v_mov_b32_e32 v1, s5
1250; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 10
1251; VI-NEXT:    v_cndmask_b32_e32 v1, 5, v1, vcc
1252; VI-NEXT:    v_lshlrev_b16_e32 v0, 8, v0
1253; VI-NEXT:    s_lshr_b32 s5, s10, 8
1254; VI-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
1255; VI-NEXT:    v_mov_b32_e32 v1, s5
1256; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 9
1257; VI-NEXT:    v_cndmask_b32_e32 v1, 5, v1, vcc
1258; VI-NEXT:    v_mov_b32_e32 v2, s10
1259; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 8
1260; VI-NEXT:    v_cndmask_b32_e32 v2, 5, v2, vcc
1261; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v1
1262; VI-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
1263; VI-NEXT:    s_lshr_b32 s5, s9, 24
1264; VI-NEXT:    v_or_b32_sdwa v2, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
1265; VI-NEXT:    v_mov_b32_e32 v0, s5
1266; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 7
1267; VI-NEXT:    s_lshr_b32 s5, s9, 16
1268; VI-NEXT:    v_cndmask_b32_e32 v0, 5, v0, vcc
1269; VI-NEXT:    v_mov_b32_e32 v1, s5
1270; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 6
1271; VI-NEXT:    v_cndmask_b32_e32 v1, 5, v1, vcc
1272; VI-NEXT:    v_lshlrev_b16_e32 v0, 8, v0
1273; VI-NEXT:    s_lshr_b32 s5, s9, 8
1274; VI-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
1275; VI-NEXT:    v_mov_b32_e32 v1, s5
1276; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 5
1277; VI-NEXT:    v_cndmask_b32_e32 v1, 5, v1, vcc
1278; VI-NEXT:    v_mov_b32_e32 v4, s9
1279; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 4
1280; VI-NEXT:    v_cndmask_b32_e32 v4, 5, v4, vcc
1281; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v1
1282; VI-NEXT:    v_or_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
1283; VI-NEXT:    s_lshr_b32 s5, s8, 24
1284; VI-NEXT:    v_or_b32_sdwa v1, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
1285; VI-NEXT:    v_mov_b32_e32 v0, s5
1286; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 3
1287; VI-NEXT:    s_lshr_b32 s5, s8, 16
1288; VI-NEXT:    v_cndmask_b32_e32 v0, 5, v0, vcc
1289; VI-NEXT:    v_mov_b32_e32 v4, s5
1290; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 2
1291; VI-NEXT:    v_cndmask_b32_e32 v4, 5, v4, vcc
1292; VI-NEXT:    v_lshlrev_b16_e32 v0, 8, v0
1293; VI-NEXT:    s_lshr_b32 s5, s8, 8
1294; VI-NEXT:    v_or_b32_sdwa v0, v4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
1295; VI-NEXT:    v_mov_b32_e32 v4, s5
1296; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 1
1297; VI-NEXT:    v_cndmask_b32_e32 v4, 5, v4, vcc
1298; VI-NEXT:    v_mov_b32_e32 v5, s8
1299; VI-NEXT:    v_cmp_ne_u32_e64 vcc, s4, 0
1300; VI-NEXT:    v_lshlrev_b16_e32 v4, 8, v4
1301; VI-NEXT:    v_cndmask_b32_e32 v5, 5, v5, vcc
1302; VI-NEXT:    v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
1303; VI-NEXT:    v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
1304; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
1305; VI-NEXT:    s_endpgm
1306  %vecins = insertelement <16 x i8> %a, i8 5, i32 %b
1307  store <16 x i8> %vecins, <16 x i8> addrspace(1)* %out, align 16
1308  ret void
1309}
1310
1311; This test requires handling INSERT_SUBREG in SIFixSGPRCopies.  Check that
1312; the compiler doesn't crash.
1313define amdgpu_kernel void @insert_split_bb(<2 x i32> addrspace(1)* %out, i32 addrspace(1)* %in, i32 %a, i32 %b) {
1314; SI-LABEL: insert_split_bb:
1315; SI:       ; %bb.0: ; %entry
1316; SI-NEXT:    s_load_dword s0, s[4:5], 0x4
1317; SI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
1318; SI-NEXT:    s_waitcnt lgkmcnt(0)
1319; SI-NEXT:    s_cmp_lg_u32 s0, 0
1320; SI-NEXT:    s_cbranch_scc0 BB26_2
1321; SI-NEXT:  ; %bb.1: ; %else
1322; SI-NEXT:    s_load_dword s1, s[6:7], 0x1
1323; SI-NEXT:    s_mov_b64 s[2:3], 0
1324; SI-NEXT:    s_andn2_b64 vcc, exec, s[2:3]
1325; SI-NEXT:    s_waitcnt lgkmcnt(0)
1326; SI-NEXT:    s_mov_b64 vcc, vcc
1327; SI-NEXT:    s_cbranch_vccz BB26_3
1328; SI-NEXT:    s_branch BB26_4
1329; SI-NEXT:  BB26_2:
1330; SI-NEXT:    s_mov_b64 s[2:3], -1
1331; SI-NEXT:    s_andn2_b64 vcc, exec, s[2:3]
1332; SI-NEXT:    s_cbranch_vccnz BB26_4
1333; SI-NEXT:  BB26_3: ; %if
1334; SI-NEXT:    s_load_dword s1, s[6:7], 0x0
1335; SI-NEXT:  BB26_4: ; %endif
1336; SI-NEXT:    s_waitcnt lgkmcnt(0)
1337; SI-NEXT:    v_mov_b32_e32 v0, s0
1338; SI-NEXT:    s_mov_b32 s7, 0x100f000
1339; SI-NEXT:    s_mov_b32 s6, -1
1340; SI-NEXT:    v_mov_b32_e32 v1, s1
1341; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1342; SI-NEXT:    s_endpgm
1343;
1344; VI-LABEL: insert_split_bb:
1345; VI:       ; %bb.0: ; %entry
1346; VI-NEXT:    s_load_dword s0, s[4:5], 0x10
1347; VI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
1348; VI-NEXT:    s_waitcnt lgkmcnt(0)
1349; VI-NEXT:    s_cmp_lg_u32 s0, 0
1350; VI-NEXT:    s_cbranch_scc0 BB26_2
1351; VI-NEXT:  ; %bb.1: ; %else
1352; VI-NEXT:    s_load_dword s1, s[6:7], 0x4
1353; VI-NEXT:    s_mov_b64 s[2:3], 0
1354; VI-NEXT:    s_andn2_b64 vcc, exec, s[2:3]
1355; VI-NEXT:    s_cbranch_vccz BB26_3
1356; VI-NEXT:    s_branch BB26_4
1357; VI-NEXT:  BB26_2:
1358; VI-NEXT:    s_mov_b64 s[2:3], -1
1359; VI-NEXT:    s_andn2_b64 vcc, exec, s[2:3]
1360; VI-NEXT:    s_cbranch_vccnz BB26_4
1361; VI-NEXT:  BB26_3: ; %if
1362; VI-NEXT:    s_waitcnt lgkmcnt(0)
1363; VI-NEXT:    s_load_dword s1, s[6:7], 0x0
1364; VI-NEXT:  BB26_4: ; %endif
1365; VI-NEXT:    s_waitcnt lgkmcnt(0)
1366; VI-NEXT:    v_mov_b32_e32 v0, s0
1367; VI-NEXT:    s_mov_b32 s7, 0x1100f000
1368; VI-NEXT:    s_mov_b32 s6, -1
1369; VI-NEXT:    v_mov_b32_e32 v1, s1
1370; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1371; VI-NEXT:    s_endpgm
1372entry:
1373  %0 = insertelement <2 x i32> undef, i32 %a, i32 0
1374  %1 = icmp eq i32 %a, 0
1375  br i1 %1, label %if, label %else
1376
1377if:
1378  %2 = load i32, i32 addrspace(1)* %in
1379  %3 = insertelement <2 x i32> %0, i32 %2, i32 1
1380  br label %endif
1381
1382else:
1383  %4 = getelementptr i32, i32 addrspace(1)* %in, i32 1
1384  %5 = load i32, i32 addrspace(1)* %4
1385  %6 = insertelement <2 x i32> %0, i32 %5, i32 1
1386  br label %endif
1387
1388endif:
1389  %7 = phi <2 x i32> [%3, %if], [%6, %else]
1390  store <2 x i32> %7, <2 x i32> addrspace(1)* %out
1391  ret void
1392}
1393
1394define amdgpu_kernel void @dynamic_insertelement_v2f64(<2 x double> addrspace(1)* %out, [8 x i32], <2 x double> %a, [8 x i32], i32 %b) nounwind {
1395; SI-LABEL: dynamic_insertelement_v2f64:
1396; SI:       ; %bb.0:
1397; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
1398; SI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0xc
1399; SI-NEXT:    s_load_dword s4, s[4:5], 0x18
1400; SI-NEXT:    v_mov_b32_e32 v1, 0x40200000
1401; SI-NEXT:    s_mov_b32 s3, 0x100f000
1402; SI-NEXT:    s_mov_b32 s2, -1
1403; SI-NEXT:    s_waitcnt lgkmcnt(0)
1404; SI-NEXT:    v_mov_b32_e32 v0, s11
1405; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s4, 1
1406; SI-NEXT:    v_cndmask_b32_e32 v3, v0, v1, vcc
1407; SI-NEXT:    v_mov_b32_e32 v0, s10
1408; SI-NEXT:    v_cndmask_b32_e64 v2, v0, 0, vcc
1409; SI-NEXT:    v_mov_b32_e32 v0, s9
1410; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s4, 0
1411; SI-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
1412; SI-NEXT:    v_mov_b32_e32 v0, s8
1413; SI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc
1414; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
1415; SI-NEXT:    s_endpgm
1416;
1417; VI-LABEL: dynamic_insertelement_v2f64:
1418; VI:       ; %bb.0:
1419; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
1420; VI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x30
1421; VI-NEXT:    s_load_dword s4, s[4:5], 0x60
1422; VI-NEXT:    v_mov_b32_e32 v1, 0x40200000
1423; VI-NEXT:    s_mov_b32 s3, 0x1100f000
1424; VI-NEXT:    s_mov_b32 s2, -1
1425; VI-NEXT:    s_waitcnt lgkmcnt(0)
1426; VI-NEXT:    v_mov_b32_e32 v0, s11
1427; VI-NEXT:    v_cmp_eq_u32_e64 vcc, s4, 1
1428; VI-NEXT:    v_cndmask_b32_e32 v3, v0, v1, vcc
1429; VI-NEXT:    v_mov_b32_e32 v0, s10
1430; VI-NEXT:    v_cndmask_b32_e64 v2, v0, 0, vcc
1431; VI-NEXT:    v_mov_b32_e32 v0, s9
1432; VI-NEXT:    v_cmp_eq_u32_e64 vcc, s4, 0
1433; VI-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
1434; VI-NEXT:    v_mov_b32_e32 v0, s8
1435; VI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc
1436; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
1437; VI-NEXT:    s_endpgm
1438  %vecins = insertelement <2 x double> %a, double 8.0, i32 %b
1439  store <2 x double> %vecins, <2 x double> addrspace(1)* %out, align 16
1440  ret void
1441}
1442
1443define amdgpu_kernel void @dynamic_insertelement_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %a, i32 %b) nounwind {
1444; SI-LABEL: dynamic_insertelement_v2i64:
1445; SI:       ; %bb.0:
1446; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
1447; SI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x4
1448; SI-NEXT:    s_load_dword s6, s[4:5], 0x8
1449; SI-NEXT:    s_mov_b32 s3, 0x100f000
1450; SI-NEXT:    s_mov_b32 s2, -1
1451; SI-NEXT:    s_waitcnt lgkmcnt(0)
1452; SI-NEXT:    v_mov_b32_e32 v0, s11
1453; SI-NEXT:    v_cmp_eq_u32_e64 s[4:5], s6, 1
1454; SI-NEXT:    v_cndmask_b32_e64 v3, v0, 0, s[4:5]
1455; SI-NEXT:    v_mov_b32_e32 v0, s10
1456; SI-NEXT:    v_cndmask_b32_e64 v2, v0, 5, s[4:5]
1457; SI-NEXT:    v_mov_b32_e32 v0, s9
1458; SI-NEXT:    v_cmp_eq_u32_e64 s[4:5], s6, 0
1459; SI-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[4:5]
1460; SI-NEXT:    v_mov_b32_e32 v0, s8
1461; SI-NEXT:    v_cndmask_b32_e64 v0, v0, 5, s[4:5]
1462; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
1463; SI-NEXT:    s_endpgm
1464;
1465; VI-LABEL: dynamic_insertelement_v2i64:
1466; VI:       ; %bb.0:
1467; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
1468; VI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x10
1469; VI-NEXT:    s_load_dword s6, s[4:5], 0x20
1470; VI-NEXT:    s_mov_b32 s3, 0x1100f000
1471; VI-NEXT:    s_mov_b32 s2, -1
1472; VI-NEXT:    s_waitcnt lgkmcnt(0)
1473; VI-NEXT:    v_mov_b32_e32 v0, s11
1474; VI-NEXT:    v_cmp_eq_u32_e64 s[4:5], s6, 1
1475; VI-NEXT:    v_cndmask_b32_e64 v3, v0, 0, s[4:5]
1476; VI-NEXT:    v_mov_b32_e32 v0, s10
1477; VI-NEXT:    v_cndmask_b32_e64 v2, v0, 5, s[4:5]
1478; VI-NEXT:    v_mov_b32_e32 v0, s9
1479; VI-NEXT:    v_cmp_eq_u32_e64 s[4:5], s6, 0
1480; VI-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[4:5]
1481; VI-NEXT:    v_mov_b32_e32 v0, s8
1482; VI-NEXT:    v_cndmask_b32_e64 v0, v0, 5, s[4:5]
1483; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
1484; VI-NEXT:    s_endpgm
1485  %vecins = insertelement <2 x i64> %a, i64 5, i32 %b
1486  store <2 x i64> %vecins, <2 x i64> addrspace(1)* %out, align 8
1487  ret void
1488}
1489
1490define amdgpu_kernel void @dynamic_insertelement_v3i64(<3 x i64> addrspace(1)* %out, <3 x i64> %a, i32 %b) nounwind {
1491; SI-LABEL: dynamic_insertelement_v3i64:
1492; SI:       ; %bb.0:
1493; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
1494; SI-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x8
1495; SI-NEXT:    s_load_dword s6, s[4:5], 0x10
1496; SI-NEXT:    s_mov_b32 s3, 0x100f000
1497; SI-NEXT:    s_mov_b32 s2, -1
1498; SI-NEXT:    s_waitcnt lgkmcnt(0)
1499; SI-NEXT:    v_mov_b32_e32 v0, s13
1500; SI-NEXT:    v_cmp_eq_u32_e64 s[4:5], s6, 2
1501; SI-NEXT:    v_cndmask_b32_e64 v5, v0, 0, s[4:5]
1502; SI-NEXT:    v_mov_b32_e32 v0, s12
1503; SI-NEXT:    v_cndmask_b32_e64 v4, v0, 5, s[4:5]
1504; SI-NEXT:    v_mov_b32_e32 v0, s11
1505; SI-NEXT:    v_cmp_eq_u32_e64 s[4:5], s6, 1
1506; SI-NEXT:    v_cndmask_b32_e64 v3, v0, 0, s[4:5]
1507; SI-NEXT:    v_mov_b32_e32 v0, s10
1508; SI-NEXT:    v_cndmask_b32_e64 v2, v0, 5, s[4:5]
1509; SI-NEXT:    v_mov_b32_e32 v0, s9
1510; SI-NEXT:    v_cmp_eq_u32_e64 s[4:5], s6, 0
1511; SI-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[4:5]
1512; SI-NEXT:    v_mov_b32_e32 v0, s8
1513; SI-NEXT:    v_cndmask_b32_e64 v0, v0, 5, s[4:5]
1514; SI-NEXT:    buffer_store_dwordx2 v[4:5], off, s[0:3], 0 offset:16
1515; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
1516; SI-NEXT:    s_endpgm
1517;
1518; VI-LABEL: dynamic_insertelement_v3i64:
1519; VI:       ; %bb.0:
1520; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
1521; VI-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x20
1522; VI-NEXT:    s_load_dword s6, s[4:5], 0x40
1523; VI-NEXT:    s_mov_b32 s3, 0x1100f000
1524; VI-NEXT:    s_mov_b32 s2, -1
1525; VI-NEXT:    s_waitcnt lgkmcnt(0)
1526; VI-NEXT:    v_mov_b32_e32 v0, s13
1527; VI-NEXT:    v_cmp_eq_u32_e64 s[4:5], s6, 2
1528; VI-NEXT:    v_cndmask_b32_e64 v5, v0, 0, s[4:5]
1529; VI-NEXT:    v_mov_b32_e32 v0, s12
1530; VI-NEXT:    v_cndmask_b32_e64 v4, v0, 5, s[4:5]
1531; VI-NEXT:    v_mov_b32_e32 v0, s11
1532; VI-NEXT:    v_cmp_eq_u32_e64 s[4:5], s6, 1
1533; VI-NEXT:    v_cndmask_b32_e64 v3, v0, 0, s[4:5]
1534; VI-NEXT:    v_mov_b32_e32 v0, s10
1535; VI-NEXT:    v_cndmask_b32_e64 v2, v0, 5, s[4:5]
1536; VI-NEXT:    v_mov_b32_e32 v0, s9
1537; VI-NEXT:    v_cmp_eq_u32_e64 s[4:5], s6, 0
1538; VI-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[4:5]
1539; VI-NEXT:    v_mov_b32_e32 v0, s8
1540; VI-NEXT:    v_cndmask_b32_e64 v0, v0, 5, s[4:5]
1541; VI-NEXT:    buffer_store_dwordx2 v[4:5], off, s[0:3], 0 offset:16
1542; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
1543; VI-NEXT:    s_endpgm
1544  %vecins = insertelement <3 x i64> %a, i64 5, i32 %b
1545  store <3 x i64> %vecins, <3 x i64> addrspace(1)* %out, align 32
1546  ret void
1547}
1548
1549define amdgpu_kernel void @dynamic_insertelement_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %a, i32 %b) nounwind {
1550; SI-LABEL: dynamic_insertelement_v4f64:
1551; SI:       ; %bb.0:
1552; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
1553; SI-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x8
1554; SI-NEXT:    s_load_dword s4, s[4:5], 0x10
1555; SI-NEXT:    v_mov_b32_e32 v4, 0x40200000
1556; SI-NEXT:    s_mov_b32 s3, 0x100f000
1557; SI-NEXT:    s_mov_b32 s2, -1
1558; SI-NEXT:    s_waitcnt lgkmcnt(0)
1559; SI-NEXT:    v_mov_b32_e32 v0, s11
1560; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s4, 1
1561; SI-NEXT:    v_cndmask_b32_e32 v3, v0, v4, vcc
1562; SI-NEXT:    v_mov_b32_e32 v0, s10
1563; SI-NEXT:    v_cndmask_b32_e64 v2, v0, 0, vcc
1564; SI-NEXT:    v_mov_b32_e32 v0, s9
1565; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s4, 0
1566; SI-NEXT:    v_cndmask_b32_e32 v1, v0, v4, vcc
1567; SI-NEXT:    v_mov_b32_e32 v0, s8
1568; SI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc
1569; SI-NEXT:    v_mov_b32_e32 v5, s15
1570; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s4, 3
1571; SI-NEXT:    v_cndmask_b32_e32 v7, v5, v4, vcc
1572; SI-NEXT:    v_mov_b32_e32 v5, s14
1573; SI-NEXT:    v_cndmask_b32_e64 v6, v5, 0, vcc
1574; SI-NEXT:    v_mov_b32_e32 v5, s13
1575; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s4, 2
1576; SI-NEXT:    v_cndmask_b32_e32 v5, v5, v4, vcc
1577; SI-NEXT:    v_mov_b32_e32 v4, s12
1578; SI-NEXT:    v_cndmask_b32_e64 v4, v4, 0, vcc
1579; SI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
1580; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
1581; SI-NEXT:    s_endpgm
1582;
1583; VI-LABEL: dynamic_insertelement_v4f64:
1584; VI:       ; %bb.0:
1585; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
1586; VI-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x20
1587; VI-NEXT:    s_load_dword s4, s[4:5], 0x40
1588; VI-NEXT:    v_mov_b32_e32 v4, 0x40200000
1589; VI-NEXT:    s_mov_b32 s3, 0x1100f000
1590; VI-NEXT:    s_mov_b32 s2, -1
1591; VI-NEXT:    s_waitcnt lgkmcnt(0)
1592; VI-NEXT:    v_mov_b32_e32 v0, s11
1593; VI-NEXT:    v_cmp_eq_u32_e64 vcc, s4, 1
1594; VI-NEXT:    v_cndmask_b32_e32 v3, v0, v4, vcc
1595; VI-NEXT:    v_mov_b32_e32 v0, s10
1596; VI-NEXT:    v_cndmask_b32_e64 v2, v0, 0, vcc
1597; VI-NEXT:    v_mov_b32_e32 v0, s9
1598; VI-NEXT:    v_cmp_eq_u32_e64 vcc, s4, 0
1599; VI-NEXT:    v_cndmask_b32_e32 v1, v0, v4, vcc
1600; VI-NEXT:    v_mov_b32_e32 v0, s8
1601; VI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc
1602; VI-NEXT:    v_mov_b32_e32 v5, s15
1603; VI-NEXT:    v_cmp_eq_u32_e64 vcc, s4, 3
1604; VI-NEXT:    v_cndmask_b32_e32 v7, v5, v4, vcc
1605; VI-NEXT:    v_mov_b32_e32 v5, s14
1606; VI-NEXT:    v_cndmask_b32_e64 v6, v5, 0, vcc
1607; VI-NEXT:    v_mov_b32_e32 v5, s13
1608; VI-NEXT:    v_cmp_eq_u32_e64 vcc, s4, 2
1609; VI-NEXT:    v_cndmask_b32_e32 v5, v5, v4, vcc
1610; VI-NEXT:    v_mov_b32_e32 v4, s12
1611; VI-NEXT:    v_cndmask_b32_e64 v4, v4, 0, vcc
1612; VI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
1613; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
1614; VI-NEXT:    s_endpgm
1615  %vecins = insertelement <4 x double> %a, double 8.0, i32 %b
1616  store <4 x double> %vecins, <4 x double> addrspace(1)* %out, align 16
1617  ret void
1618}
1619
1620define amdgpu_kernel void @dynamic_insertelement_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %a, i32 %b) #0 {
1621; SI-LABEL: dynamic_insertelement_v8f64:
1622; SI:       ; %bb.0:
1623; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
1624; SI-NEXT:    s_load_dwordx16 s[8:23], s[4:5], 0x10
1625; SI-NEXT:    s_load_dword s4, s[4:5], 0x20
1626; SI-NEXT:    v_mov_b32_e32 v16, 0x40200000
1627; SI-NEXT:    s_mov_b32 s3, 0x100f000
1628; SI-NEXT:    s_mov_b32 s2, -1
1629; SI-NEXT:    s_waitcnt lgkmcnt(0)
1630; SI-NEXT:    v_mov_b32_e32 v0, s8
1631; SI-NEXT:    s_lshl_b32 s4, s4, 1
1632; SI-NEXT:    v_mov_b32_e32 v1, s9
1633; SI-NEXT:    v_mov_b32_e32 v2, s10
1634; SI-NEXT:    v_mov_b32_e32 v3, s11
1635; SI-NEXT:    v_mov_b32_e32 v4, s12
1636; SI-NEXT:    v_mov_b32_e32 v5, s13
1637; SI-NEXT:    v_mov_b32_e32 v6, s14
1638; SI-NEXT:    v_mov_b32_e32 v7, s15
1639; SI-NEXT:    v_mov_b32_e32 v8, s16
1640; SI-NEXT:    v_mov_b32_e32 v9, s17
1641; SI-NEXT:    v_mov_b32_e32 v10, s18
1642; SI-NEXT:    v_mov_b32_e32 v11, s19
1643; SI-NEXT:    v_mov_b32_e32 v12, s20
1644; SI-NEXT:    v_mov_b32_e32 v13, s21
1645; SI-NEXT:    v_mov_b32_e32 v14, s22
1646; SI-NEXT:    v_mov_b32_e32 v15, s23
1647; SI-NEXT:    s_mov_b32 m0, s4
1648; SI-NEXT:    v_movreld_b32_e32 v0, 0
1649; SI-NEXT:    v_movreld_b32_e32 v1, v16
1650; SI-NEXT:    buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48
1651; SI-NEXT:    buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32
1652; SI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
1653; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
1654; SI-NEXT:    s_endpgm
1655;
1656; VI-LABEL: dynamic_insertelement_v8f64:
1657; VI:       ; %bb.0:
1658; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
1659; VI-NEXT:    s_load_dwordx16 s[8:23], s[4:5], 0x40
1660; VI-NEXT:    s_load_dword s4, s[4:5], 0x80
1661; VI-NEXT:    v_mov_b32_e32 v16, 0x40200000
1662; VI-NEXT:    s_mov_b32 s3, 0x1100f000
1663; VI-NEXT:    s_mov_b32 s2, -1
1664; VI-NEXT:    s_waitcnt lgkmcnt(0)
1665; VI-NEXT:    v_mov_b32_e32 v0, s8
1666; VI-NEXT:    s_lshl_b32 s4, s4, 1
1667; VI-NEXT:    v_mov_b32_e32 v1, s9
1668; VI-NEXT:    v_mov_b32_e32 v2, s10
1669; VI-NEXT:    v_mov_b32_e32 v3, s11
1670; VI-NEXT:    v_mov_b32_e32 v4, s12
1671; VI-NEXT:    v_mov_b32_e32 v5, s13
1672; VI-NEXT:    v_mov_b32_e32 v6, s14
1673; VI-NEXT:    v_mov_b32_e32 v7, s15
1674; VI-NEXT:    v_mov_b32_e32 v8, s16
1675; VI-NEXT:    v_mov_b32_e32 v9, s17
1676; VI-NEXT:    v_mov_b32_e32 v10, s18
1677; VI-NEXT:    v_mov_b32_e32 v11, s19
1678; VI-NEXT:    v_mov_b32_e32 v12, s20
1679; VI-NEXT:    v_mov_b32_e32 v13, s21
1680; VI-NEXT:    v_mov_b32_e32 v14, s22
1681; VI-NEXT:    v_mov_b32_e32 v15, s23
1682; VI-NEXT:    s_mov_b32 m0, s4
1683; VI-NEXT:    v_movreld_b32_e32 v0, 0
1684; VI-NEXT:    v_movreld_b32_e32 v1, v16
1685; VI-NEXT:    buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48
1686; VI-NEXT:    buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32
1687; VI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
1688; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
1689; VI-NEXT:    s_endpgm
1690  %vecins = insertelement <8 x double> %a, double 8.0, i32 %b
1691  store <8 x double> %vecins, <8 x double> addrspace(1)* %out, align 16
1692  ret void
1693}
1694
1695declare <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
1696
1697attributes #0 = { nounwind }
1698attributes #1 = { nounwind readnone }
1699