1; RUN: llc -verify-machineinstrs -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -mattr=-flat-for-global,+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI,GCN-NO-TONGA %s 2; RUN: llc -verify-machineinstrs -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -mattr=-flat-for-global -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,GCN-TONGA %s 3 4; FIXME: Broken on evergreen 5; FIXME: For some reason the 8 and 16 vectors are being stored as 6; individual elements instead of 128-bit stores. 7 8 9; FIXME: Why is the constant moved into the intermediate register and 10; not just directly into the vector component? 11 12; GCN-LABEL: {{^}}insertelement_v4f32_0: 13; GCN: s_load_dwordx4 14; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 15; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 16; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 17; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 18; GCN-DAG: s_mov_b32 [[CONSTREG:s[0-9]+]], 0x40a00000 19; GCN-DAG: v_mov_b32_e32 v[[LOW_REG:[0-9]+]], [[CONSTREG]] 20; GCN: buffer_store_dwordx4 v{{\[}}[[LOW_REG]]: 21define amdgpu_kernel void @insertelement_v4f32_0(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind { 22 %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 0 23 store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16 24 ret void 25} 26 27; GCN-LABEL: {{^}}insertelement_v4f32_1: 28define amdgpu_kernel void @insertelement_v4f32_1(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind { 29 %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 1 30 store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16 31 ret void 32} 33 34; GCN-LABEL: {{^}}insertelement_v4f32_2: 35define amdgpu_kernel void @insertelement_v4f32_2(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind { 36 %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 2 37 store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16 38 ret void 39} 40 41; GCN-LABEL: {{^}}insertelement_v4f32_3: 42define amdgpu_kernel void @insertelement_v4f32_3(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind { 43 %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 3 44 store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16 45 ret void 46} 47 48; GCN-LABEL: {{^}}insertelement_v4i32_0: 49define amdgpu_kernel void @insertelement_v4i32_0(<4 x i32> addrspace(1)* %out, <4 x i32> %a) nounwind { 50 %vecins = insertelement <4 x i32> %a, i32 999, i32 0 51 store <4 x i32> %vecins, <4 x i32> addrspace(1)* %out, align 16 52 ret void 53} 54 55; GCN-LABEL: {{^}}insertelement_v3f32_1: 56define amdgpu_kernel void @insertelement_v3f32_1(<3 x float> addrspace(1)* %out, <3 x float> %a) nounwind { 57 %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 1 58 store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16 59 ret void 60} 61 62; GCN-LABEL: {{^}}insertelement_v3f32_2: 63define amdgpu_kernel void @insertelement_v3f32_2(<3 x float> addrspace(1)* %out, <3 x float> %a) nounwind { 64 %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 2 65 store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16 66 ret void 67} 68 69; GCN-LABEL: {{^}}insertelement_v3f32_3: 70define amdgpu_kernel void @insertelement_v3f32_3(<3 x float> addrspace(1)* %out, <3 x float> %a) nounwind { 71 %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 3 72 store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16 73 ret void 74} 75 76; GCN-LABEL: {{^}}insertelement_to_sgpr: 77; GCN-NOT: v_readfirstlane 78define <4 x float> @insertelement_to_sgpr() nounwind { 79 %tmp = load <4 x i32>, <4 x i32> addrspace(4)* undef 80 %tmp1 = insertelement <4 x i32> %tmp, i32 0, i32 0 81 %tmp2 = call <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f32(i32 1, float undef, float undef, <8 x i32> undef, <4 x i32> %tmp1, i1 0, i32 0, i32 0) 82 ret <4 x float> %tmp2 83} 84 85; GCN-LABEL: {{^}}dynamic_insertelement_v2f32: 86; GCN: v_mov_b32_e32 [[CONST:v[0-9]+]], 0x40a00000 87; GCN: v_movreld_b32_e32 v[[LOW_RESULT_REG:[0-9]+]], [[CONST]] 88; GCN: buffer_store_dwordx2 {{v\[}}[[LOW_RESULT_REG]]: 89define amdgpu_kernel void @dynamic_insertelement_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, i32 %b) nounwind { 90 %vecins = insertelement <2 x float> %a, float 5.000000e+00, i32 %b 91 store <2 x float> %vecins, <2 x float> addrspace(1)* %out, align 8 92 ret void 93} 94 95; GCN-LABEL: {{^}}dynamic_insertelement_v3f32: 96; GCN: v_mov_b32_e32 [[CONST:v[0-9]+]], 0x40a00000 97; GCN: v_movreld_b32_e32 v[[LOW_RESULT_REG:[0-9]+]], [[CONST]] 98; GCN-DAG: buffer_store_dwordx2 {{v\[}}[[LOW_RESULT_REG]]: 99; GCN-DAG: buffer_store_dword v 100define amdgpu_kernel void @dynamic_insertelement_v3f32(<3 x float> addrspace(1)* %out, <3 x float> %a, i32 %b) nounwind { 101 %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 %b 102 store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16 103 ret void 104} 105 106; GCN-LABEL: {{^}}dynamic_insertelement_v4f32: 107; GCN: v_mov_b32_e32 [[CONST:v[0-9]+]], 0x40a00000 108; GCN: v_movreld_b32_e32 v[[LOW_RESULT_REG:[0-9]+]], [[CONST]] 109; GCN: buffer_store_dwordx4 {{v\[}}[[LOW_RESULT_REG]]: 110define amdgpu_kernel void @dynamic_insertelement_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, i32 %b) nounwind { 111 %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 %b 112 store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16 113 ret void 114} 115 116; GCN-LABEL: {{^}}dynamic_insertelement_v8f32: 117; GCN: v_movreld_b32_e32 v{{[0-9]+}}, v{{[0-9]+}} 118; GCN: buffer_store_dwordx4 119; GCN: buffer_store_dwordx4 120define amdgpu_kernel void @dynamic_insertelement_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, i32 %b) nounwind { 121 %vecins = insertelement <8 x float> %a, float 5.000000e+00, i32 %b 122 store <8 x float> %vecins, <8 x float> addrspace(1)* %out, align 32 123 ret void 124} 125 126; GCN-LABEL: {{^}}dynamic_insertelement_v16f32: 127; GCN: v_movreld_b32_e32 v{{[0-9]+}}, v{{[0-9]+}} 128; GCN: buffer_store_dwordx4 129; GCN: buffer_store_dwordx4 130; GCN: buffer_store_dwordx4 131; GCN: buffer_store_dwordx4 132define amdgpu_kernel void @dynamic_insertelement_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %a, i32 %b) nounwind { 133 %vecins = insertelement <16 x float> %a, float 5.000000e+00, i32 %b 134 store <16 x float> %vecins, <16 x float> addrspace(1)* %out, align 64 135 ret void 136} 137 138; GCN-LABEL: {{^}}dynamic_insertelement_v2i32: 139; GCN: v_movreld_b32 140; GCN: buffer_store_dwordx2 141define amdgpu_kernel void @dynamic_insertelement_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, i32 %b) nounwind { 142 %vecins = insertelement <2 x i32> %a, i32 5, i32 %b 143 store <2 x i32> %vecins, <2 x i32> addrspace(1)* %out, align 8 144 ret void 145} 146 147; GCN-LABEL: {{^}}dynamic_insertelement_v3i32: 148; GCN: v_movreld_b32_e32 v[[LOW_RESULT_REG:[0-9]+]], 5 149; GCN-DAG: buffer_store_dwordx2 {{v\[}}[[LOW_RESULT_REG]]: 150; GCN-DAG: buffer_store_dword v 151define amdgpu_kernel void @dynamic_insertelement_v3i32(<3 x i32> addrspace(1)* %out, <3 x i32> %a, i32 %b) nounwind { 152 %vecins = insertelement <3 x i32> %a, i32 5, i32 %b 153 store <3 x i32> %vecins, <3 x i32> addrspace(1)* %out, align 16 154 ret void 155} 156 157; GCN-LABEL: {{^}}dynamic_insertelement_v4i32: 158; GCN: s_load_dword [[SVAL:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, {{0x11|0x44}} 159; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[SVAL]] 160; GCN: v_movreld_b32_e32 v{{[0-9]+}}, [[VVAL]] 161; GCN: buffer_store_dwordx4 162define amdgpu_kernel void @dynamic_insertelement_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, i32 %b, [8 x i32], i32 %val) nounwind { 163 %vecins = insertelement <4 x i32> %a, i32 %val, i32 %b 164 store <4 x i32> %vecins, <4 x i32> addrspace(1)* %out, align 16 165 ret void 166} 167 168; GCN-LABEL: {{^}}dynamic_insertelement_v8i32: 169; GCN: v_movreld_b32 170; GCN: buffer_store_dwordx4 171; GCN: buffer_store_dwordx4 172define amdgpu_kernel void @dynamic_insertelement_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> %a, i32 %b) nounwind { 173 %vecins = insertelement <8 x i32> %a, i32 5, i32 %b 174 store <8 x i32> %vecins, <8 x i32> addrspace(1)* %out, align 32 175 ret void 176} 177 178; GCN-LABEL: {{^}}dynamic_insertelement_v16i32: 179; GCN: v_movreld_b32 180; GCN: buffer_store_dwordx4 181; GCN: buffer_store_dwordx4 182; GCN: buffer_store_dwordx4 183; GCN: buffer_store_dwordx4 184define amdgpu_kernel void @dynamic_insertelement_v16i32(<16 x i32> addrspace(1)* %out, <16 x i32> %a, i32 %b) nounwind { 185 %vecins = insertelement <16 x i32> %a, i32 5, i32 %b 186 store <16 x i32> %vecins, <16 x i32> addrspace(1)* %out, align 64 187 ret void 188} 189 190; GCN-LABEL: {{^}}dynamic_insertelement_v2i16: 191define amdgpu_kernel void @dynamic_insertelement_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %a, i32 %b) nounwind { 192 %vecins = insertelement <2 x i16> %a, i16 5, i32 %b 193 store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out, align 8 194 ret void 195} 196 197; GCN-LABEL: {{^}}dynamic_insertelement_v3i16: 198define amdgpu_kernel void @dynamic_insertelement_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %a, i32 %b) nounwind { 199 %vecins = insertelement <3 x i16> %a, i16 5, i32 %b 200 store <3 x i16> %vecins, <3 x i16> addrspace(1)* %out, align 8 201 ret void 202} 203 204; GCN-LABEL: {{^}}dynamic_insertelement_v2i8: 205; VI: s_load_dword [[LOAD:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x28 206; VI-NEXT: s_load_dword [[IDX:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x4c 207; VI-NOT: _load 208; VI: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 3 209; VI: v_lshlrev_b16_e64 [[MASK:v[0-9]+]], [[SCALED_IDX]], -1 210; VI: v_and_b32_e32 [[INSERT:v[0-9]+]], 5, [[MASK]] 211; VI: v_xor_b32_e32 [[NOT_MASK:v[0-9]+]], -1, [[MASK]] 212; VI: v_and_b32_e32 [[AND_NOT_MASK:v[0-9]+]], [[LOAD]], [[NOT_MASK]] 213; VI: v_or_b32_e32 [[OR:v[0-9]+]], [[INSERT]], [[AND_NOT_MASK]] 214; VI: buffer_store_short [[OR]] 215define amdgpu_kernel void @dynamic_insertelement_v2i8(<2 x i8> addrspace(1)* %out, [8 x i32], <2 x i8> %a, [8 x i32], i32 %b) nounwind { 216 %vecins = insertelement <2 x i8> %a, i8 5, i32 %b 217 store <2 x i8> %vecins, <2 x i8> addrspace(1)* %out, align 8 218 ret void 219} 220 221; FIXME: post legalize i16 and i32 shifts aren't merged because of 222; isTypeDesirableForOp in SimplifyDemandedBits 223 224; GCN-LABEL: {{^}}dynamic_insertelement_v3i8: 225; VI: s_load_dword [[LOAD:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x28 226; VI-NEXT: s_load_dword [[IDX:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x4c 227; VI-NOT: _load 228 229; VI: v_mov_b32_e32 [[V_LOAD:v[0-9]+]], [[LOAD]] 230; VI: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 3 231; VI: s_lshl_b32 [[SHIFTED_MASK:s[0-9]+]], 0xffff, [[SCALED_IDX]] 232; VI: s_not_b32 [[NOT_MASK:s[0-9]+]], [[SHIFTED_MASK]] 233; VI: s_and_b32 [[AND_NOT_MASK:s[0-9]+]], [[NOT_MASK]], [[LOAD]] 234; VI: v_bfi_b32 [[BFI:v[0-9]+]], [[SHIFTED_MASK]], 5, [[V_LOAD]] 235; VI: s_lshr_b32 [[HI2:s[0-9]+]], [[AND_NOT_MASK]], 16 236 237; VI-DAG: buffer_store_short [[BFI]] 238; VI-DAG: v_mov_b32_e32 [[V_HI2:v[0-9]+]], [[HI2]] 239; VI: buffer_store_byte [[V_HI2]] 240define amdgpu_kernel void @dynamic_insertelement_v3i8(<3 x i8> addrspace(1)* %out, [8 x i32], <3 x i8> %a, [8 x i32], i32 %b) nounwind { 241 %vecins = insertelement <3 x i8> %a, i8 5, i32 %b 242 store <3 x i8> %vecins, <3 x i8> addrspace(1)* %out, align 4 243 ret void 244} 245 246; GCN-LABEL: {{^}}dynamic_insertelement_v4i8: 247; VI: s_load_dword [[LOAD:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x28 248; VI-NEXT: s_load_dword [[IDX:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x4c 249; VI-NOT: _load 250 251; VI: v_mov_b32_e32 [[V_LOAD:v[0-9]+]], [[LOAD]] 252; VI-DAG: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 3 253; VI: s_lshl_b32 [[SHIFTED_MASK:s[0-9]+]], 0xffff, [[SCALED_IDX]] 254; VI: v_bfi_b32 [[BFI:v[0-9]+]], [[SHIFTED_MASK]], 5, [[V_LOAD]] 255; VI: buffer_store_dword [[BFI]] 256define amdgpu_kernel void @dynamic_insertelement_v4i8(<4 x i8> addrspace(1)* %out, [8 x i32], <4 x i8> %a, [8 x i32], i32 %b) nounwind { 257 %vecins = insertelement <4 x i8> %a, i8 5, i32 %b 258 store <4 x i8> %vecins, <4 x i8> addrspace(1)* %out, align 4 259 ret void 260} 261 262; GCN-LABEL: {{^}}s_dynamic_insertelement_v8i8: 263; VI-NOT: {{buffer|flat|global}}_load 264; VI-DAG: s_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x0 265; VI-DAG: s_load_dword [[IDX:s[0-9]]], s[4:5], 0x10 266; VI-DAG: s_mov_b32 s[[MASK_HI:[0-9]+]], 0{{$}} 267; VI-DAG: s_load_dwordx2 [[VEC:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0x0 268 269; VI-DAG: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 3 270; VI-DAG: s_mov_b32 s[[MASK_LO:[0-9]+]], 0xffff 271; VI: s_lshl_b64 s{{\[}}[[MASK_SHIFT_LO:[0-9]+]]:[[MASK_SHIFT_HI:[0-9]+]]{{\]}}, s{{\[}}[[MASK_LO]]:[[MASK_HI]]{{\]}}, [[SCALED_IDX]] 272; VI: s_not_b64 [[NOT_MASK:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[MASK_SHIFT_LO]]:[[MASK_SHIFT_HI]]{{\]}} 273; VI: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], [[NOT_MASK]], [[VEC]] 274; VI: s_and_b32 s[[INS:[0-9]+]], s[[MASK_SHIFT_LO]], 5 275; VI: s_or_b64 s{{\[}}[[RESULT0:[0-9]+]]:[[RESULT1:[0-9]+]]{{\]}}, s{{\[}}[[INS]]:[[MASK_HI]]{{\]}}, [[AND]] 276; VI: v_mov_b32_e32 v[[V_RESULT0:[0-9]+]], s[[RESULT0]] 277; VI: v_mov_b32_e32 v[[V_RESULT1:[0-9]+]], s[[RESULT1]] 278; VI: buffer_store_dwordx2 v{{\[}}[[V_RESULT0]]:[[V_RESULT1]]{{\]}} 279define amdgpu_kernel void @s_dynamic_insertelement_v8i8(<8 x i8> addrspace(1)* %out, <8 x i8> addrspace(4)* %a.ptr, i32 %b) nounwind { 280 %a = load <8 x i8>, <8 x i8> addrspace(4)* %a.ptr, align 4 281 %vecins = insertelement <8 x i8> %a, i8 5, i32 %b 282 store <8 x i8> %vecins, <8 x i8> addrspace(1)* %out, align 8 283 ret void 284} 285 286; GCN-LABEL: {{^}}dynamic_insertelement_v16i8: 287; GCN: s_load_dwordx2 288; GCN: s_load_dwordx4 289; GCN: s_load_dword s 290 291; GCN: buffer_store_byte 292; GCN: buffer_store_byte 293; GCN: buffer_store_byte 294; GCN: buffer_store_byte 295; GCN: buffer_store_byte 296; GCN: buffer_store_byte 297; GCN: buffer_store_byte 298; GCN: buffer_store_byte 299; GCN: buffer_store_byte 300; GCN: buffer_store_byte 301; GCN: buffer_store_byte 302; GCN: buffer_store_byte 303; GCN: buffer_store_byte 304; GCN: buffer_store_byte 305; GCN: buffer_store_byte 306; GCN: buffer_store_byte 307 308; GCN: buffer_store_byte 309; GCN: buffer_store_dwordx4 310define amdgpu_kernel void @dynamic_insertelement_v16i8(<16 x i8> addrspace(1)* %out, <16 x i8> %a, i32 %b) nounwind { 311 %vecins = insertelement <16 x i8> %a, i8 5, i32 %b 312 store <16 x i8> %vecins, <16 x i8> addrspace(1)* %out, align 16 313 ret void 314} 315 316; This test requires handling INSERT_SUBREG in SIFixSGPRCopies. Check that 317; the compiler doesn't crash. 318; GCN-LABEL: {{^}}insert_split_bb: 319define amdgpu_kernel void @insert_split_bb(<2 x i32> addrspace(1)* %out, i32 addrspace(1)* %in, i32 %a, i32 %b) { 320entry: 321 %0 = insertelement <2 x i32> undef, i32 %a, i32 0 322 %1 = icmp eq i32 %a, 0 323 br i1 %1, label %if, label %else 324 325if: 326 %2 = load i32, i32 addrspace(1)* %in 327 %3 = insertelement <2 x i32> %0, i32 %2, i32 1 328 br label %endif 329 330else: 331 %4 = getelementptr i32, i32 addrspace(1)* %in, i32 1 332 %5 = load i32, i32 addrspace(1)* %4 333 %6 = insertelement <2 x i32> %0, i32 %5, i32 1 334 br label %endif 335 336endif: 337 %7 = phi <2 x i32> [%3, %if], [%6, %else] 338 store <2 x i32> %7, <2 x i32> addrspace(1)* %out 339 ret void 340} 341 342; GCN-LABEL: {{^}}dynamic_insertelement_v2f64: 343; GCN-DAG: s_load_dwordx4 s{{\[}}[[A_ELT0:[0-9]+]]:[[A_ELT3:[0-9]+]]{{\]}} 344; GCN-DAG: s_load_dword [[IDX:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, {{0x18|0x60}}{{$}} 345 346; GCN-DAG: s_lshl_b32 [[SCALEDIDX:s[0-9]+]], [[IDX]], 1{{$}} 347 348; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 349; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 350; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 351; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 352; GCN-DAG: v_mov_b32_e32 [[ELT1:v[0-9]+]], 0x40200000 353 354; GCN-DAG: s_mov_b32 m0, [[SCALEDIDX]] 355; GCN-DAG: v_movreld_b32_e32 v{{[0-9]+}}, 0 356 357; Increment to next element folded into base register, but FileCheck 358; can't do math expressions 359 360; FIXME: Should be able to manipulate m0 directly instead of s_lshl_b32 + copy to m0 361 362; GCN: v_movreld_b32_e32 v{{[0-9]+}}, [[ELT1]] 363 364; GCN: buffer_store_dwordx4 365; GCN: s_endpgm 366define amdgpu_kernel void @dynamic_insertelement_v2f64(<2 x double> addrspace(1)* %out, [8 x i32], <2 x double> %a, [8 x i32], i32 %b) nounwind { 367 %vecins = insertelement <2 x double> %a, double 8.0, i32 %b 368 store <2 x double> %vecins, <2 x double> addrspace(1)* %out, align 16 369 ret void 370} 371 372; GCN-LABEL: {{^}}dynamic_insertelement_v2i64: 373 374; GCN-DAG: v_movreld_b32_e32 v{{[0-9]+}}, 5 375; GCN-DAG: v_movreld_b32_e32 v{{[0-9]+}}, 0 376 377; GCN: buffer_store_dwordx4 378; GCN: s_endpgm 379define amdgpu_kernel void @dynamic_insertelement_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %a, i32 %b) nounwind { 380 %vecins = insertelement <2 x i64> %a, i64 5, i32 %b 381 store <2 x i64> %vecins, <2 x i64> addrspace(1)* %out, align 8 382 ret void 383} 384 385; GCN-LABEL: {{^}}dynamic_insertelement_v3i64: 386define amdgpu_kernel void @dynamic_insertelement_v3i64(<3 x i64> addrspace(1)* %out, <3 x i64> %a, i32 %b) nounwind { 387 %vecins = insertelement <3 x i64> %a, i64 5, i32 %b 388 store <3 x i64> %vecins, <3 x i64> addrspace(1)* %out, align 32 389 ret void 390} 391 392; FIXME: Should be able to do without stack access. The used stack 393; space is also 2x what should be required. 394 395; GCN-LABEL: {{^}}dynamic_insertelement_v4f64: 396 397; Stack store 398 399; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s[0:3], {{s[0-9]+}} offset:32{{$}} 400; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s[0:3], {{s[0-9]+}} offset:48{{$}} 401 402; Write element 403; GCN: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], {{s[0-9]+}} offen{{$}} 404 405; Stack reload 406; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s[0:3], {{s[0-9]+}} offset:32{{$}} 407; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s[0:3], {{s[0-9]+}} offset:48{{$}} 408 409; Store result 410; GCN: buffer_store_dwordx4 411; GCN: buffer_store_dwordx4 412; GCN: s_endpgm 413; GCN: ScratchSize: 64 414 415define amdgpu_kernel void @dynamic_insertelement_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %a, i32 %b) nounwind { 416 %vecins = insertelement <4 x double> %a, double 8.0, i32 %b 417 store <4 x double> %vecins, <4 x double> addrspace(1)* %out, align 16 418 ret void 419} 420 421; GCN-LABEL: {{^}}dynamic_insertelement_v8f64: 422; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s[0:3], {{s[0-9]+}} offset:64{{$}} 423; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s[0:3], {{s[0-9]+}} offset:80{{$}} 424; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s[0:3], {{s[0-9]+}} offset:96{{$}} 425; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s[0:3], {{s[0-9]+}} offset:112{{$}} 426 427; GCN: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], {{s[0-9]+}} offen{{$}} 428 429; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s[0:3], {{s[0-9]+}} offset:64{{$}} 430; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s[0:3], {{s[0-9]+}} offset:80{{$}} 431; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s[0:3], {{s[0-9]+}} offset:96{{$}} 432; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s[0:3], {{s[0-9]+}} offset:112{{$}} 433 434; GCN: buffer_store_dwordx4 435; GCN: buffer_store_dwordx4 436; GCN: buffer_store_dwordx4 437; GCN: buffer_store_dwordx4 438; GCN: s_endpgm 439; GCN: ScratchSize: 128 440define amdgpu_kernel void @dynamic_insertelement_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %a, i32 %b) #0 { 441 %vecins = insertelement <8 x double> %a, double 8.0, i32 %b 442 store <8 x double> %vecins, <8 x double> addrspace(1)* %out, align 16 443 ret void 444} 445 446declare <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 447 448attributes #0 = { nounwind } 449attributes #1 = { nounwind readnone } 450