1; RUN: llc -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI,GCN-NO-TONGA %s 2; RUN: llc -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,GCN-TONGA %s 3 4; FIXME: Broken on evergreen 5; FIXME: For some reason the 8 and 16 vectors are being stored as 6; individual elements instead of 128-bit stores. 7 8 9; FIXME: Why is the constant moved into the intermediate register and 10; not just directly into the vector component? 11 12; GCN-LABEL: {{^}}insertelement_v4f32_0: 13; GCN: s_load_dwordx4 14; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 15; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 16; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 17; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 18; GCN-DAG: s_mov_b32 [[CONSTREG:s[0-9]+]], 0x40a00000 19; GCN-DAG: v_mov_b32_e32 v[[LOW_REG:[0-9]+]], [[CONSTREG]] 20; GCN: buffer_store_dwordx4 v{{\[}}[[LOW_REG]]: 21define amdgpu_kernel void @insertelement_v4f32_0(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind { 22 %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 0 23 store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16 24 ret void 25} 26 27; GCN-LABEL: {{^}}insertelement_v4f32_1: 28define amdgpu_kernel void @insertelement_v4f32_1(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind { 29 %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 1 30 store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16 31 ret void 32} 33 34; GCN-LABEL: {{^}}insertelement_v4f32_2: 35define amdgpu_kernel void @insertelement_v4f32_2(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind { 36 %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 2 37 store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16 38 ret void 39} 40 41; GCN-LABEL: {{^}}insertelement_v4f32_3: 42define amdgpu_kernel void @insertelement_v4f32_3(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind { 43 %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 3 44 store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16 45 ret void 46} 47 48; GCN-LABEL: {{^}}insertelement_v4i32_0: 49define amdgpu_kernel void @insertelement_v4i32_0(<4 x i32> addrspace(1)* %out, <4 x i32> %a) nounwind { 50 %vecins = insertelement <4 x i32> %a, i32 999, i32 0 51 store <4 x i32> %vecins, <4 x i32> addrspace(1)* %out, align 16 52 ret void 53} 54 55; GCN-LABEL: {{^}}insertelement_v3f32_1: 56define amdgpu_kernel void @insertelement_v3f32_1(<3 x float> addrspace(1)* %out, <3 x float> %a) nounwind { 57 %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 1 58 store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16 59 ret void 60} 61 62; GCN-LABEL: {{^}}insertelement_v3f32_2: 63define amdgpu_kernel void @insertelement_v3f32_2(<3 x float> addrspace(1)* %out, <3 x float> %a) nounwind { 64 %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 2 65 store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16 66 ret void 67} 68 69; GCN-LABEL: {{^}}insertelement_v3f32_3: 70define amdgpu_kernel void @insertelement_v3f32_3(<3 x float> addrspace(1)* %out, <3 x float> %a) nounwind { 71 %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 3 72 store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16 73 ret void 74} 75 76; GCN-LABEL: {{^}}insertelement_to_sgpr: 77; GCN-NOT: v_readfirstlane 78define amdgpu_ps <4 x float> @insertelement_to_sgpr() nounwind { 79 %tmp = load <4 x i32>, <4 x i32> addrspace(2)* undef 80 %tmp1 = insertelement <4 x i32> %tmp, i32 0, i32 0 81 %tmp2 = call <4 x float> @llvm.amdgcn.image.gather4.lz.v4f32.v2f32.v8i32(<2 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 false, i1 false, i1 false, i1 false, i1 true) 82 ret <4 x float> %tmp2 83} 84 85; GCN-LABEL: {{^}}dynamic_insertelement_v2f32: 86; GCN: v_mov_b32_e32 [[CONST:v[0-9]+]], 0x40a00000 87; GCN: v_movreld_b32_e32 v[[LOW_RESULT_REG:[0-9]+]], [[CONST]] 88; GCN: buffer_store_dwordx2 {{v\[}}[[LOW_RESULT_REG]]: 89define amdgpu_kernel void @dynamic_insertelement_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, i32 %b) nounwind { 90 %vecins = insertelement <2 x float> %a, float 5.000000e+00, i32 %b 91 store <2 x float> %vecins, <2 x float> addrspace(1)* %out, align 8 92 ret void 93} 94 95; GCN-LABEL: {{^}}dynamic_insertelement_v3f32: 96; GCN: v_mov_b32_e32 [[CONST:v[0-9]+]], 0x40a00000 97; GCN: v_movreld_b32_e32 v[[LOW_RESULT_REG:[0-9]+]], [[CONST]] 98; GCN-DAG: buffer_store_dwordx2 {{v\[}}[[LOW_RESULT_REG]]: 99; GCN-DAG: buffer_store_dword v 100define amdgpu_kernel void @dynamic_insertelement_v3f32(<3 x float> addrspace(1)* %out, <3 x float> %a, i32 %b) nounwind { 101 %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 %b 102 store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16 103 ret void 104} 105 106; GCN-LABEL: {{^}}dynamic_insertelement_v4f32: 107; GCN: v_mov_b32_e32 [[CONST:v[0-9]+]], 0x40a00000 108; GCN: v_movreld_b32_e32 v[[LOW_RESULT_REG:[0-9]+]], [[CONST]] 109; GCN: buffer_store_dwordx4 {{v\[}}[[LOW_RESULT_REG]]: 110define amdgpu_kernel void @dynamic_insertelement_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, i32 %b) nounwind { 111 %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 %b 112 store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16 113 ret void 114} 115 116; GCN-LABEL: {{^}}dynamic_insertelement_v8f32: 117; GCN: v_movreld_b32_e32 v{{[0-9]+}}, v{{[0-9]+}} 118; GCN: buffer_store_dwordx4 119; GCN: buffer_store_dwordx4 120define amdgpu_kernel void @dynamic_insertelement_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, i32 %b) nounwind { 121 %vecins = insertelement <8 x float> %a, float 5.000000e+00, i32 %b 122 store <8 x float> %vecins, <8 x float> addrspace(1)* %out, align 32 123 ret void 124} 125 126; GCN-LABEL: {{^}}dynamic_insertelement_v16f32: 127; GCN: v_movreld_b32_e32 v{{[0-9]+}}, v{{[0-9]+}} 128; GCN: buffer_store_dwordx4 129; GCN: buffer_store_dwordx4 130; GCN: buffer_store_dwordx4 131; GCN: buffer_store_dwordx4 132define amdgpu_kernel void @dynamic_insertelement_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %a, i32 %b) nounwind { 133 %vecins = insertelement <16 x float> %a, float 5.000000e+00, i32 %b 134 store <16 x float> %vecins, <16 x float> addrspace(1)* %out, align 64 135 ret void 136} 137 138; GCN-LABEL: {{^}}dynamic_insertelement_v2i32: 139; GCN: v_movreld_b32 140; GCN: buffer_store_dwordx2 141define amdgpu_kernel void @dynamic_insertelement_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, i32 %b) nounwind { 142 %vecins = insertelement <2 x i32> %a, i32 5, i32 %b 143 store <2 x i32> %vecins, <2 x i32> addrspace(1)* %out, align 8 144 ret void 145} 146 147; GCN-LABEL: {{^}}dynamic_insertelement_v3i32: 148; GCN: v_movreld_b32_e32 v[[LOW_RESULT_REG:[0-9]+]], 5 149; GCN-DAG: buffer_store_dwordx2 {{v\[}}[[LOW_RESULT_REG]]: 150; GCN-DAG: buffer_store_dword v 151define amdgpu_kernel void @dynamic_insertelement_v3i32(<3 x i32> addrspace(1)* %out, <3 x i32> %a, i32 %b) nounwind { 152 %vecins = insertelement <3 x i32> %a, i32 5, i32 %b 153 store <3 x i32> %vecins, <3 x i32> addrspace(1)* %out, align 16 154 ret void 155} 156 157; GCN-LABEL: {{^}}dynamic_insertelement_v4i32: 158; GCN: s_load_dword [[SVAL:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, {{0x12|0x48}} 159; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[SVAL]] 160; GCN: v_movreld_b32_e32 v{{[0-9]+}}, [[VVAL]] 161; GCN: buffer_store_dwordx4 162define amdgpu_kernel void @dynamic_insertelement_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, i32 %b, i32 %val) nounwind { 163 %vecins = insertelement <4 x i32> %a, i32 %val, i32 %b 164 store <4 x i32> %vecins, <4 x i32> addrspace(1)* %out, align 16 165 ret void 166} 167 168; GCN-LABEL: {{^}}dynamic_insertelement_v8i32: 169; GCN: v_movreld_b32 170; GCN: buffer_store_dwordx4 171; GCN: buffer_store_dwordx4 172define amdgpu_kernel void @dynamic_insertelement_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> %a, i32 %b) nounwind { 173 %vecins = insertelement <8 x i32> %a, i32 5, i32 %b 174 store <8 x i32> %vecins, <8 x i32> addrspace(1)* %out, align 32 175 ret void 176} 177 178; GCN-LABEL: {{^}}dynamic_insertelement_v16i32: 179; GCN: v_movreld_b32 180; GCN: buffer_store_dwordx4 181; GCN: buffer_store_dwordx4 182; GCN: buffer_store_dwordx4 183; GCN: buffer_store_dwordx4 184define amdgpu_kernel void @dynamic_insertelement_v16i32(<16 x i32> addrspace(1)* %out, <16 x i32> %a, i32 %b) nounwind { 185 %vecins = insertelement <16 x i32> %a, i32 5, i32 %b 186 store <16 x i32> %vecins, <16 x i32> addrspace(1)* %out, align 64 187 ret void 188} 189 190; GCN-LABEL: {{^}}dynamic_insertelement_v2i16: 191define amdgpu_kernel void @dynamic_insertelement_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %a, i32 %b) nounwind { 192 %vecins = insertelement <2 x i16> %a, i16 5, i32 %b 193 store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out, align 8 194 ret void 195} 196 197; GCN-LABEL: {{^}}dynamic_insertelement_v3i16: 198define amdgpu_kernel void @dynamic_insertelement_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %a, i32 %b) nounwind { 199 %vecins = insertelement <3 x i16> %a, i16 5, i32 %b 200 store <3 x i16> %vecins, <3 x i16> addrspace(1)* %out, align 8 201 ret void 202} 203 204; GCN-LABEL: {{^}}dynamic_insertelement_v2i8: 205; VI: buffer_load_ushort [[LOAD:v[0-9]]] 206; VI: s_load_dword [[IDX:s[0-9]]] 207; VI: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 3 208; VI: v_lshlrev_b16_e64 [[SHL:v[0-9]+]], [[SCALED_IDX]], -1 209; VI: v_xor_b32_e32 [[NOT:v[0-9]+]], -1, [[SHL]] 210; VI: v_and_b32_e32 [[AND0:v[0-9]+]], 5, [[SHL]] 211; VI: v_and_b32_e32 [[AND1:v[0-9]+]], [[NOT]], [[LOAD]] 212; VI: v_or_b32_e32 [[OR:v[0-9]+]], [[AND0]], [[AND1]] 213; VI: buffer_store_short [[OR]] 214define amdgpu_kernel void @dynamic_insertelement_v2i8(<2 x i8> addrspace(1)* %out, <2 x i8> %a, i32 %b) nounwind { 215 %vecins = insertelement <2 x i8> %a, i8 5, i32 %b 216 store <2 x i8> %vecins, <2 x i8> addrspace(1)* %out, align 8 217 ret void 218} 219 220; GCN-LABEL: {{^}}dynamic_insertelement_v3i8: 221; VI: buffer_load_ubyte 222; VI: buffer_load_ushort 223; VI: s_lshl_b32 s{{[0-9]+}}, s{{[0-9]+}}, 3 224; VI: s_lshl_b32 s{{[0-9]+}}, 0xffff, 225; VI: s_not_b32 226; VI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}} 227; VI: v_or_b32_e32 228; VI: v_and_b32 229; VI: v_bfi_b32 230; VI: v_lshrrev_b32 231define amdgpu_kernel void @dynamic_insertelement_v3i8(<3 x i8> addrspace(1)* %out, <3 x i8> %a, i32 %b) nounwind { 232 %vecins = insertelement <3 x i8> %a, i8 5, i32 %b 233 store <3 x i8> %vecins, <3 x i8> addrspace(1)* %out, align 4 234 ret void 235} 236 237; GCN-LABEL: {{^}}dynamic_insertelement_v4i8: 238; VI: s_load_dword [[VEC:s[0-9]+]] 239; VI: s_load_dword [[IDX:s[0-9]]] 240; VI-DAG: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 3 241; VI-DAG: s_lshl_b32 [[MASK:s[0-9]+]], 0xffff, [[SCALED_IDX]] 242; VI-DAG: v_mov_b32_e32 [[V_VEC:v[0-9]+]], [[VEC]] 243; VI: v_bfi_b32 [[BFI:v[0-9]+]], [[MASK]], 5, [[V_VEC]] 244define amdgpu_kernel void @dynamic_insertelement_v4i8(<4 x i8> addrspace(1)* %out, <4 x i8> %a, i32 %b) nounwind { 245 %vecins = insertelement <4 x i8> %a, i8 5, i32 %b 246 store <4 x i8> %vecins, <4 x i8> addrspace(1)* %out, align 4 247 ret void 248} 249 250; GCN-LABEL: {{^}}dynamic_insertelement_v8i8: 251; VI: s_load_dwordx2 [[VEC:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c 252; VI: s_load_dword [[IDX:s[0-9]]] 253; VI-DAG: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 3 254; VI-DAG: s_mov_b32 s[[MASK_HI:[0-9]+]], 0 255; VI-DAG: s_mov_b32 s[[MASK_LO:[0-9]+]], 0xffff 256; VI: s_lshl_b64 s{{\[}}[[MASK_SHIFT_LO:[0-9]+]]:[[MASK_SHIFT_HI:[0-9]+]]{{\]}}, s{{\[}}[[MASK_LO]]:[[MASK_HI]]{{\]}}, [[SCALED_IDX]] 257; VI: s_not_b64 [[NOT_MASK:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[MASK_SHIFT_LO]]:[[MASK_SHIFT_HI]]{{\]}} 258; VI: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], [[NOT_MASK]], [[VEC]] 259; VI: s_and_b32 s[[INS:[0-9]+]], s[[MASK_SHIFT_LO]], 5 260; VI: s_or_b64 s{{\[}}[[RESULT0:[0-9]+]]:[[RESULT1:[0-9]+]]{{\]}}, s{{\[}}[[INS]]:[[MASK_HI]]{{\]}}, [[AND]] 261; VI: v_mov_b32_e32 v[[V_RESULT0:[0-9]+]], s[[RESULT0]] 262; VI: v_mov_b32_e32 v[[V_RESULT1:[0-9]+]], s[[RESULT1]] 263; VI: buffer_store_dwordx2 v{{\[}}[[V_RESULT0]]:[[V_RESULT1]]{{\]}} 264define amdgpu_kernel void @dynamic_insertelement_v8i8(<8 x i8> addrspace(1)* %out, <8 x i8> %a, i32 %b) nounwind { 265 %vecins = insertelement <8 x i8> %a, i8 5, i32 %b 266 store <8 x i8> %vecins, <8 x i8> addrspace(1)* %out, align 8 267 ret void 268} 269 270; GCN-LABEL: {{^}}dynamic_insertelement_v16i8: 271; GCN: buffer_load_ubyte 272; GCN: buffer_load_ubyte 273; GCN: buffer_load_ubyte 274; GCN: buffer_load_ubyte 275; GCN: buffer_load_ubyte 276; GCN: buffer_load_ubyte 277; GCN: buffer_load_ubyte 278; GCN: buffer_load_ubyte 279; GCN: buffer_load_ubyte 280; GCN: buffer_load_ubyte 281; GCN: buffer_load_ubyte 282; GCN: buffer_load_ubyte 283; GCN: buffer_load_ubyte 284; GCN: buffer_load_ubyte 285; GCN: buffer_load_ubyte 286; GCN: buffer_load_ubyte 287 288; GCN: buffer_store_byte 289; GCN: buffer_store_byte 290; GCN: buffer_store_byte 291; GCN: buffer_store_byte 292; GCN: buffer_store_byte 293; GCN: buffer_store_byte 294; GCN: buffer_store_byte 295; GCN: buffer_store_byte 296; GCN: buffer_store_byte 297; GCN: buffer_store_byte 298; GCN: buffer_store_byte 299; GCN: buffer_store_byte 300; GCN: buffer_store_byte 301; GCN: buffer_store_byte 302; GCN: buffer_store_byte 303; GCN: buffer_store_byte 304 305; GCN: buffer_store_byte 306; GCN: buffer_store_dwordx4 307define amdgpu_kernel void @dynamic_insertelement_v16i8(<16 x i8> addrspace(1)* %out, <16 x i8> %a, i32 %b) nounwind { 308 %vecins = insertelement <16 x i8> %a, i8 5, i32 %b 309 store <16 x i8> %vecins, <16 x i8> addrspace(1)* %out, align 16 310 ret void 311} 312 313; This test requires handling INSERT_SUBREG in SIFixSGPRCopies. Check that 314; the compiler doesn't crash. 315; GCN-LABEL: {{^}}insert_split_bb: 316define amdgpu_kernel void @insert_split_bb(<2 x i32> addrspace(1)* %out, i32 addrspace(1)* %in, i32 %a, i32 %b) { 317entry: 318 %0 = insertelement <2 x i32> undef, i32 %a, i32 0 319 %1 = icmp eq i32 %a, 0 320 br i1 %1, label %if, label %else 321 322if: 323 %2 = load i32, i32 addrspace(1)* %in 324 %3 = insertelement <2 x i32> %0, i32 %2, i32 1 325 br label %endif 326 327else: 328 %4 = getelementptr i32, i32 addrspace(1)* %in, i32 1 329 %5 = load i32, i32 addrspace(1)* %4 330 %6 = insertelement <2 x i32> %0, i32 %5, i32 1 331 br label %endif 332 333endif: 334 %7 = phi <2 x i32> [%3, %if], [%6, %else] 335 store <2 x i32> %7, <2 x i32> addrspace(1)* %out 336 ret void 337} 338 339; GCN-LABEL: {{^}}dynamic_insertelement_v2f64: 340; GCN-DAG: s_load_dwordx4 s{{\[}}[[A_ELT0:[0-9]+]]:[[A_ELT3:[0-9]+]]{{\]}} 341; GCN-DAG: s_load_dword [[IDX:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, {{0x11|0x44}}{{$}} 342 343; GCN-DAG: s_lshl_b32 [[SCALEDIDX:s[0-9]+]], [[IDX]], 1{{$}} 344 345; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 346; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 347; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 348; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 349; GCN-DAG: v_mov_b32_e32 [[ELT1:v[0-9]+]], 0x40200000 350 351; GCN-DAG: s_mov_b32 m0, [[SCALEDIDX]] 352; GCN: v_movreld_b32_e32 v{{[0-9]+}}, 0 353 354; Increment to next element folded into base register, but FileCheck 355; can't do math expressions 356 357; FIXME: Should be able to manipulate m0 directly instead of s_lshl_b32 + copy to m0 358 359; GCN: v_movreld_b32_e32 v{{[0-9]+}}, [[ELT1]] 360 361; GCN: buffer_store_dwordx4 362; GCN: s_endpgm 363define amdgpu_kernel void @dynamic_insertelement_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %a, i32 %b) nounwind { 364 %vecins = insertelement <2 x double> %a, double 8.0, i32 %b 365 store <2 x double> %vecins, <2 x double> addrspace(1)* %out, align 16 366 ret void 367} 368 369; GCN-LABEL: {{^}}dynamic_insertelement_v2i64: 370 371; GCN-DAG: v_movreld_b32_e32 v{{[0-9]+}}, 5 372; GCN-DAG: v_movreld_b32_e32 v{{[0-9]+}}, 0 373 374; GCN: buffer_store_dwordx4 375; GCN: s_endpgm 376define amdgpu_kernel void @dynamic_insertelement_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %a, i32 %b) nounwind { 377 %vecins = insertelement <2 x i64> %a, i64 5, i32 %b 378 store <2 x i64> %vecins, <2 x i64> addrspace(1)* %out, align 8 379 ret void 380} 381 382; GCN-LABEL: {{^}}dynamic_insertelement_v3i64: 383define amdgpu_kernel void @dynamic_insertelement_v3i64(<3 x i64> addrspace(1)* %out, <3 x i64> %a, i32 %b) nounwind { 384 %vecins = insertelement <3 x i64> %a, i64 5, i32 %b 385 store <3 x i64> %vecins, <3 x i64> addrspace(1)* %out, align 32 386 ret void 387} 388 389; FIXME: Should be able to do without stack access. The used stack 390; space is also 2x what should be required. 391 392; GCN-LABEL: {{^}}dynamic_insertelement_v4f64: 393; GCN: SCRATCH_RSRC_DWORD 394 395; Stack store 396 397; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:32{{$}} 398; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:48{{$}} 399 400; Write element 401; GCN: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen{{$}} 402 403; Stack reload 404; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:32{{$}} 405; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:48{{$}} 406 407; Store result 408; GCN: buffer_store_dwordx4 409; GCN: buffer_store_dwordx4 410; GCN: s_endpgm 411; GCN: ScratchSize: 64 412 413define amdgpu_kernel void @dynamic_insertelement_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %a, i32 %b) nounwind { 414 %vecins = insertelement <4 x double> %a, double 8.0, i32 %b 415 store <4 x double> %vecins, <4 x double> addrspace(1)* %out, align 16 416 ret void 417} 418 419; GCN-LABEL: {{^}}dynamic_insertelement_v8f64: 420; GCN-DAG: SCRATCH_RSRC_DWORD 421 422; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:64{{$}} 423; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:80{{$}} 424; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:96{{$}} 425; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:112{{$}} 426 427; GCN: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen{{$}} 428 429; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:64{{$}} 430; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:80{{$}} 431; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:96{{$}} 432; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:112{{$}} 433 434; GCN: buffer_store_dwordx4 435; GCN: buffer_store_dwordx4 436; GCN: buffer_store_dwordx4 437; GCN: buffer_store_dwordx4 438; GCN: s_endpgm 439; GCN: ScratchSize: 128 440define amdgpu_kernel void @dynamic_insertelement_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %a, i32 %b) #0 { 441 %vecins = insertelement <8 x double> %a, double 8.0, i32 %b 442 store <8 x double> %vecins, <8 x double> addrspace(1)* %out, align 16 443 ret void 444} 445 446declare <4 x float> @llvm.amdgcn.image.gather4.lz.v4f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1 447 448attributes #0 = { nounwind } 449attributes #1 = { nounwind readnone } 450