1*a11bf9a7SArthur Eubanks; RUN: opt -mtriple=amdgcn-- -inline -S -amdgpu-inline-max-bb=2 %s | FileCheck %s --check-prefix=NOINL 2*a11bf9a7SArthur Eubanks; RUN: opt -mtriple=amdgcn-- -inline -S -amdgpu-inline-max-bb=3 %s | FileCheck %s --check-prefix=INL 3*a11bf9a7SArthur Eubanks; RUN: opt -mtriple=amdgcn-- -passes=inline -S -amdgpu-inline-max-bb=2 %s | FileCheck %s --check-prefix=NOINL 4*a11bf9a7SArthur Eubanks; RUN: opt -mtriple=amdgcn-- -passes=inline -S -amdgpu-inline-max-bb=3 %s | FileCheck %s --check-prefix=INL 5cb8de55fSValery Pykhtin 6cb8de55fSValery Pykhtindefine i32 @callee(i32 %x) { 7cb8de55fSValery Pykhtinentry: 8cb8de55fSValery Pykhtin %cc = icmp eq i32 %x, 1 9cb8de55fSValery Pykhtin br i1 %cc, label %ret_res, label %mulx 10cb8de55fSValery Pykhtin 11cb8de55fSValery Pykhtinmulx: 12cb8de55fSValery Pykhtin %mul1 = mul i32 %x, %x 13cb8de55fSValery Pykhtin %mul2 = mul i32 %mul1, %x 14cb8de55fSValery Pykhtin %mul3 = mul i32 %mul1, %mul2 15cb8de55fSValery Pykhtin %mul4 = mul i32 %mul3, %mul2 16cb8de55fSValery Pykhtin %mul5 = mul i32 %mul4, %mul3 17cb8de55fSValery Pykhtin br label %ret_res 18cb8de55fSValery Pykhtin 19cb8de55fSValery Pykhtinret_res: 20cb8de55fSValery Pykhtin %r = phi i32 [ %mul5, %mulx ], [ %x, %entry ] 21cb8de55fSValery Pykhtin ret i32 %r 22cb8de55fSValery Pykhtin} 23cb8de55fSValery Pykhtin 24cb8de55fSValery Pykhtin; INL-LABEL: @caller 25cb8de55fSValery Pykhtin; NOINL-LABEL: @caller 26cb8de55fSValery Pykhtin; INL: mul i32 27cb8de55fSValery Pykhtin; INL-NOT: call i32 28cb8de55fSValery Pykhtin; NOINL-NOT: mul i32 29cb8de55fSValery Pykhtin; NOINL: call i32 30cb8de55fSValery Pykhtin 31cb8de55fSValery Pykhtindefine amdgpu_kernel void @caller(i32 %x) { 32cb8de55fSValery Pykhtin %res = call i32 @callee(i32 %x) 33cb8de55fSValery Pykhtin store volatile i32 %res, i32 addrspace(1)* undef 34cb8de55fSValery Pykhtin ret void 35cb8de55fSValery Pykhtin} 36ffeb01c1SValery Pykhtin 37ffeb01c1SValery Pykhtin 38ffeb01c1SValery Pykhtin; inlinehint 39ffeb01c1SValery Pykhtindefine i32 @callee_hint(i32 %x) #0 { 40ffeb01c1SValery Pykhtinentry: 41ffeb01c1SValery Pykhtin %cc = icmp eq i32 %x, 1 42ffeb01c1SValery Pykhtin br i1 %cc, label %ret_res, label %mulx 43ffeb01c1SValery Pykhtin 44ffeb01c1SValery Pykhtinmulx: 45ffeb01c1SValery Pykhtin %mul1 = mul i32 %x, %x 46ffeb01c1SValery Pykhtin %mul2 = mul i32 %mul1, %x 47ffeb01c1SValery Pykhtin %mul3 = mul i32 %mul1, %mul2 48ffeb01c1SValery Pykhtin %mul4 = mul i32 %mul3, %mul2 49ffeb01c1SValery Pykhtin %mul5 = mul i32 %mul4, %mul3 50ffeb01c1SValery Pykhtin br label %ret_res 51ffeb01c1SValery Pykhtin 52ffeb01c1SValery Pykhtinret_res: 53ffeb01c1SValery Pykhtin %r = phi i32 [ %mul5, %mulx ], [ %x, %entry ] 54ffeb01c1SValery Pykhtin ret i32 %r 55ffeb01c1SValery Pykhtin} 56ffeb01c1SValery Pykhtin 57ffeb01c1SValery Pykhtin; INL-LABEL: @caller_hint 58ffeb01c1SValery Pykhtin; NOINL-LABEL: @caller_hint 59ffeb01c1SValery Pykhtin; INL: mul i32 60ffeb01c1SValery Pykhtin; INL-NOT: call i32 61ffeb01c1SValery Pykhtin; NOINL: mul i32 62ffeb01c1SValery Pykhtin; NOINL-NOT: call i32 63ffeb01c1SValery Pykhtin 64ffeb01c1SValery Pykhtindefine amdgpu_kernel void @caller_hint(i32 %x) { 65ffeb01c1SValery Pykhtin %res = call i32 @callee_hint(i32 %x) 66ffeb01c1SValery Pykhtin store volatile i32 %res, i32 addrspace(1)* undef 67ffeb01c1SValery Pykhtin ret void 68ffeb01c1SValery Pykhtin} 69ffeb01c1SValery Pykhtin 70ffeb01c1SValery Pykhtinattributes #0 = { inlinehint } 71