1; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s
2; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
3
4; CHECK: {{^}}inline_asm:
5; CHECK: s_endpgm
6; CHECK: s_endpgm
7define void @inline_asm(i32 addrspace(1)* %out) {
8entry:
9  store i32 5, i32 addrspace(1)* %out
10  call void asm sideeffect "s_endpgm", ""()
11  ret void
12}
13
14; CHECK: {{^}}inline_asm_shader:
15; CHECK: s_endpgm
16; CHECK: s_endpgm
17define amdgpu_ps void @inline_asm_shader() {
18entry:
19  call void asm sideeffect "s_endpgm", ""()
20  ret void
21}
22
23
24; CHECK: {{^}}branch_on_asm:
25; Make sure inline assembly is treted as divergent.
26; CHECK: s_mov_b32 s{{[0-9]+}}, 0
27; CHECK: s_and_saveexec_b64
28define void @branch_on_asm(i32 addrspace(1)* %out) {
29	%zero = call i32 asm "s_mov_b32 $0, 0", "=s"()
30	%cmp = icmp eq i32 %zero, 0
31	br i1 %cmp, label %if, label %endif
32
33if:
34	store i32 0, i32 addrspace(1)* %out
35	br label %endif
36
37endif:
38  ret void
39}
40
41; CHECK: {{^}}v_cmp_asm:
42; CHECK: v_mov_b32_e32 [[SRC:v[0-9]+]], s{{[0-9]+}}
43; CHECK: v_cmp_ne_i32_e64 s{{\[}}[[MASK_LO:[0-9]+]]:[[MASK_HI:[0-9]+]]{{\]}}, 0, [[SRC]]
44; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[MASK_LO]]
45; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[MASK_HI]]
46; CHECK: buffer_store_dwordx2 v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
47define void @v_cmp_asm(i64 addrspace(1)* %out, i32 %in) {
48  %sgpr = tail call i64 asm "v_cmp_ne_i32_e64 $0, 0, $1", "=s,v"(i32 %in)
49  store i64 %sgpr, i64 addrspace(1)* %out
50  ret void
51}
52