1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
3; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
4; RUN: opt -mtriple=amdgcn-- -S -amdgpu-unify-divergent-exit-nodes -verify %s | FileCheck -check-prefix=IR %s
5
6define amdgpu_kernel void @infinite_loop(i32 addrspace(1)* %out) {
7; SI-LABEL: infinite_loop:
8; SI:       ; %bb.0: ; %entry
9; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
10; SI-NEXT:    s_mov_b32 s3, 0xf000
11; SI-NEXT:    s_mov_b32 s2, -1
12; SI-NEXT:    v_mov_b32_e32 v0, 0x3e7
13; SI-NEXT:  BB0_1: ; %loop
14; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
15; SI-NEXT:    s_waitcnt lgkmcnt(0)
16; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
17; SI-NEXT:    s_branch BB0_1
18; IR-LABEL: @infinite_loop(
19; IR-NEXT:  entry:
20; IR-NEXT:    br label [[LOOP:%.*]]
21; IR:       loop:
22; IR-NEXT:    store volatile i32 999, i32 addrspace(1)* [[OUT:%.*]], align 4
23; IR-NEXT:    br label [[LOOP]]
24entry:
25  br label %loop
26
27loop:
28  store volatile i32 999, i32 addrspace(1)* %out, align 4
29  br label %loop
30}
31
32define amdgpu_kernel void @infinite_loop_ret(i32 addrspace(1)* %out) {
33; SI-LABEL: infinite_loop_ret:
34; SI:       ; %bb.0: ; %entry
35; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
36; SI-NEXT:    s_and_saveexec_b64 s[2:3], vcc
37; SI-NEXT:    s_cbranch_execz BB1_3
38; SI-NEXT:  ; %bb.1: ; %loop.preheader
39; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
40; SI-NEXT:    s_mov_b32 s3, 0xf000
41; SI-NEXT:    s_mov_b32 s2, -1
42; SI-NEXT:    v_mov_b32_e32 v0, 0x3e7
43; SI-NEXT:    s_and_b64 vcc, exec, -1
44; SI-NEXT:  BB1_2: ; %loop
45; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
46; SI-NEXT:    s_waitcnt lgkmcnt(0)
47; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
48; SI-NEXT:    s_cbranch_vccnz BB1_2
49; SI-NEXT:  BB1_3: ; %UnifiedReturnBlock
50; SI-NEXT:    s_endpgm
51; IR-LABEL: @infinite_loop_ret(
52; IR-NEXT:  entry:
53; IR-NEXT:    [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()
54; IR-NEXT:    [[COND:%.*]] = icmp eq i32 [[TMP]], 1
55; IR-NEXT:    br i1 [[COND]], label [[LOOP:%.*]], label [[UNIFIEDRETURNBLOCK:%.*]]
56; IR:       loop:
57; IR-NEXT:    store volatile i32 999, i32 addrspace(1)* [[OUT:%.*]], align 4
58; IR-NEXT:    br i1 true, label [[LOOP]], label [[UNIFIEDRETURNBLOCK]]
59; IR:       UnifiedReturnBlock:
60; IR-NEXT:    ret void
61entry:
62  %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
63  %cond = icmp eq i32 %tmp, 1
64  br i1 %cond, label %loop, label %return
65
66loop:
67  store volatile i32 999, i32 addrspace(1)* %out, align 4
68  br label %loop
69
70return:
71  ret void
72}
73
74define amdgpu_kernel void @infinite_loops(i32 addrspace(1)* %out) {
75; SI-LABEL: infinite_loops:
76; SI:       ; %bb.0: ; %entry
77; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
78; SI-NEXT:    s_mov_b64 s[2:3], -1
79; SI-NEXT:    s_cbranch_scc1 BB2_4
80; SI-NEXT:  ; %bb.1:
81; SI-NEXT:    s_mov_b32 s3, 0xf000
82; SI-NEXT:    s_mov_b32 s2, -1
83; SI-NEXT:    v_mov_b32_e32 v0, 0x378
84; SI-NEXT:    s_and_b64 vcc, exec, -1
85; SI-NEXT:  BB2_2: ; %loop2
86; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
87; SI-NEXT:    s_waitcnt lgkmcnt(0)
88; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
89; SI-NEXT:    s_cbranch_vccnz BB2_2
90; SI-NEXT:  ; %bb.3: ; %Flow
91; SI-NEXT:    s_mov_b64 s[2:3], 0
92; SI-NEXT:  BB2_4: ; %Flow2
93; SI-NEXT:    s_and_b64 vcc, exec, s[2:3]
94; SI-NEXT:    s_waitcnt lgkmcnt(0)
95; SI-NEXT:    s_mov_b64 vcc, vcc
96; SI-NEXT:    s_cbranch_vccz BB2_7
97; SI-NEXT:  ; %bb.5:
98; SI-NEXT:    s_mov_b32 s3, 0xf000
99; SI-NEXT:    s_mov_b32 s2, -1
100; SI-NEXT:    s_waitcnt expcnt(0)
101; SI-NEXT:    v_mov_b32_e32 v0, 0x3e7
102; SI-NEXT:    s_and_b64 vcc, exec, 0
103; SI-NEXT:  BB2_6: ; %loop1
104; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
105; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
106; SI-NEXT:    s_cbranch_vccz BB2_6
107; SI-NEXT:  BB2_7: ; %DummyReturnBlock
108; SI-NEXT:    s_endpgm
109; IR-LABEL: @infinite_loops(
110; IR-NEXT:  entry:
111; IR-NEXT:    br i1 undef, label [[LOOP1:%.*]], label [[LOOP2:%.*]]
112; IR:       loop1:
113; IR-NEXT:    store volatile i32 999, i32 addrspace(1)* [[OUT:%.*]], align 4
114; IR-NEXT:    br i1 true, label [[LOOP1]], label [[DUMMYRETURNBLOCK:%.*]]
115; IR:       loop2:
116; IR-NEXT:    store volatile i32 888, i32 addrspace(1)* [[OUT]], align 4
117; IR-NEXT:    br i1 true, label [[LOOP2]], label [[DUMMYRETURNBLOCK]]
118; IR:       DummyReturnBlock:
119; IR-NEXT:    ret void
120entry:
121  br i1 undef, label %loop1, label %loop2
122
123loop1:
124  store volatile i32 999, i32 addrspace(1)* %out, align 4
125  br label %loop1
126
127loop2:
128  store volatile i32 888, i32 addrspace(1)* %out, align 4
129  br label %loop2
130}
131
132define amdgpu_kernel void @infinite_loop_nest_ret(i32 addrspace(1)* %out) {
133; SI-LABEL: infinite_loop_nest_ret:
134; SI:       ; %bb.0: ; %entry
135; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
136; SI-NEXT:    s_and_saveexec_b64 s[2:3], vcc
137; SI-NEXT:    s_cbranch_execz BB3_5
138; SI-NEXT:  ; %bb.1: ; %outer_loop.preheader
139; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
140; SI-NEXT:    v_cmp_ne_u32_e64 s[0:1], 3, v0
141; SI-NEXT:    s_mov_b32 s7, 0xf000
142; SI-NEXT:    s_mov_b32 s6, -1
143; SI-NEXT:  BB3_2: ; %outer_loop
144; SI-NEXT:    ; =>This Loop Header: Depth=1
145; SI-NEXT:    ; Child Loop BB3_3 Depth 2
146; SI-NEXT:    s_mov_b64 s[2:3], 0
147; SI-NEXT:  BB3_3: ; %inner_loop
148; SI-NEXT:    ; Parent Loop BB3_2 Depth=1
149; SI-NEXT:    ; => This Inner Loop Header: Depth=2
150; SI-NEXT:    s_and_b64 s[8:9], exec, s[0:1]
151; SI-NEXT:    s_or_b64 s[2:3], s[8:9], s[2:3]
152; SI-NEXT:    s_waitcnt expcnt(0)
153; SI-NEXT:    v_mov_b32_e32 v0, 0x3e7
154; SI-NEXT:    s_waitcnt lgkmcnt(0)
155; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0
156; SI-NEXT:    s_andn2_b64 exec, exec, s[2:3]
157; SI-NEXT:    s_cbranch_execnz BB3_3
158; SI-NEXT:  ; %bb.4: ; %loop.exit.guard
159; SI-NEXT:    ; in Loop: Header=BB3_2 Depth=1
160; SI-NEXT:    s_or_b64 exec, exec, s[2:3]
161; SI-NEXT:    s_mov_b64 vcc, 0
162; SI-NEXT:    s_branch BB3_2
163; SI-NEXT:  BB3_5: ; %UnifiedReturnBlock
164; SI-NEXT:    s_endpgm
165; IR-LABEL: @infinite_loop_nest_ret(
166; IR-NEXT:  entry:
167; IR-NEXT:    [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()
168; IR-NEXT:    [[COND1:%.*]] = icmp eq i32 [[TMP]], 1
169; IR-NEXT:    br i1 [[COND1]], label [[OUTER_LOOP:%.*]], label [[UNIFIEDRETURNBLOCK:%.*]]
170; IR:       outer_loop:
171; IR-NEXT:    br label [[INNER_LOOP:%.*]]
172; IR:       inner_loop:
173; IR-NEXT:    store volatile i32 999, i32 addrspace(1)* [[OUT:%.*]], align 4
174; IR-NEXT:    [[COND3:%.*]] = icmp eq i32 [[TMP]], 3
175; IR-NEXT:    br i1 true, label [[TRANSITIONBLOCK:%.*]], label [[UNIFIEDRETURNBLOCK]]
176; IR:       TransitionBlock:
177; IR-NEXT:    br i1 [[COND3]], label [[INNER_LOOP]], label [[OUTER_LOOP]]
178; IR:       UnifiedReturnBlock:
179; IR-NEXT:    ret void
180entry:
181  %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
182  %cond1 = icmp eq i32 %tmp, 1
183  br i1 %cond1, label %outer_loop, label %return
184
185outer_loop:
186  ; %cond2 = icmp eq i32 %tmp, 2
187  ; br i1 %cond2, label %outer_loop, label %inner_loop
188  br label %inner_loop
189
190inner_loop:                                     ; preds = %LeafBlock, %LeafBlock1
191  store volatile i32 999, i32 addrspace(1)* %out, align 4
192  %cond3 = icmp eq i32 %tmp, 3
193  br i1 %cond3, label %inner_loop, label %outer_loop
194
195return:
196  ret void
197}
198
199declare i32 @llvm.amdgcn.workitem.id.x()
200