1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 3; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s 4; RUN: opt -mtriple=amdgcn-- -S -amdgpu-unify-divergent-exit-nodes -verify %s | FileCheck -check-prefix=IR %s 5 6define amdgpu_kernel void @infinite_loop(i32 addrspace(1)* %out) { 7; SI-LABEL: infinite_loop: 8; SI: ; %bb.0: ; %entry 9; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 10; SI-NEXT: s_mov_b32 s3, 0xf000 11; SI-NEXT: s_mov_b32 s2, -1 12; SI-NEXT: v_mov_b32_e32 v0, 0x3e7 13; SI-NEXT: BB0_1: ; %loop 14; SI-NEXT: ; =>This Inner Loop Header: Depth=1 15; SI-NEXT: s_waitcnt lgkmcnt(0) 16; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 17; SI-NEXT: s_branch BB0_1 18; IR-LABEL: @infinite_loop( 19; IR-NEXT: entry: 20; IR-NEXT: br label [[LOOP:%.*]] 21; IR: loop: 22; IR-NEXT: store volatile i32 999, i32 addrspace(1)* [[OUT:%.*]], align 4 23; IR-NEXT: br label [[LOOP]] 24; 25entry: 26 br label %loop 27 28loop: 29 store volatile i32 999, i32 addrspace(1)* %out, align 4 30 br label %loop 31} 32 33define amdgpu_kernel void @infinite_loop_ret(i32 addrspace(1)* %out) { 34; SI-LABEL: infinite_loop_ret: 35; SI: ; %bb.0: ; %entry 36; SI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 37; SI-NEXT: s_and_saveexec_b64 s[2:3], vcc 38; SI-NEXT: s_cbranch_execz BB1_3 39; SI-NEXT: ; %bb.1: ; %loop.preheader 40; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 41; SI-NEXT: s_mov_b32 s3, 0xf000 42; SI-NEXT: s_mov_b32 s2, -1 43; SI-NEXT: v_mov_b32_e32 v0, 0x3e7 44; SI-NEXT: s_and_b64 vcc, exec, -1 45; SI-NEXT: BB1_2: ; %loop 46; SI-NEXT: ; =>This Inner Loop Header: Depth=1 47; SI-NEXT: s_waitcnt lgkmcnt(0) 48; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 49; SI-NEXT: s_cbranch_vccnz BB1_2 50; SI-NEXT: BB1_3: ; %UnifiedReturnBlock 51; SI-NEXT: s_endpgm 52; IR-LABEL: @infinite_loop_ret( 53; IR-NEXT: entry: 54; IR-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x() 55; IR-NEXT: [[COND:%.*]] = icmp eq i32 [[TMP]], 1 56; IR-NEXT: br i1 [[COND]], label [[LOOP:%.*]], label [[UNIFIEDRETURNBLOCK:%.*]] 57; IR: loop: 58; IR-NEXT: store volatile i32 999, i32 addrspace(1)* [[OUT:%.*]], align 4 59; IR-NEXT: br i1 true, label [[LOOP]], label [[UNIFIEDRETURNBLOCK]] 60; IR: UnifiedReturnBlock: 61; IR-NEXT: ret void 62; 63entry: 64 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() 65 %cond = icmp eq i32 %tmp, 1 66 br i1 %cond, label %loop, label %return 67 68loop: 69 store volatile i32 999, i32 addrspace(1)* %out, align 4 70 br label %loop 71 72return: 73 ret void 74} 75 76define amdgpu_kernel void @infinite_loops(i32 addrspace(1)* %out) { 77; SI-LABEL: infinite_loops: 78; SI: ; %bb.0: ; %entry 79; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 80; SI-NEXT: s_mov_b32 s3, 0xf000 81; SI-NEXT: s_mov_b32 s2, -1 82; SI-NEXT: s_cbranch_scc0 BB2_3 83; SI-NEXT: ; %bb.1: ; %loop1.preheader 84; SI-NEXT: v_mov_b32_e32 v0, 0x3e7 85; SI-NEXT: s_and_b64 vcc, exec, -1 86; SI-NEXT: BB2_2: ; %loop1 87; SI-NEXT: ; =>This Inner Loop Header: Depth=1 88; SI-NEXT: s_waitcnt lgkmcnt(0) 89; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 90; SI-NEXT: s_cbranch_vccnz BB2_2 91; SI-NEXT: s_branch BB2_5 92; SI-NEXT: BB2_3: 93; SI-NEXT: v_mov_b32_e32 v0, 0x378 94; SI-NEXT: s_and_b64 vcc, exec, -1 95; SI-NEXT: BB2_4: ; %loop2 96; SI-NEXT: ; =>This Inner Loop Header: Depth=1 97; SI-NEXT: s_waitcnt lgkmcnt(0) 98; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 99; SI-NEXT: s_cbranch_vccnz BB2_4 100; SI-NEXT: BB2_5: ; %DummyReturnBlock 101; SI-NEXT: s_endpgm 102; IR-LABEL: @infinite_loops( 103; IR-NEXT: entry: 104; IR-NEXT: br i1 undef, label [[LOOP1:%.*]], label [[LOOP2:%.*]] 105; IR: loop1: 106; IR-NEXT: store volatile i32 999, i32 addrspace(1)* [[OUT:%.*]], align 4 107; IR-NEXT: br i1 true, label [[LOOP1]], label [[DUMMYRETURNBLOCK:%.*]] 108; IR: loop2: 109; IR-NEXT: store volatile i32 888, i32 addrspace(1)* [[OUT]], align 4 110; IR-NEXT: br i1 true, label [[LOOP2]], label [[DUMMYRETURNBLOCK]] 111; IR: DummyReturnBlock: 112; IR-NEXT: ret void 113; 114entry: 115 br i1 undef, label %loop1, label %loop2 116 117loop1: 118 store volatile i32 999, i32 addrspace(1)* %out, align 4 119 br label %loop1 120 121loop2: 122 store volatile i32 888, i32 addrspace(1)* %out, align 4 123 br label %loop2 124} 125 126define amdgpu_kernel void @infinite_loop_nest_ret(i32 addrspace(1)* %out) { 127; SI-LABEL: infinite_loop_nest_ret: 128; SI: ; %bb.0: ; %entry 129; SI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 130; SI-NEXT: s_and_saveexec_b64 s[2:3], vcc 131; SI-NEXT: s_cbranch_execz BB3_5 132; SI-NEXT: ; %bb.1: ; %outer_loop.preheader 133; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 134; SI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0 135; SI-NEXT: v_cmp_ne_u32_e64 s[0:1], 3, v0 136; SI-NEXT: s_mov_b64 s[2:3], 0 137; SI-NEXT: s_mov_b32 s7, 0xf000 138; SI-NEXT: s_mov_b32 s6, -1 139; SI-NEXT: BB3_2: ; %outer_loop 140; SI-NEXT: ; =>This Loop Header: Depth=1 141; SI-NEXT: ; Child Loop BB3_3 Depth 2 142; SI-NEXT: s_and_b64 s[8:9], exec, vcc 143; SI-NEXT: s_or_b64 s[2:3], s[8:9], s[2:3] 144; SI-NEXT: s_mov_b64 s[8:9], 0 145; SI-NEXT: BB3_3: ; %inner_loop 146; SI-NEXT: ; Parent Loop BB3_2 Depth=1 147; SI-NEXT: ; => This Inner Loop Header: Depth=2 148; SI-NEXT: s_and_b64 s[10:11], exec, s[0:1] 149; SI-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9] 150; SI-NEXT: s_waitcnt expcnt(0) 151; SI-NEXT: v_mov_b32_e32 v0, 0x3e7 152; SI-NEXT: s_waitcnt lgkmcnt(0) 153; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 154; SI-NEXT: s_andn2_b64 exec, exec, s[8:9] 155; SI-NEXT: s_cbranch_execnz BB3_3 156; SI-NEXT: ; %bb.4: ; %Flow 157; SI-NEXT: ; in Loop: Header=BB3_2 Depth=1 158; SI-NEXT: s_or_b64 exec, exec, s[8:9] 159; SI-NEXT: s_andn2_b64 exec, exec, s[2:3] 160; SI-NEXT: s_cbranch_execnz BB3_2 161; SI-NEXT: BB3_5: ; %UnifiedReturnBlock 162; SI-NEXT: s_endpgm 163; IR-LABEL: @infinite_loop_nest_ret( 164; IR-NEXT: entry: 165; IR-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x() 166; IR-NEXT: [[COND1:%.*]] = icmp eq i32 [[TMP]], 1 167; IR-NEXT: br i1 [[COND1]], label [[OUTER_LOOP:%.*]], label [[UNIFIEDRETURNBLOCK:%.*]] 168; IR: outer_loop: 169; IR-NEXT: br label [[INNER_LOOP:%.*]] 170; IR: inner_loop: 171; IR-NEXT: store volatile i32 999, i32 addrspace(1)* [[OUT:%.*]], align 4 172; IR-NEXT: [[COND3:%.*]] = icmp eq i32 [[TMP]], 3 173; IR-NEXT: br i1 true, label [[TRANSITIONBLOCK:%.*]], label [[UNIFIEDRETURNBLOCK]] 174; IR: TransitionBlock: 175; IR-NEXT: br i1 [[COND3]], label [[INNER_LOOP]], label [[OUTER_LOOP]] 176; IR: UnifiedReturnBlock: 177; IR-NEXT: ret void 178; 179entry: 180 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() 181 %cond1 = icmp eq i32 %tmp, 1 182 br i1 %cond1, label %outer_loop, label %return 183 184outer_loop: 185 ; %cond2 = icmp eq i32 %tmp, 2 186 ; br i1 %cond2, label %outer_loop, label %inner_loop 187 br label %inner_loop 188 189inner_loop: ; preds = %LeafBlock, %LeafBlock1 190 store volatile i32 999, i32 addrspace(1)* %out, align 4 191 %cond3 = icmp eq i32 %tmp, 3 192 br i1 %cond3, label %inner_loop, label %outer_loop 193 194return: 195 ret void 196} 197 198declare i32 @llvm.amdgcn.workitem.id.x() 199