1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 3; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s 4; RUN: opt -mtriple=amdgcn-- -S -amdgpu-unify-divergent-exit-nodes -verify %s | FileCheck -check-prefix=IR %s 5 6define amdgpu_kernel void @infinite_loop(i32 addrspace(1)* %out) { 7; SI-LABEL: infinite_loop: 8; SI: ; %bb.0: ; %entry 9; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 10; SI-NEXT: s_mov_b32 s3, 0xf000 11; SI-NEXT: s_mov_b32 s2, -1 12; SI-NEXT: v_mov_b32_e32 v0, 0x3e7 13; SI-NEXT: BB0_1: ; %loop 14; SI-NEXT: ; =>This Inner Loop Header: Depth=1 15; SI-NEXT: s_waitcnt lgkmcnt(0) 16; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 17; SI-NEXT: s_branch BB0_1 18; IR-LABEL: @infinite_loop( 19; IR-NEXT: entry: 20; IR-NEXT: br label [[LOOP:%.*]] 21; IR: loop: 22; IR-NEXT: store volatile i32 999, i32 addrspace(1)* [[OUT:%.*]], align 4 23; IR-NEXT: br label [[LOOP]] 24; 25entry: 26 br label %loop 27 28loop: 29 store volatile i32 999, i32 addrspace(1)* %out, align 4 30 br label %loop 31} 32 33define amdgpu_kernel void @infinite_loop_ret(i32 addrspace(1)* %out) { 34; SI-LABEL: infinite_loop_ret: 35; SI: ; %bb.0: ; %entry 36; SI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 37; SI-NEXT: s_and_saveexec_b64 s[2:3], vcc 38; SI-NEXT: s_cbranch_execz BB1_3 39; SI-NEXT: ; %bb.1: ; %loop.preheader 40; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 41; SI-NEXT: s_mov_b32 s3, 0xf000 42; SI-NEXT: s_mov_b32 s2, -1 43; SI-NEXT: v_mov_b32_e32 v0, 0x3e7 44; SI-NEXT: s_and_b64 vcc, exec, -1 45; SI-NEXT: BB1_2: ; %loop 46; SI-NEXT: ; =>This Inner Loop Header: Depth=1 47; SI-NEXT: s_waitcnt lgkmcnt(0) 48; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 49; SI-NEXT: s_cbranch_vccnz BB1_2 50; SI-NEXT: BB1_3: ; %UnifiedReturnBlock 51; SI-NEXT: s_endpgm 52; IR-LABEL: @infinite_loop_ret( 53; IR-NEXT: entry: 54; IR-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x() 55; IR-NEXT: [[COND:%.*]] = icmp eq i32 [[TMP]], 1 56; IR-NEXT: br i1 [[COND]], label [[LOOP:%.*]], label [[UNIFIEDRETURNBLOCK:%.*]] 57; IR: loop: 58; IR-NEXT: store volatile i32 999, i32 addrspace(1)* [[OUT:%.*]], align 4 59; IR-NEXT: br i1 true, label [[LOOP]], label [[UNIFIEDRETURNBLOCK]] 60; IR: UnifiedReturnBlock: 61; IR-NEXT: ret void 62; 63entry: 64 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() 65 %cond = icmp eq i32 %tmp, 1 66 br i1 %cond, label %loop, label %return 67 68loop: 69 store volatile i32 999, i32 addrspace(1)* %out, align 4 70 br label %loop 71 72return: 73 ret void 74} 75 76define amdgpu_kernel void @infinite_loops(i32 addrspace(1)* %out) { 77; SI-LABEL: infinite_loops: 78; SI: ; %bb.0: ; %entry 79; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 80; SI-NEXT: s_mov_b64 s[2:3], -1 81; SI-NEXT: s_cbranch_scc1 BB2_4 82; SI-NEXT: ; %bb.1: 83; SI-NEXT: s_mov_b32 s3, 0xf000 84; SI-NEXT: s_mov_b32 s2, -1 85; SI-NEXT: v_mov_b32_e32 v0, 0x378 86; SI-NEXT: s_and_b64 vcc, exec, -1 87; SI-NEXT: BB2_2: 88; SI: s_waitcnt lgkmcnt(0) 89; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 90; SI-NEXT: s_cbranch_vccnz BB2_2 91; SI-NEXT: ; %bb.3: 92; SI-NEXT: s_mov_b64 s[2:3], 0 93; SI-NEXT: BB2_4: 94; SI-NEXT: s_and_b64 vcc, exec, s[2:3] 95; SI-NEXT: s_waitcnt lgkmcnt(0) 96; SI-NEXT: s_mov_b64 vcc, vcc 97; SI-NEXT: s_cbranch_vccz BB2_7 98; SI-NEXT: ; %bb.5: 99; SI-NEXT: s_mov_b32 s3, 0xf000 100; SI-NEXT: s_mov_b32 s2, -1 101; SI-NEXT: s_waitcnt expcnt(0) 102; SI-NEXT: v_mov_b32_e32 v0, 0x3e7 103; SI-NEXT: s_and_b64 vcc, exec, 0 104; SI-NEXT: BB2_6: 105; SI: buffer_store_dword v0, off, s[0:3], 0 106; SI-NEXT: s_cbranch_vccz BB2_6 107; SI-NEXT: BB2_7: 108; SI-NEXT: s_endpgm 109 110; IR-LABEL: @infinite_loops( 111; IR-NEXT: entry: 112; IR-NEXT: br i1 undef, label [[LOOP1:%.*]], label [[LOOP2:%.*]] 113; IR: loop1: 114; IR-NEXT: store volatile i32 999, i32 addrspace(1)* [[OUT:%.*]], align 4 115; IR-NEXT: br i1 true, label [[LOOP1]], label [[DUMMYRETURNBLOCK:%.*]] 116; IR: loop2: 117; IR-NEXT: store volatile i32 888, i32 addrspace(1)* [[OUT]], align 4 118; IR-NEXT: br i1 true, label [[LOOP2]], label [[DUMMYRETURNBLOCK]] 119; IR: DummyReturnBlock: 120; IR-NEXT: ret void 121; 122entry: 123 br i1 undef, label %loop1, label %loop2 124 125loop1: 126 store volatile i32 999, i32 addrspace(1)* %out, align 4 127 br label %loop1 128 129loop2: 130 store volatile i32 888, i32 addrspace(1)* %out, align 4 131 br label %loop2 132} 133 134define amdgpu_kernel void @infinite_loop_nest_ret(i32 addrspace(1)* %out) { 135; SI-LABEL: infinite_loop_nest_ret: 136; SI: ; %bb.0: ; %entry 137; SI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 138; SI-NEXT: s_and_saveexec_b64 s[2:3], vcc 139; SI-NEXT: s_cbranch_execz BB3_5 140; SI-NEXT: ; %bb.1: ; %outer_loop.preheader 141; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 142; SI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0 143; SI-NEXT: v_cmp_ne_u32_e64 s[0:1], 3, v0 144; SI-NEXT: s_mov_b64 s[2:3], 0 145; SI-NEXT: s_mov_b32 s7, 0xf000 146; SI-NEXT: s_mov_b32 s6, -1 147; SI-NEXT: BB3_2: ; %outer_loop 148; SI-NEXT: ; =>This Loop Header: Depth=1 149; SI-NEXT: ; Child Loop BB3_3 Depth 2 150; SI-NEXT: s_and_b64 s[8:9], exec, vcc 151; SI-NEXT: s_or_b64 s[2:3], s[8:9], s[2:3] 152; SI-NEXT: s_mov_b64 s[8:9], 0 153; SI-NEXT: BB3_3: ; %inner_loop 154; SI-NEXT: ; Parent Loop BB3_2 Depth=1 155; SI-NEXT: ; => This Inner Loop Header: Depth=2 156; SI-NEXT: s_and_b64 s[10:11], exec, s[0:1] 157; SI-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9] 158; SI-NEXT: s_waitcnt expcnt(0) 159; SI-NEXT: v_mov_b32_e32 v0, 0x3e7 160; SI-NEXT: s_waitcnt lgkmcnt(0) 161; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 162; SI-NEXT: s_andn2_b64 exec, exec, s[8:9] 163; SI-NEXT: s_cbranch_execnz BB3_3 164; SI-NEXT: ; %bb.4: ; %Flow 165; SI-NEXT: ; in Loop: Header=BB3_2 Depth=1 166; SI-NEXT: s_or_b64 exec, exec, s[8:9] 167; SI-NEXT: s_andn2_b64 exec, exec, s[2:3] 168; SI-NEXT: s_cbranch_execnz BB3_2 169; SI-NEXT: BB3_5: ; %UnifiedReturnBlock 170; SI-NEXT: s_endpgm 171; IR-LABEL: @infinite_loop_nest_ret( 172; IR-NEXT: entry: 173; IR-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x() 174; IR-NEXT: [[COND1:%.*]] = icmp eq i32 [[TMP]], 1 175; IR-NEXT: br i1 [[COND1]], label [[OUTER_LOOP:%.*]], label [[UNIFIEDRETURNBLOCK:%.*]] 176; IR: outer_loop: 177; IR-NEXT: br label [[INNER_LOOP:%.*]] 178; IR: inner_loop: 179; IR-NEXT: store volatile i32 999, i32 addrspace(1)* [[OUT:%.*]], align 4 180; IR-NEXT: [[COND3:%.*]] = icmp eq i32 [[TMP]], 3 181; IR-NEXT: br i1 true, label [[TRANSITIONBLOCK:%.*]], label [[UNIFIEDRETURNBLOCK]] 182; IR: TransitionBlock: 183; IR-NEXT: br i1 [[COND3]], label [[INNER_LOOP]], label [[OUTER_LOOP]] 184; IR: UnifiedReturnBlock: 185; IR-NEXT: ret void 186; 187entry: 188 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() 189 %cond1 = icmp eq i32 %tmp, 1 190 br i1 %cond1, label %outer_loop, label %return 191 192outer_loop: 193 ; %cond2 = icmp eq i32 %tmp, 2 194 ; br i1 %cond2, label %outer_loop, label %inner_loop 195 br label %inner_loop 196 197inner_loop: ; preds = %LeafBlock, %LeafBlock1 198 store volatile i32 999, i32 addrspace(1)* %out, align 4 199 %cond3 = icmp eq i32 %tmp, 3 200 br i1 %cond3, label %inner_loop, label %outer_loop 201 202return: 203 ret void 204} 205 206declare i32 @llvm.amdgcn.workitem.id.x() 207