1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=-flat-for-global -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=GFX10 %s 3; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=tonga -mattr=-flat-for-global -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s 4; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s 5 6; FIXME: Merge into imm.ll 7 8define amdgpu_kernel void @store_inline_imm_neg_0.0_i16(i16 addrspace(1)* %out) { 9; GFX10-LABEL: store_inline_imm_neg_0.0_i16: 10; GFX10: ; %bb.0: 11; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xfa] 12; GFX10-NEXT: v_mov_b32_e32 v0, 0xffff8000 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x80,0xff,0xff] 13; GFX10-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x03,0x83,0xbe,0x00,0x60,0x01,0x31] 14; GFX10-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x03,0x82,0xbe] 15; GFX10-NEXT: ; implicit-def: $vcc_hi 16; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf] 17; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 18; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 19; 20; VI-LABEL: store_inline_imm_neg_0.0_i16: 21; VI: ; %bb.0: 22; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x06,0xc0,0x00,0x00,0x00,0x00] 23; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11] 24; VI-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] 25; VI-NEXT: v_mov_b32_e32 v0, 0xffff8000 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x80,0xff,0xff] 26; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0x00,0x8c,0xbf] 27; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 28; VI-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 29; 30; SI-LABEL: store_inline_imm_neg_0.0_i16: 31; SI: ; %bb.0: 32; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 33; SI-NEXT: s_mov_b32 s3, 0xf000 34; SI-NEXT: s_mov_b32 s2, -1 35; SI-NEXT: v_mov_b32_e32 v0, 0x8000 36; SI-NEXT: s_waitcnt lgkmcnt(0) 37; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 38; SI-NEXT: s_endpgm 39 store volatile i16 -32768, i16 addrspace(1)* %out 40 ret void 41} 42 43define amdgpu_kernel void @store_inline_imm_0.0_f16(half addrspace(1)* %out) { 44; GFX10-LABEL: store_inline_imm_0.0_f16: 45; GFX10: ; %bb.0: 46; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xfa] 47; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; encoding: [0x80,0x02,0x00,0x7e] 48; GFX10-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x03,0x83,0xbe,0x00,0x60,0x01,0x31] 49; GFX10-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x03,0x82,0xbe] 50; GFX10-NEXT: ; implicit-def: $vcc_hi 51; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf] 52; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 53; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 54; 55; VI-LABEL: store_inline_imm_0.0_f16: 56; VI: ; %bb.0: 57; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x06,0xc0,0x00,0x00,0x00,0x00] 58; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11] 59; VI-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] 60; VI-NEXT: v_mov_b32_e32 v0, 0 ; encoding: [0x80,0x02,0x00,0x7e] 61; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0x00,0x8c,0xbf] 62; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 63; VI-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 64; 65; SI-LABEL: store_inline_imm_0.0_f16: 66; SI: ; %bb.0: 67; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 68; SI-NEXT: s_mov_b32 s3, 0xf000 69; SI-NEXT: s_mov_b32 s2, -1 70; SI-NEXT: v_mov_b32_e32 v0, 0 71; SI-NEXT: s_waitcnt lgkmcnt(0) 72; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 73; SI-NEXT: s_endpgm 74 store half 0.0, half addrspace(1)* %out 75 ret void 76} 77 78define amdgpu_kernel void @store_imm_neg_0.0_f16(half addrspace(1)* %out) { 79; GFX10-LABEL: store_imm_neg_0.0_f16: 80; GFX10: ; %bb.0: 81; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xfa] 82; GFX10-NEXT: v_mov_b32_e32 v0, 0xffff8000 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x80,0xff,0xff] 83; GFX10-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x03,0x83,0xbe,0x00,0x60,0x01,0x31] 84; GFX10-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x03,0x82,0xbe] 85; GFX10-NEXT: ; implicit-def: $vcc_hi 86; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf] 87; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 88; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 89; 90; VI-LABEL: store_imm_neg_0.0_f16: 91; VI: ; %bb.0: 92; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x06,0xc0,0x00,0x00,0x00,0x00] 93; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11] 94; VI-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] 95; VI-NEXT: v_mov_b32_e32 v0, 0xffff8000 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x80,0xff,0xff] 96; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0x00,0x8c,0xbf] 97; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 98; VI-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 99; 100; SI-LABEL: store_imm_neg_0.0_f16: 101; SI: ; %bb.0: 102; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 103; SI-NEXT: s_mov_b32 s3, 0xf000 104; SI-NEXT: s_mov_b32 s2, -1 105; SI-NEXT: v_mov_b32_e32 v0, 0x8000 106; SI-NEXT: s_waitcnt lgkmcnt(0) 107; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 108; SI-NEXT: s_endpgm 109 store half -0.0, half addrspace(1)* %out 110 ret void 111} 112 113define amdgpu_kernel void @store_inline_imm_0.5_f16(half addrspace(1)* %out) { 114; GFX10-LABEL: store_inline_imm_0.5_f16: 115; GFX10: ; %bb.0: 116; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xfa] 117; GFX10-NEXT: v_mov_b32_e32 v0, 0x3800 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x38,0x00,0x00] 118; GFX10-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x03,0x83,0xbe,0x00,0x60,0x01,0x31] 119; GFX10-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x03,0x82,0xbe] 120; GFX10-NEXT: ; implicit-def: $vcc_hi 121; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf] 122; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 123; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 124; 125; VI-LABEL: store_inline_imm_0.5_f16: 126; VI: ; %bb.0: 127; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x06,0xc0,0x00,0x00,0x00,0x00] 128; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11] 129; VI-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] 130; VI-NEXT: v_mov_b32_e32 v0, 0x3800 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x38,0x00,0x00] 131; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0x00,0x8c,0xbf] 132; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 133; VI-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 134; 135; SI-LABEL: store_inline_imm_0.5_f16: 136; SI: ; %bb.0: 137; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 138; SI-NEXT: s_mov_b32 s3, 0xf000 139; SI-NEXT: s_mov_b32 s2, -1 140; SI-NEXT: v_mov_b32_e32 v0, 0x3800 141; SI-NEXT: s_waitcnt lgkmcnt(0) 142; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 143; SI-NEXT: s_endpgm 144 store half 0.5, half addrspace(1)* %out 145 ret void 146} 147 148define amdgpu_kernel void @store_inline_imm_m_0.5_f16(half addrspace(1)* %out) { 149; GFX10-LABEL: store_inline_imm_m_0.5_f16: 150; GFX10: ; %bb.0: 151; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xfa] 152; GFX10-NEXT: v_mov_b32_e32 v0, 0xffffb800 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0xb8,0xff,0xff] 153; GFX10-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x03,0x83,0xbe,0x00,0x60,0x01,0x31] 154; GFX10-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x03,0x82,0xbe] 155; GFX10-NEXT: ; implicit-def: $vcc_hi 156; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf] 157; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 158; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 159; 160; VI-LABEL: store_inline_imm_m_0.5_f16: 161; VI: ; %bb.0: 162; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x06,0xc0,0x00,0x00,0x00,0x00] 163; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11] 164; VI-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] 165; VI-NEXT: v_mov_b32_e32 v0, 0xffffb800 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0xb8,0xff,0xff] 166; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0x00,0x8c,0xbf] 167; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 168; VI-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 169; 170; SI-LABEL: store_inline_imm_m_0.5_f16: 171; SI: ; %bb.0: 172; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 173; SI-NEXT: s_mov_b32 s3, 0xf000 174; SI-NEXT: s_mov_b32 s2, -1 175; SI-NEXT: v_mov_b32_e32 v0, 0xb800 176; SI-NEXT: s_waitcnt lgkmcnt(0) 177; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 178; SI-NEXT: s_endpgm 179 store half -0.5, half addrspace(1)* %out 180 ret void 181} 182 183define amdgpu_kernel void @store_inline_imm_1.0_f16(half addrspace(1)* %out) { 184; GFX10-LABEL: store_inline_imm_1.0_f16: 185; GFX10: ; %bb.0: 186; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xfa] 187; GFX10-NEXT: v_mov_b32_e32 v0, 0x3c00 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x3c,0x00,0x00] 188; GFX10-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x03,0x83,0xbe,0x00,0x60,0x01,0x31] 189; GFX10-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x03,0x82,0xbe] 190; GFX10-NEXT: ; implicit-def: $vcc_hi 191; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf] 192; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 193; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 194; 195; VI-LABEL: store_inline_imm_1.0_f16: 196; VI: ; %bb.0: 197; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x06,0xc0,0x00,0x00,0x00,0x00] 198; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11] 199; VI-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] 200; VI-NEXT: v_mov_b32_e32 v0, 0x3c00 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x3c,0x00,0x00] 201; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0x00,0x8c,0xbf] 202; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 203; VI-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 204; 205; SI-LABEL: store_inline_imm_1.0_f16: 206; SI: ; %bb.0: 207; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 208; SI-NEXT: s_mov_b32 s3, 0xf000 209; SI-NEXT: s_mov_b32 s2, -1 210; SI-NEXT: v_mov_b32_e32 v0, 0x3c00 211; SI-NEXT: s_waitcnt lgkmcnt(0) 212; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 213; SI-NEXT: s_endpgm 214 store half 1.0, half addrspace(1)* %out 215 ret void 216} 217 218define amdgpu_kernel void @store_inline_imm_m_1.0_f16(half addrspace(1)* %out) { 219; GFX10-LABEL: store_inline_imm_m_1.0_f16: 220; GFX10: ; %bb.0: 221; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xfa] 222; GFX10-NEXT: v_mov_b32_e32 v0, 0xffffbc00 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0xbc,0xff,0xff] 223; GFX10-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x03,0x83,0xbe,0x00,0x60,0x01,0x31] 224; GFX10-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x03,0x82,0xbe] 225; GFX10-NEXT: ; implicit-def: $vcc_hi 226; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf] 227; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 228; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 229; 230; VI-LABEL: store_inline_imm_m_1.0_f16: 231; VI: ; %bb.0: 232; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x06,0xc0,0x00,0x00,0x00,0x00] 233; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11] 234; VI-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] 235; VI-NEXT: v_mov_b32_e32 v0, 0xffffbc00 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0xbc,0xff,0xff] 236; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0x00,0x8c,0xbf] 237; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 238; VI-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 239; 240; SI-LABEL: store_inline_imm_m_1.0_f16: 241; SI: ; %bb.0: 242; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 243; SI-NEXT: s_mov_b32 s3, 0xf000 244; SI-NEXT: s_mov_b32 s2, -1 245; SI-NEXT: v_mov_b32_e32 v0, 0xbc00 246; SI-NEXT: s_waitcnt lgkmcnt(0) 247; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 248; SI-NEXT: s_endpgm 249 store half -1.0, half addrspace(1)* %out 250 ret void 251} 252 253define amdgpu_kernel void @store_inline_imm_2.0_f16(half addrspace(1)* %out) { 254; GFX10-LABEL: store_inline_imm_2.0_f16: 255; GFX10: ; %bb.0: 256; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xfa] 257; GFX10-NEXT: v_mov_b32_e32 v0, 0x4000 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x40,0x00,0x00] 258; GFX10-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x03,0x83,0xbe,0x00,0x60,0x01,0x31] 259; GFX10-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x03,0x82,0xbe] 260; GFX10-NEXT: ; implicit-def: $vcc_hi 261; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf] 262; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 263; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 264; 265; VI-LABEL: store_inline_imm_2.0_f16: 266; VI: ; %bb.0: 267; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x06,0xc0,0x00,0x00,0x00,0x00] 268; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11] 269; VI-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] 270; VI-NEXT: v_mov_b32_e32 v0, 0x4000 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x40,0x00,0x00] 271; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0x00,0x8c,0xbf] 272; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 273; VI-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 274; 275; SI-LABEL: store_inline_imm_2.0_f16: 276; SI: ; %bb.0: 277; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 278; SI-NEXT: s_mov_b32 s3, 0xf000 279; SI-NEXT: s_mov_b32 s2, -1 280; SI-NEXT: v_mov_b32_e32 v0, 0x4000 281; SI-NEXT: s_waitcnt lgkmcnt(0) 282; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 283; SI-NEXT: s_endpgm 284 store half 2.0, half addrspace(1)* %out 285 ret void 286} 287 288define amdgpu_kernel void @store_inline_imm_m_2.0_f16(half addrspace(1)* %out) { 289; GFX10-LABEL: store_inline_imm_m_2.0_f16: 290; GFX10: ; %bb.0: 291; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xfa] 292; GFX10-NEXT: v_mov_b32_e32 v0, 0xffffc000 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0xc0,0xff,0xff] 293; GFX10-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x03,0x83,0xbe,0x00,0x60,0x01,0x31] 294; GFX10-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x03,0x82,0xbe] 295; GFX10-NEXT: ; implicit-def: $vcc_hi 296; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf] 297; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 298; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 299; 300; VI-LABEL: store_inline_imm_m_2.0_f16: 301; VI: ; %bb.0: 302; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x06,0xc0,0x00,0x00,0x00,0x00] 303; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11] 304; VI-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] 305; VI-NEXT: v_mov_b32_e32 v0, 0xffffc000 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0xc0,0xff,0xff] 306; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0x00,0x8c,0xbf] 307; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 308; VI-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 309; 310; SI-LABEL: store_inline_imm_m_2.0_f16: 311; SI: ; %bb.0: 312; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 313; SI-NEXT: s_mov_b32 s3, 0xf000 314; SI-NEXT: s_mov_b32 s2, -1 315; SI-NEXT: v_mov_b32_e32 v0, 0xc000 316; SI-NEXT: s_waitcnt lgkmcnt(0) 317; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 318; SI-NEXT: s_endpgm 319 store half -2.0, half addrspace(1)* %out 320 ret void 321} 322 323define amdgpu_kernel void @store_inline_imm_4.0_f16(half addrspace(1)* %out) { 324; GFX10-LABEL: store_inline_imm_4.0_f16: 325; GFX10: ; %bb.0: 326; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xfa] 327; GFX10-NEXT: v_mov_b32_e32 v0, 0x4400 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x44,0x00,0x00] 328; GFX10-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x03,0x83,0xbe,0x00,0x60,0x01,0x31] 329; GFX10-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x03,0x82,0xbe] 330; GFX10-NEXT: ; implicit-def: $vcc_hi 331; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf] 332; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 333; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 334; 335; VI-LABEL: store_inline_imm_4.0_f16: 336; VI: ; %bb.0: 337; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x06,0xc0,0x00,0x00,0x00,0x00] 338; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11] 339; VI-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] 340; VI-NEXT: v_mov_b32_e32 v0, 0x4400 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x44,0x00,0x00] 341; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0x00,0x8c,0xbf] 342; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 343; VI-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 344; 345; SI-LABEL: store_inline_imm_4.0_f16: 346; SI: ; %bb.0: 347; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 348; SI-NEXT: s_mov_b32 s3, 0xf000 349; SI-NEXT: s_mov_b32 s2, -1 350; SI-NEXT: v_mov_b32_e32 v0, 0x4400 351; SI-NEXT: s_waitcnt lgkmcnt(0) 352; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 353; SI-NEXT: s_endpgm 354 store half 4.0, half addrspace(1)* %out 355 ret void 356} 357 358define amdgpu_kernel void @store_inline_imm_m_4.0_f16(half addrspace(1)* %out) { 359; GFX10-LABEL: store_inline_imm_m_4.0_f16: 360; GFX10: ; %bb.0: 361; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xfa] 362; GFX10-NEXT: v_mov_b32_e32 v0, 0xffffc400 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0xc4,0xff,0xff] 363; GFX10-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x03,0x83,0xbe,0x00,0x60,0x01,0x31] 364; GFX10-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x03,0x82,0xbe] 365; GFX10-NEXT: ; implicit-def: $vcc_hi 366; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf] 367; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 368; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 369; 370; VI-LABEL: store_inline_imm_m_4.0_f16: 371; VI: ; %bb.0: 372; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x06,0xc0,0x00,0x00,0x00,0x00] 373; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11] 374; VI-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] 375; VI-NEXT: v_mov_b32_e32 v0, 0xffffc400 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0xc4,0xff,0xff] 376; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0x00,0x8c,0xbf] 377; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 378; VI-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 379; 380; SI-LABEL: store_inline_imm_m_4.0_f16: 381; SI: ; %bb.0: 382; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 383; SI-NEXT: s_mov_b32 s3, 0xf000 384; SI-NEXT: s_mov_b32 s2, -1 385; SI-NEXT: v_mov_b32_e32 v0, 0xc400 386; SI-NEXT: s_waitcnt lgkmcnt(0) 387; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 388; SI-NEXT: s_endpgm 389 store half -4.0, half addrspace(1)* %out 390 ret void 391} 392 393define amdgpu_kernel void @store_inline_imm_inv_2pi_f16(half addrspace(1)* %out) { 394; GFX10-LABEL: store_inline_imm_inv_2pi_f16: 395; GFX10: ; %bb.0: 396; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xfa] 397; GFX10-NEXT: v_mov_b32_e32 v0, 0x3118 ; encoding: [0xff,0x02,0x00,0x7e,0x18,0x31,0x00,0x00] 398; GFX10-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x03,0x83,0xbe,0x00,0x60,0x01,0x31] 399; GFX10-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x03,0x82,0xbe] 400; GFX10-NEXT: ; implicit-def: $vcc_hi 401; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf] 402; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 403; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 404; 405; VI-LABEL: store_inline_imm_inv_2pi_f16: 406; VI: ; %bb.0: 407; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x06,0xc0,0x00,0x00,0x00,0x00] 408; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11] 409; VI-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] 410; VI-NEXT: v_mov_b32_e32 v0, 0x3118 ; encoding: [0xff,0x02,0x00,0x7e,0x18,0x31,0x00,0x00] 411; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0x00,0x8c,0xbf] 412; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 413; VI-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 414; 415; SI-LABEL: store_inline_imm_inv_2pi_f16: 416; SI: ; %bb.0: 417; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 418; SI-NEXT: s_mov_b32 s3, 0xf000 419; SI-NEXT: s_mov_b32 s2, -1 420; SI-NEXT: v_mov_b32_e32 v0, 0x3118 421; SI-NEXT: s_waitcnt lgkmcnt(0) 422; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 423; SI-NEXT: s_endpgm 424 store half 0xH3118, half addrspace(1)* %out 425 ret void 426} 427 428define amdgpu_kernel void @store_inline_imm_m_inv_2pi_f16(half addrspace(1)* %out) { 429; GFX10-LABEL: store_inline_imm_m_inv_2pi_f16: 430; GFX10: ; %bb.0: 431; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xfa] 432; GFX10-NEXT: v_mov_b32_e32 v0, 0xffffb118 ; encoding: [0xff,0x02,0x00,0x7e,0x18,0xb1,0xff,0xff] 433; GFX10-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x03,0x83,0xbe,0x00,0x60,0x01,0x31] 434; GFX10-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x03,0x82,0xbe] 435; GFX10-NEXT: ; implicit-def: $vcc_hi 436; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf] 437; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 438; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 439; 440; VI-LABEL: store_inline_imm_m_inv_2pi_f16: 441; VI: ; %bb.0: 442; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x06,0xc0,0x00,0x00,0x00,0x00] 443; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11] 444; VI-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] 445; VI-NEXT: v_mov_b32_e32 v0, 0xffffb118 ; encoding: [0xff,0x02,0x00,0x7e,0x18,0xb1,0xff,0xff] 446; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0x00,0x8c,0xbf] 447; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 448; VI-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 449; 450; SI-LABEL: store_inline_imm_m_inv_2pi_f16: 451; SI: ; %bb.0: 452; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 453; SI-NEXT: s_mov_b32 s3, 0xf000 454; SI-NEXT: s_mov_b32 s2, -1 455; SI-NEXT: v_mov_b32_e32 v0, 0xb118 456; SI-NEXT: s_waitcnt lgkmcnt(0) 457; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 458; SI-NEXT: s_endpgm 459 store half 0xHB118, half addrspace(1)* %out 460 ret void 461} 462 463define amdgpu_kernel void @store_literal_imm_f16(half addrspace(1)* %out) { 464; GFX10-LABEL: store_literal_imm_f16: 465; GFX10: ; %bb.0: 466; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xfa] 467; GFX10-NEXT: v_mov_b32_e32 v0, 0x6c00 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x6c,0x00,0x00] 468; GFX10-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x03,0x83,0xbe,0x00,0x60,0x01,0x31] 469; GFX10-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x03,0x82,0xbe] 470; GFX10-NEXT: ; implicit-def: $vcc_hi 471; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf] 472; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 473; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 474; 475; VI-LABEL: store_literal_imm_f16: 476; VI: ; %bb.0: 477; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x06,0xc0,0x00,0x00,0x00,0x00] 478; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11] 479; VI-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] 480; VI-NEXT: v_mov_b32_e32 v0, 0x6c00 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x6c,0x00,0x00] 481; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0x00,0x8c,0xbf] 482; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 483; VI-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 484; 485; SI-LABEL: store_literal_imm_f16: 486; SI: ; %bb.0: 487; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 488; SI-NEXT: s_mov_b32 s3, 0xf000 489; SI-NEXT: s_mov_b32 s2, -1 490; SI-NEXT: v_mov_b32_e32 v0, 0x6c00 491; SI-NEXT: s_waitcnt lgkmcnt(0) 492; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 493; SI-NEXT: s_endpgm 494 store half 4096.0, half addrspace(1)* %out 495 ret void 496} 497 498define amdgpu_kernel void @add_inline_imm_0.0_f16(half addrspace(1)* %out, half %x) { 499; GFX10-LABEL: add_inline_imm_0.0_f16: 500; GFX10: ; %bb.0: 501; GFX10-NEXT: s_clause 0x1 ; encoding: [0x01,0x00,0xa1,0xbf] 502; GFX10-NEXT: s_load_dword s2, s[4:5], 0x8 ; encoding: [0x82,0x00,0x00,0xf4,0x08,0x00,0x00,0xfa] 503; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xfa] 504; GFX10-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x03,0x83,0xbe,0x00,0x60,0x01,0x31] 505; GFX10-NEXT: ; implicit-def: $vcc_hi 506; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf] 507; GFX10-NEXT: v_add_f16_e64 v0, s2, 0 ; encoding: [0x00,0x00,0x32,0xd5,0x02,0x00,0x01,0x00] 508; GFX10-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x03,0x82,0xbe] 509; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 510; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 511; 512; VI-LABEL: add_inline_imm_0.0_f16: 513; VI: ; %bb.0: 514; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x06,0xc0,0x00,0x00,0x00,0x00] 515; VI-NEXT: s_load_dword s4, s[4:5], 0x8 ; encoding: [0x02,0x01,0x02,0xc0,0x08,0x00,0x00,0x00] 516; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11] 517; VI-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] 518; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0x00,0x8c,0xbf] 519; VI-NEXT: v_add_f16_e64 v0, s4, 0 ; encoding: [0x00,0x00,0x1f,0xd1,0x04,0x00,0x01,0x00] 520; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 521; VI-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 522; 523; SI-LABEL: add_inline_imm_0.0_f16: 524; SI: ; %bb.0: 525; SI-NEXT: s_load_dword s2, s[0:1], 0xb 526; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 527; SI-NEXT: s_mov_b32 s3, 0xf000 528; SI-NEXT: s_waitcnt lgkmcnt(0) 529; SI-NEXT: v_cvt_f32_f16_e32 v0, s2 530; SI-NEXT: s_mov_b32 s2, -1 531; SI-NEXT: v_add_f32_e32 v0, 0, v0 532; SI-NEXT: v_cvt_f16_f32_e32 v0, v0 533; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 534; SI-NEXT: s_endpgm 535 %y = fadd half %x, 0.0 536 store half %y, half addrspace(1)* %out 537 ret void 538} 539 540define amdgpu_kernel void @add_inline_imm_0.5_f16(half addrspace(1)* %out, half %x) { 541; GFX10-LABEL: add_inline_imm_0.5_f16: 542; GFX10: ; %bb.0: 543; GFX10-NEXT: s_clause 0x1 ; encoding: [0x01,0x00,0xa1,0xbf] 544; GFX10-NEXT: s_load_dword s2, s[4:5], 0x8 ; encoding: [0x82,0x00,0x00,0xf4,0x08,0x00,0x00,0xfa] 545; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xfa] 546; GFX10-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x03,0x83,0xbe,0x00,0x60,0x01,0x31] 547; GFX10-NEXT: ; implicit-def: $vcc_hi 548; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf] 549; GFX10-NEXT: v_add_f16_e64 v0, s2, 0.5 ; encoding: [0x00,0x00,0x32,0xd5,0x02,0xe0,0x01,0x00] 550; GFX10-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x03,0x82,0xbe] 551; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 552; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 553; 554; VI-LABEL: add_inline_imm_0.5_f16: 555; VI: ; %bb.0: 556; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x06,0xc0,0x00,0x00,0x00,0x00] 557; VI-NEXT: s_load_dword s4, s[4:5], 0x8 ; encoding: [0x02,0x01,0x02,0xc0,0x08,0x00,0x00,0x00] 558; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11] 559; VI-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] 560; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0x00,0x8c,0xbf] 561; VI-NEXT: v_add_f16_e64 v0, s4, 0.5 ; encoding: [0x00,0x00,0x1f,0xd1,0x04,0xe0,0x01,0x00] 562; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 563; VI-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 564; 565; SI-LABEL: add_inline_imm_0.5_f16: 566; SI: ; %bb.0: 567; SI-NEXT: s_load_dword s2, s[0:1], 0xb 568; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 569; SI-NEXT: s_mov_b32 s3, 0xf000 570; SI-NEXT: s_waitcnt lgkmcnt(0) 571; SI-NEXT: v_cvt_f32_f16_e32 v0, s2 572; SI-NEXT: s_mov_b32 s2, -1 573; SI-NEXT: v_add_f32_e32 v0, 0.5, v0 574; SI-NEXT: v_cvt_f16_f32_e32 v0, v0 575; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 576; SI-NEXT: s_endpgm 577 %y = fadd half %x, 0.5 578 store half %y, half addrspace(1)* %out 579 ret void 580} 581 582define amdgpu_kernel void @add_inline_imm_neg_0.5_f16(half addrspace(1)* %out, half %x) { 583; GFX10-LABEL: add_inline_imm_neg_0.5_f16: 584; GFX10: ; %bb.0: 585; GFX10-NEXT: s_clause 0x1 ; encoding: [0x01,0x00,0xa1,0xbf] 586; GFX10-NEXT: s_load_dword s2, s[4:5], 0x8 ; encoding: [0x82,0x00,0x00,0xf4,0x08,0x00,0x00,0xfa] 587; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xfa] 588; GFX10-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x03,0x83,0xbe,0x00,0x60,0x01,0x31] 589; GFX10-NEXT: ; implicit-def: $vcc_hi 590; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf] 591; GFX10-NEXT: v_add_f16_e64 v0, s2, -0.5 ; encoding: [0x00,0x00,0x32,0xd5,0x02,0xe2,0x01,0x00] 592; GFX10-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x03,0x82,0xbe] 593; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 594; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 595; 596; VI-LABEL: add_inline_imm_neg_0.5_f16: 597; VI: ; %bb.0: 598; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x06,0xc0,0x00,0x00,0x00,0x00] 599; VI-NEXT: s_load_dword s4, s[4:5], 0x8 ; encoding: [0x02,0x01,0x02,0xc0,0x08,0x00,0x00,0x00] 600; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11] 601; VI-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] 602; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0x00,0x8c,0xbf] 603; VI-NEXT: v_add_f16_e64 v0, s4, -0.5 ; encoding: [0x00,0x00,0x1f,0xd1,0x04,0xe2,0x01,0x00] 604; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 605; VI-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 606; 607; SI-LABEL: add_inline_imm_neg_0.5_f16: 608; SI: ; %bb.0: 609; SI-NEXT: s_load_dword s2, s[0:1], 0xb 610; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 611; SI-NEXT: s_mov_b32 s3, 0xf000 612; SI-NEXT: s_waitcnt lgkmcnt(0) 613; SI-NEXT: v_cvt_f32_f16_e32 v0, s2 614; SI-NEXT: s_mov_b32 s2, -1 615; SI-NEXT: v_add_f32_e32 v0, -0.5, v0 616; SI-NEXT: v_cvt_f16_f32_e32 v0, v0 617; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 618; SI-NEXT: s_endpgm 619 %y = fadd half %x, -0.5 620 store half %y, half addrspace(1)* %out 621 ret void 622} 623 624define amdgpu_kernel void @add_inline_imm_1.0_f16(half addrspace(1)* %out, half %x) { 625; GFX10-LABEL: add_inline_imm_1.0_f16: 626; GFX10: ; %bb.0: 627; GFX10-NEXT: s_clause 0x1 ; encoding: [0x01,0x00,0xa1,0xbf] 628; GFX10-NEXT: s_load_dword s2, s[4:5], 0x8 ; encoding: [0x82,0x00,0x00,0xf4,0x08,0x00,0x00,0xfa] 629; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xfa] 630; GFX10-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x03,0x83,0xbe,0x00,0x60,0x01,0x31] 631; GFX10-NEXT: ; implicit-def: $vcc_hi 632; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf] 633; GFX10-NEXT: v_add_f16_e64 v0, s2, 1.0 ; encoding: [0x00,0x00,0x32,0xd5,0x02,0xe4,0x01,0x00] 634; GFX10-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x03,0x82,0xbe] 635; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 636; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 637; 638; VI-LABEL: add_inline_imm_1.0_f16: 639; VI: ; %bb.0: 640; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x06,0xc0,0x00,0x00,0x00,0x00] 641; VI-NEXT: s_load_dword s4, s[4:5], 0x8 ; encoding: [0x02,0x01,0x02,0xc0,0x08,0x00,0x00,0x00] 642; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11] 643; VI-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] 644; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0x00,0x8c,0xbf] 645; VI-NEXT: v_add_f16_e64 v0, s4, 1.0 ; encoding: [0x00,0x00,0x1f,0xd1,0x04,0xe4,0x01,0x00] 646; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 647; VI-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 648; 649; SI-LABEL: add_inline_imm_1.0_f16: 650; SI: ; %bb.0: 651; SI-NEXT: s_load_dword s2, s[0:1], 0xb 652; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 653; SI-NEXT: s_mov_b32 s3, 0xf000 654; SI-NEXT: s_waitcnt lgkmcnt(0) 655; SI-NEXT: v_cvt_f32_f16_e32 v0, s2 656; SI-NEXT: s_mov_b32 s2, -1 657; SI-NEXT: v_add_f32_e32 v0, 1.0, v0 658; SI-NEXT: v_cvt_f16_f32_e32 v0, v0 659; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 660; SI-NEXT: s_endpgm 661 %y = fadd half %x, 1.0 662 store half %y, half addrspace(1)* %out 663 ret void 664} 665 666define amdgpu_kernel void @add_inline_imm_neg_1.0_f16(half addrspace(1)* %out, half %x) { 667; GFX10-LABEL: add_inline_imm_neg_1.0_f16: 668; GFX10: ; %bb.0: 669; GFX10-NEXT: s_clause 0x1 ; encoding: [0x01,0x00,0xa1,0xbf] 670; GFX10-NEXT: s_load_dword s2, s[4:5], 0x8 ; encoding: [0x82,0x00,0x00,0xf4,0x08,0x00,0x00,0xfa] 671; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xfa] 672; GFX10-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x03,0x83,0xbe,0x00,0x60,0x01,0x31] 673; GFX10-NEXT: ; implicit-def: $vcc_hi 674; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf] 675; GFX10-NEXT: v_add_f16_e64 v0, s2, -1.0 ; encoding: [0x00,0x00,0x32,0xd5,0x02,0xe6,0x01,0x00] 676; GFX10-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x03,0x82,0xbe] 677; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 678; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 679; 680; VI-LABEL: add_inline_imm_neg_1.0_f16: 681; VI: ; %bb.0: 682; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x06,0xc0,0x00,0x00,0x00,0x00] 683; VI-NEXT: s_load_dword s4, s[4:5], 0x8 ; encoding: [0x02,0x01,0x02,0xc0,0x08,0x00,0x00,0x00] 684; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11] 685; VI-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] 686; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0x00,0x8c,0xbf] 687; VI-NEXT: v_add_f16_e64 v0, s4, -1.0 ; encoding: [0x00,0x00,0x1f,0xd1,0x04,0xe6,0x01,0x00] 688; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 689; VI-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 690; 691; SI-LABEL: add_inline_imm_neg_1.0_f16: 692; SI: ; %bb.0: 693; SI-NEXT: s_load_dword s2, s[0:1], 0xb 694; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 695; SI-NEXT: s_mov_b32 s3, 0xf000 696; SI-NEXT: s_waitcnt lgkmcnt(0) 697; SI-NEXT: v_cvt_f32_f16_e32 v0, s2 698; SI-NEXT: s_mov_b32 s2, -1 699; SI-NEXT: v_add_f32_e32 v0, -1.0, v0 700; SI-NEXT: v_cvt_f16_f32_e32 v0, v0 701; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 702; SI-NEXT: s_endpgm 703 %y = fadd half %x, -1.0 704 store half %y, half addrspace(1)* %out 705 ret void 706} 707 708define amdgpu_kernel void @add_inline_imm_2.0_f16(half addrspace(1)* %out, half %x) { 709; GFX10-LABEL: add_inline_imm_2.0_f16: 710; GFX10: ; %bb.0: 711; GFX10-NEXT: s_clause 0x1 ; encoding: [0x01,0x00,0xa1,0xbf] 712; GFX10-NEXT: s_load_dword s2, s[4:5], 0x8 ; encoding: [0x82,0x00,0x00,0xf4,0x08,0x00,0x00,0xfa] 713; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xfa] 714; GFX10-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x03,0x83,0xbe,0x00,0x60,0x01,0x31] 715; GFX10-NEXT: ; implicit-def: $vcc_hi 716; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf] 717; GFX10-NEXT: v_add_f16_e64 v0, s2, 2.0 ; encoding: [0x00,0x00,0x32,0xd5,0x02,0xe8,0x01,0x00] 718; GFX10-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x03,0x82,0xbe] 719; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 720; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 721; 722; VI-LABEL: add_inline_imm_2.0_f16: 723; VI: ; %bb.0: 724; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x06,0xc0,0x00,0x00,0x00,0x00] 725; VI-NEXT: s_load_dword s4, s[4:5], 0x8 ; encoding: [0x02,0x01,0x02,0xc0,0x08,0x00,0x00,0x00] 726; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11] 727; VI-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] 728; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0x00,0x8c,0xbf] 729; VI-NEXT: v_add_f16_e64 v0, s4, 2.0 ; encoding: [0x00,0x00,0x1f,0xd1,0x04,0xe8,0x01,0x00] 730; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 731; VI-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 732; 733; SI-LABEL: add_inline_imm_2.0_f16: 734; SI: ; %bb.0: 735; SI-NEXT: s_load_dword s2, s[0:1], 0xb 736; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 737; SI-NEXT: s_mov_b32 s3, 0xf000 738; SI-NEXT: s_waitcnt lgkmcnt(0) 739; SI-NEXT: v_cvt_f32_f16_e32 v0, s2 740; SI-NEXT: s_mov_b32 s2, -1 741; SI-NEXT: v_add_f32_e32 v0, 2.0, v0 742; SI-NEXT: v_cvt_f16_f32_e32 v0, v0 743; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 744; SI-NEXT: s_endpgm 745 %y = fadd half %x, 2.0 746 store half %y, half addrspace(1)* %out 747 ret void 748} 749 750define amdgpu_kernel void @add_inline_imm_neg_2.0_f16(half addrspace(1)* %out, half %x) { 751; GFX10-LABEL: add_inline_imm_neg_2.0_f16: 752; GFX10: ; %bb.0: 753; GFX10-NEXT: s_clause 0x1 ; encoding: [0x01,0x00,0xa1,0xbf] 754; GFX10-NEXT: s_load_dword s2, s[4:5], 0x8 ; encoding: [0x82,0x00,0x00,0xf4,0x08,0x00,0x00,0xfa] 755; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xfa] 756; GFX10-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x03,0x83,0xbe,0x00,0x60,0x01,0x31] 757; GFX10-NEXT: ; implicit-def: $vcc_hi 758; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf] 759; GFX10-NEXT: v_add_f16_e64 v0, s2, -2.0 ; encoding: [0x00,0x00,0x32,0xd5,0x02,0xea,0x01,0x00] 760; GFX10-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x03,0x82,0xbe] 761; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 762; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 763; 764; VI-LABEL: add_inline_imm_neg_2.0_f16: 765; VI: ; %bb.0: 766; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x06,0xc0,0x00,0x00,0x00,0x00] 767; VI-NEXT: s_load_dword s4, s[4:5], 0x8 ; encoding: [0x02,0x01,0x02,0xc0,0x08,0x00,0x00,0x00] 768; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11] 769; VI-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] 770; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0x00,0x8c,0xbf] 771; VI-NEXT: v_add_f16_e64 v0, s4, -2.0 ; encoding: [0x00,0x00,0x1f,0xd1,0x04,0xea,0x01,0x00] 772; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 773; VI-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 774; 775; SI-LABEL: add_inline_imm_neg_2.0_f16: 776; SI: ; %bb.0: 777; SI-NEXT: s_load_dword s2, s[0:1], 0xb 778; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 779; SI-NEXT: s_mov_b32 s3, 0xf000 780; SI-NEXT: s_waitcnt lgkmcnt(0) 781; SI-NEXT: v_cvt_f32_f16_e32 v0, s2 782; SI-NEXT: s_mov_b32 s2, -1 783; SI-NEXT: v_add_f32_e32 v0, -2.0, v0 784; SI-NEXT: v_cvt_f16_f32_e32 v0, v0 785; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 786; SI-NEXT: s_endpgm 787 %y = fadd half %x, -2.0 788 store half %y, half addrspace(1)* %out 789 ret void 790} 791 792define amdgpu_kernel void @add_inline_imm_4.0_f16(half addrspace(1)* %out, half %x) { 793; GFX10-LABEL: add_inline_imm_4.0_f16: 794; GFX10: ; %bb.0: 795; GFX10-NEXT: s_clause 0x1 ; encoding: [0x01,0x00,0xa1,0xbf] 796; GFX10-NEXT: s_load_dword s2, s[4:5], 0x8 ; encoding: [0x82,0x00,0x00,0xf4,0x08,0x00,0x00,0xfa] 797; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xfa] 798; GFX10-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x03,0x83,0xbe,0x00,0x60,0x01,0x31] 799; GFX10-NEXT: ; implicit-def: $vcc_hi 800; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf] 801; GFX10-NEXT: v_add_f16_e64 v0, s2, 4.0 ; encoding: [0x00,0x00,0x32,0xd5,0x02,0xec,0x01,0x00] 802; GFX10-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x03,0x82,0xbe] 803; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 804; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 805; 806; VI-LABEL: add_inline_imm_4.0_f16: 807; VI: ; %bb.0: 808; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x06,0xc0,0x00,0x00,0x00,0x00] 809; VI-NEXT: s_load_dword s4, s[4:5], 0x8 ; encoding: [0x02,0x01,0x02,0xc0,0x08,0x00,0x00,0x00] 810; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11] 811; VI-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] 812; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0x00,0x8c,0xbf] 813; VI-NEXT: v_add_f16_e64 v0, s4, 4.0 ; encoding: [0x00,0x00,0x1f,0xd1,0x04,0xec,0x01,0x00] 814; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 815; VI-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 816; 817; SI-LABEL: add_inline_imm_4.0_f16: 818; SI: ; %bb.0: 819; SI-NEXT: s_load_dword s2, s[0:1], 0xb 820; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 821; SI-NEXT: s_mov_b32 s3, 0xf000 822; SI-NEXT: s_waitcnt lgkmcnt(0) 823; SI-NEXT: v_cvt_f32_f16_e32 v0, s2 824; SI-NEXT: s_mov_b32 s2, -1 825; SI-NEXT: v_add_f32_e32 v0, 4.0, v0 826; SI-NEXT: v_cvt_f16_f32_e32 v0, v0 827; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 828; SI-NEXT: s_endpgm 829 %y = fadd half %x, 4.0 830 store half %y, half addrspace(1)* %out 831 ret void 832} 833 834define amdgpu_kernel void @add_inline_imm_neg_4.0_f16(half addrspace(1)* %out, half %x) { 835; GFX10-LABEL: add_inline_imm_neg_4.0_f16: 836; GFX10: ; %bb.0: 837; GFX10-NEXT: s_clause 0x1 ; encoding: [0x01,0x00,0xa1,0xbf] 838; GFX10-NEXT: s_load_dword s2, s[4:5], 0x8 ; encoding: [0x82,0x00,0x00,0xf4,0x08,0x00,0x00,0xfa] 839; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xfa] 840; GFX10-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x03,0x83,0xbe,0x00,0x60,0x01,0x31] 841; GFX10-NEXT: ; implicit-def: $vcc_hi 842; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf] 843; GFX10-NEXT: v_add_f16_e64 v0, s2, -4.0 ; encoding: [0x00,0x00,0x32,0xd5,0x02,0xee,0x01,0x00] 844; GFX10-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x03,0x82,0xbe] 845; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 846; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 847; 848; VI-LABEL: add_inline_imm_neg_4.0_f16: 849; VI: ; %bb.0: 850; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x06,0xc0,0x00,0x00,0x00,0x00] 851; VI-NEXT: s_load_dword s4, s[4:5], 0x8 ; encoding: [0x02,0x01,0x02,0xc0,0x08,0x00,0x00,0x00] 852; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11] 853; VI-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] 854; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0x00,0x8c,0xbf] 855; VI-NEXT: v_add_f16_e64 v0, s4, -4.0 ; encoding: [0x00,0x00,0x1f,0xd1,0x04,0xee,0x01,0x00] 856; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 857; VI-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 858; 859; SI-LABEL: add_inline_imm_neg_4.0_f16: 860; SI: ; %bb.0: 861; SI-NEXT: s_load_dword s2, s[0:1], 0xb 862; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 863; SI-NEXT: s_mov_b32 s3, 0xf000 864; SI-NEXT: s_waitcnt lgkmcnt(0) 865; SI-NEXT: v_cvt_f32_f16_e32 v0, s2 866; SI-NEXT: s_mov_b32 s2, -1 867; SI-NEXT: v_add_f32_e32 v0, -4.0, v0 868; SI-NEXT: v_cvt_f16_f32_e32 v0, v0 869; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 870; SI-NEXT: s_endpgm 871 %y = fadd half %x, -4.0 872 store half %y, half addrspace(1)* %out 873 ret void 874} 875 876define amdgpu_kernel void @commute_add_inline_imm_0.5_f16(half addrspace(1)* %out, half addrspace(1)* %in) { 877; GFX10-LABEL: commute_add_inline_imm_0.5_f16: 878; GFX10: ; %bb.0: 879; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; encoding: [0x02,0x00,0x08,0xf4,0x00,0x00,0x00,0xfa] 880; GFX10-NEXT: s_mov_b32 s6, -1 ; encoding: [0xc1,0x03,0x86,0xbe] 881; GFX10-NEXT: s_mov_b32 s7, 0x31016000 ; encoding: [0xff,0x03,0x87,0xbe,0x00,0x60,0x01,0x31] 882; GFX10-NEXT: s_mov_b32 s10, s6 ; encoding: [0x06,0x03,0x8a,0xbe] 883; GFX10-NEXT: s_mov_b32 s11, s7 ; encoding: [0x07,0x03,0x8b,0xbe] 884; GFX10-NEXT: ; implicit-def: $vcc_hi 885; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf] 886; GFX10-NEXT: s_mov_b32 s8, s2 ; encoding: [0x02,0x03,0x88,0xbe] 887; GFX10-NEXT: s_mov_b32 s9, s3 ; encoding: [0x03,0x03,0x89,0xbe] 888; GFX10-NEXT: s_mov_b32 s4, s0 ; encoding: [0x00,0x03,0x84,0xbe] 889; GFX10-NEXT: buffer_load_ushort v0, off, s[8:11], 0 ; encoding: [0x00,0x00,0x28,0xe0,0x00,0x00,0x02,0x80] 890; GFX10-NEXT: s_mov_b32 s5, s1 ; encoding: [0x01,0x03,0x85,0xbe] 891; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf] 892; GFX10-NEXT: v_add_f16_e32 v0, 0.5, v0 ; encoding: [0xf0,0x00,0x00,0x64] 893; GFX10-NEXT: buffer_store_short v0, off, s[4:7], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x01,0x80] 894; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 895; 896; VI-LABEL: commute_add_inline_imm_0.5_f16: 897; VI: ; %bb.0: 898; VI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0 ; encoding: [0x02,0x01,0x0a,0xc0,0x00,0x00,0x00,0x00] 899; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11] 900; VI-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] 901; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0x00,0x8c,0xbf] 902; VI-NEXT: s_mov_b32 s0, s4 ; encoding: [0x04,0x00,0x80,0xbe] 903; VI-NEXT: s_mov_b32 s1, s5 ; encoding: [0x05,0x00,0x81,0xbe] 904; VI-NEXT: s_mov_b32 s4, s6 ; encoding: [0x06,0x00,0x84,0xbe] 905; VI-NEXT: s_mov_b32 s5, s7 ; encoding: [0x07,0x00,0x85,0xbe] 906; VI-NEXT: s_mov_b32 s6, s2 ; encoding: [0x02,0x00,0x86,0xbe] 907; VI-NEXT: s_mov_b32 s7, s3 ; encoding: [0x03,0x00,0x87,0xbe] 908; VI-NEXT: buffer_load_ushort v0, off, s[4:7], 0 ; encoding: [0x00,0x00,0x48,0xe0,0x00,0x00,0x01,0x80] 909; VI-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf] 910; VI-NEXT: v_add_f16_e32 v0, 0.5, v0 ; encoding: [0xf0,0x00,0x00,0x3e] 911; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 912; VI-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 913; 914; SI-LABEL: commute_add_inline_imm_0.5_f16: 915; SI: ; %bb.0: 916; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 917; SI-NEXT: s_mov_b32 s3, 0xf000 918; SI-NEXT: s_mov_b32 s2, -1 919; SI-NEXT: s_mov_b32 s10, s2 920; SI-NEXT: s_mov_b32 s11, s3 921; SI-NEXT: s_waitcnt lgkmcnt(0) 922; SI-NEXT: s_mov_b32 s8, s6 923; SI-NEXT: s_mov_b32 s9, s7 924; SI-NEXT: buffer_load_ushort v0, off, s[8:11], 0 925; SI-NEXT: s_mov_b32 s0, s4 926; SI-NEXT: s_mov_b32 s1, s5 927; SI-NEXT: s_waitcnt vmcnt(0) 928; SI-NEXT: v_cvt_f32_f16_e32 v0, v0 929; SI-NEXT: v_add_f32_e32 v0, 0.5, v0 930; SI-NEXT: v_cvt_f16_f32_e32 v0, v0 931; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 932; SI-NEXT: s_endpgm 933 %x = load half, half addrspace(1)* %in 934 %y = fadd half %x, 0.5 935 store half %y, half addrspace(1)* %out 936 ret void 937} 938 939define amdgpu_kernel void @commute_add_literal_f16(half addrspace(1)* %out, half addrspace(1)* %in) { 940; GFX10-LABEL: commute_add_literal_f16: 941; GFX10: ; %bb.0: 942; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; encoding: [0x02,0x00,0x08,0xf4,0x00,0x00,0x00,0xfa] 943; GFX10-NEXT: s_mov_b32 s6, -1 ; encoding: [0xc1,0x03,0x86,0xbe] 944; GFX10-NEXT: s_mov_b32 s7, 0x31016000 ; encoding: [0xff,0x03,0x87,0xbe,0x00,0x60,0x01,0x31] 945; GFX10-NEXT: s_mov_b32 s10, s6 ; encoding: [0x06,0x03,0x8a,0xbe] 946; GFX10-NEXT: s_mov_b32 s11, s7 ; encoding: [0x07,0x03,0x8b,0xbe] 947; GFX10-NEXT: ; implicit-def: $vcc_hi 948; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf] 949; GFX10-NEXT: s_mov_b32 s8, s2 ; encoding: [0x02,0x03,0x88,0xbe] 950; GFX10-NEXT: s_mov_b32 s9, s3 ; encoding: [0x03,0x03,0x89,0xbe] 951; GFX10-NEXT: s_mov_b32 s4, s0 ; encoding: [0x00,0x03,0x84,0xbe] 952; GFX10-NEXT: buffer_load_ushort v0, off, s[8:11], 0 ; encoding: [0x00,0x00,0x28,0xe0,0x00,0x00,0x02,0x80] 953; GFX10-NEXT: s_mov_b32 s5, s1 ; encoding: [0x01,0x03,0x85,0xbe] 954; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf] 955; GFX10-NEXT: v_add_f16_e32 v0, 0x6400, v0 ; encoding: [0xff,0x00,0x00,0x64,0x00,0x64,0x00,0x00] 956; GFX10-NEXT: buffer_store_short v0, off, s[4:7], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x01,0x80] 957; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 958; 959; VI-LABEL: commute_add_literal_f16: 960; VI: ; %bb.0: 961; VI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0 ; encoding: [0x02,0x01,0x0a,0xc0,0x00,0x00,0x00,0x00] 962; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11] 963; VI-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] 964; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0x00,0x8c,0xbf] 965; VI-NEXT: s_mov_b32 s0, s4 ; encoding: [0x04,0x00,0x80,0xbe] 966; VI-NEXT: s_mov_b32 s1, s5 ; encoding: [0x05,0x00,0x81,0xbe] 967; VI-NEXT: s_mov_b32 s4, s6 ; encoding: [0x06,0x00,0x84,0xbe] 968; VI-NEXT: s_mov_b32 s5, s7 ; encoding: [0x07,0x00,0x85,0xbe] 969; VI-NEXT: s_mov_b32 s6, s2 ; encoding: [0x02,0x00,0x86,0xbe] 970; VI-NEXT: s_mov_b32 s7, s3 ; encoding: [0x03,0x00,0x87,0xbe] 971; VI-NEXT: buffer_load_ushort v0, off, s[4:7], 0 ; encoding: [0x00,0x00,0x48,0xe0,0x00,0x00,0x01,0x80] 972; VI-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf] 973; VI-NEXT: v_add_f16_e32 v0, 0x6400, v0 ; encoding: [0xff,0x00,0x00,0x3e,0x00,0x64,0x00,0x00] 974; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 975; VI-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 976; 977; SI-LABEL: commute_add_literal_f16: 978; SI: ; %bb.0: 979; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 980; SI-NEXT: s_mov_b32 s3, 0xf000 981; SI-NEXT: s_mov_b32 s2, -1 982; SI-NEXT: s_mov_b32 s10, s2 983; SI-NEXT: s_mov_b32 s11, s3 984; SI-NEXT: s_waitcnt lgkmcnt(0) 985; SI-NEXT: s_mov_b32 s8, s6 986; SI-NEXT: s_mov_b32 s9, s7 987; SI-NEXT: buffer_load_ushort v0, off, s[8:11], 0 988; SI-NEXT: s_mov_b32 s0, s4 989; SI-NEXT: s_mov_b32 s1, s5 990; SI-NEXT: s_waitcnt vmcnt(0) 991; SI-NEXT: v_cvt_f32_f16_e32 v0, v0 992; SI-NEXT: v_add_f32_e32 v0, 0x44800000, v0 993; SI-NEXT: v_cvt_f16_f32_e32 v0, v0 994; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 995; SI-NEXT: s_endpgm 996 %x = load half, half addrspace(1)* %in 997 %y = fadd half %x, 1024.0 998 store half %y, half addrspace(1)* %out 999 ret void 1000} 1001 1002define amdgpu_kernel void @add_inline_imm_1_f16(half addrspace(1)* %out, half %x) { 1003; GFX10-LABEL: add_inline_imm_1_f16: 1004; GFX10: ; %bb.0: 1005; GFX10-NEXT: s_clause 0x1 ; encoding: [0x01,0x00,0xa1,0xbf] 1006; GFX10-NEXT: s_load_dword s2, s[4:5], 0x8 ; encoding: [0x82,0x00,0x00,0xf4,0x08,0x00,0x00,0xfa] 1007; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xfa] 1008; GFX10-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x03,0x83,0xbe,0x00,0x60,0x01,0x31] 1009; GFX10-NEXT: ; implicit-def: $vcc_hi 1010; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf] 1011; GFX10-NEXT: v_add_f16_e64 v0, s2, 1 ; encoding: [0x00,0x00,0x32,0xd5,0x02,0x02,0x01,0x00] 1012; GFX10-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x03,0x82,0xbe] 1013; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 1014; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 1015; 1016; VI-LABEL: add_inline_imm_1_f16: 1017; VI: ; %bb.0: 1018; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x06,0xc0,0x00,0x00,0x00,0x00] 1019; VI-NEXT: s_load_dword s4, s[4:5], 0x8 ; encoding: [0x02,0x01,0x02,0xc0,0x08,0x00,0x00,0x00] 1020; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11] 1021; VI-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] 1022; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0x00,0x8c,0xbf] 1023; VI-NEXT: v_add_f16_e64 v0, s4, 1 ; encoding: [0x00,0x00,0x1f,0xd1,0x04,0x02,0x01,0x00] 1024; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 1025; VI-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 1026; 1027; SI-LABEL: add_inline_imm_1_f16: 1028; SI: ; %bb.0: 1029; SI-NEXT: s_load_dword s2, s[0:1], 0xb 1030; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 1031; SI-NEXT: s_mov_b32 s3, 0xf000 1032; SI-NEXT: s_waitcnt lgkmcnt(0) 1033; SI-NEXT: v_cvt_f32_f16_e32 v0, s2 1034; SI-NEXT: s_mov_b32 s2, -1 1035; SI-NEXT: v_add_f32_e32 v0, 0x33800000, v0 1036; SI-NEXT: v_cvt_f16_f32_e32 v0, v0 1037; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 1038; SI-NEXT: s_endpgm 1039 %y = fadd half %x, 0xH0001 1040 store half %y, half addrspace(1)* %out 1041 ret void 1042} 1043 1044define amdgpu_kernel void @add_inline_imm_2_f16(half addrspace(1)* %out, half %x) { 1045; GFX10-LABEL: add_inline_imm_2_f16: 1046; GFX10: ; %bb.0: 1047; GFX10-NEXT: s_clause 0x1 ; encoding: [0x01,0x00,0xa1,0xbf] 1048; GFX10-NEXT: s_load_dword s2, s[4:5], 0x8 ; encoding: [0x82,0x00,0x00,0xf4,0x08,0x00,0x00,0xfa] 1049; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xfa] 1050; GFX10-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x03,0x83,0xbe,0x00,0x60,0x01,0x31] 1051; GFX10-NEXT: ; implicit-def: $vcc_hi 1052; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf] 1053; GFX10-NEXT: v_add_f16_e64 v0, s2, 2 ; encoding: [0x00,0x00,0x32,0xd5,0x02,0x04,0x01,0x00] 1054; GFX10-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x03,0x82,0xbe] 1055; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 1056; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 1057; 1058; VI-LABEL: add_inline_imm_2_f16: 1059; VI: ; %bb.0: 1060; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x06,0xc0,0x00,0x00,0x00,0x00] 1061; VI-NEXT: s_load_dword s4, s[4:5], 0x8 ; encoding: [0x02,0x01,0x02,0xc0,0x08,0x00,0x00,0x00] 1062; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11] 1063; VI-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] 1064; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0x00,0x8c,0xbf] 1065; VI-NEXT: v_add_f16_e64 v0, s4, 2 ; encoding: [0x00,0x00,0x1f,0xd1,0x04,0x04,0x01,0x00] 1066; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 1067; VI-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 1068; 1069; SI-LABEL: add_inline_imm_2_f16: 1070; SI: ; %bb.0: 1071; SI-NEXT: s_load_dword s2, s[0:1], 0xb 1072; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 1073; SI-NEXT: s_mov_b32 s3, 0xf000 1074; SI-NEXT: s_waitcnt lgkmcnt(0) 1075; SI-NEXT: v_cvt_f32_f16_e32 v0, s2 1076; SI-NEXT: s_mov_b32 s2, -1 1077; SI-NEXT: v_add_f32_e32 v0, 0x34000000, v0 1078; SI-NEXT: v_cvt_f16_f32_e32 v0, v0 1079; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 1080; SI-NEXT: s_endpgm 1081 %y = fadd half %x, 0xH0002 1082 store half %y, half addrspace(1)* %out 1083 ret void 1084} 1085 1086define amdgpu_kernel void @add_inline_imm_16_f16(half addrspace(1)* %out, half %x) { 1087; GFX10-LABEL: add_inline_imm_16_f16: 1088; GFX10: ; %bb.0: 1089; GFX10-NEXT: s_clause 0x1 ; encoding: [0x01,0x00,0xa1,0xbf] 1090; GFX10-NEXT: s_load_dword s2, s[4:5], 0x8 ; encoding: [0x82,0x00,0x00,0xf4,0x08,0x00,0x00,0xfa] 1091; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xfa] 1092; GFX10-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x03,0x83,0xbe,0x00,0x60,0x01,0x31] 1093; GFX10-NEXT: ; implicit-def: $vcc_hi 1094; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf] 1095; GFX10-NEXT: v_add_f16_e64 v0, s2, 16 ; encoding: [0x00,0x00,0x32,0xd5,0x02,0x20,0x01,0x00] 1096; GFX10-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x03,0x82,0xbe] 1097; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 1098; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 1099; 1100; VI-LABEL: add_inline_imm_16_f16: 1101; VI: ; %bb.0: 1102; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x06,0xc0,0x00,0x00,0x00,0x00] 1103; VI-NEXT: s_load_dword s4, s[4:5], 0x8 ; encoding: [0x02,0x01,0x02,0xc0,0x08,0x00,0x00,0x00] 1104; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11] 1105; VI-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] 1106; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0x00,0x8c,0xbf] 1107; VI-NEXT: v_add_f16_e64 v0, s4, 16 ; encoding: [0x00,0x00,0x1f,0xd1,0x04,0x20,0x01,0x00] 1108; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 1109; VI-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 1110; 1111; SI-LABEL: add_inline_imm_16_f16: 1112; SI: ; %bb.0: 1113; SI-NEXT: s_load_dword s2, s[0:1], 0xb 1114; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 1115; SI-NEXT: s_mov_b32 s3, 0xf000 1116; SI-NEXT: s_waitcnt lgkmcnt(0) 1117; SI-NEXT: v_cvt_f32_f16_e32 v0, s2 1118; SI-NEXT: s_mov_b32 s2, -1 1119; SI-NEXT: v_add_f32_e32 v0, 0x35800000, v0 1120; SI-NEXT: v_cvt_f16_f32_e32 v0, v0 1121; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 1122; SI-NEXT: s_endpgm 1123 %y = fadd half %x, 0xH0010 1124 store half %y, half addrspace(1)* %out 1125 ret void 1126} 1127 1128define amdgpu_kernel void @add_inline_imm_neg_1_f16(half addrspace(1)* %out, i16 addrspace(1)* %in) { 1129; GFX10-LABEL: add_inline_imm_neg_1_f16: 1130; GFX10: ; %bb.0: 1131; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; encoding: [0x02,0x00,0x08,0xf4,0x00,0x00,0x00,0xfa] 1132; GFX10-NEXT: s_mov_b32 s6, -1 ; encoding: [0xc1,0x03,0x86,0xbe] 1133; GFX10-NEXT: s_mov_b32 s7, 0x31016000 ; encoding: [0xff,0x03,0x87,0xbe,0x00,0x60,0x01,0x31] 1134; GFX10-NEXT: s_mov_b32 s10, s6 ; encoding: [0x06,0x03,0x8a,0xbe] 1135; GFX10-NEXT: s_mov_b32 s11, s7 ; encoding: [0x07,0x03,0x8b,0xbe] 1136; GFX10-NEXT: ; implicit-def: $vcc_hi 1137; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf] 1138; GFX10-NEXT: s_mov_b32 s8, s2 ; encoding: [0x02,0x03,0x88,0xbe] 1139; GFX10-NEXT: s_mov_b32 s9, s3 ; encoding: [0x03,0x03,0x89,0xbe] 1140; GFX10-NEXT: s_mov_b32 s4, s0 ; encoding: [0x00,0x03,0x84,0xbe] 1141; GFX10-NEXT: buffer_load_ushort v0, off, s[8:11], 0 ; encoding: [0x00,0x00,0x28,0xe0,0x00,0x00,0x02,0x80] 1142; GFX10-NEXT: s_mov_b32 s5, s1 ; encoding: [0x01,0x03,0x85,0xbe] 1143; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf] 1144; GFX10-NEXT: v_add_nc_u16_e64 v0, v0, -1 ; encoding: [0x00,0x00,0x03,0xd7,0x00,0x83,0x01,0x00] 1145; GFX10-NEXT: buffer_store_short v0, off, s[4:7], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x01,0x80] 1146; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 1147; 1148; VI-LABEL: add_inline_imm_neg_1_f16: 1149; VI: ; %bb.0: 1150; VI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0 ; encoding: [0x02,0x01,0x0a,0xc0,0x00,0x00,0x00,0x00] 1151; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11] 1152; VI-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] 1153; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0x00,0x8c,0xbf] 1154; VI-NEXT: s_mov_b32 s0, s4 ; encoding: [0x04,0x00,0x80,0xbe] 1155; VI-NEXT: s_mov_b32 s1, s5 ; encoding: [0x05,0x00,0x81,0xbe] 1156; VI-NEXT: s_mov_b32 s4, s6 ; encoding: [0x06,0x00,0x84,0xbe] 1157; VI-NEXT: s_mov_b32 s5, s7 ; encoding: [0x07,0x00,0x85,0xbe] 1158; VI-NEXT: s_mov_b32 s6, s2 ; encoding: [0x02,0x00,0x86,0xbe] 1159; VI-NEXT: s_mov_b32 s7, s3 ; encoding: [0x03,0x00,0x87,0xbe] 1160; VI-NEXT: buffer_load_ushort v0, off, s[4:7], 0 ; encoding: [0x00,0x00,0x48,0xe0,0x00,0x00,0x01,0x80] 1161; VI-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf] 1162; VI-NEXT: v_add_u16_e32 v0, -1, v0 ; encoding: [0xc1,0x00,0x00,0x4c] 1163; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 1164; VI-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 1165; 1166; SI-LABEL: add_inline_imm_neg_1_f16: 1167; SI: ; %bb.0: 1168; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 1169; SI-NEXT: s_mov_b32 s3, 0xf000 1170; SI-NEXT: s_mov_b32 s2, -1 1171; SI-NEXT: s_waitcnt lgkmcnt(0) 1172; SI-NEXT: s_mov_b32 s0, s4 1173; SI-NEXT: s_mov_b32 s1, s5 1174; SI-NEXT: s_mov_b32 s4, s6 1175; SI-NEXT: s_mov_b32 s5, s7 1176; SI-NEXT: s_mov_b32 s6, s2 1177; SI-NEXT: s_mov_b32 s7, s3 1178; SI-NEXT: buffer_load_ushort v0, off, s[4:7], 0 1179; SI-NEXT: s_waitcnt vmcnt(0) 1180; SI-NEXT: v_add_i32_e32 v0, vcc, -1, v0 1181; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 1182; SI-NEXT: s_endpgm 1183 %x = load i16, i16 addrspace(1)* %in 1184 %y = add i16 %x, -1 1185 %ybc = bitcast i16 %y to half 1186 store half %ybc, half addrspace(1)* %out 1187 ret void 1188} 1189 1190define amdgpu_kernel void @add_inline_imm_neg_2_f16(half addrspace(1)* %out, i16 addrspace(1)* %in) { 1191; GFX10-LABEL: add_inline_imm_neg_2_f16: 1192; GFX10: ; %bb.0: 1193; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; encoding: [0x02,0x00,0x08,0xf4,0x00,0x00,0x00,0xfa] 1194; GFX10-NEXT: s_mov_b32 s6, -1 ; encoding: [0xc1,0x03,0x86,0xbe] 1195; GFX10-NEXT: s_mov_b32 s7, 0x31016000 ; encoding: [0xff,0x03,0x87,0xbe,0x00,0x60,0x01,0x31] 1196; GFX10-NEXT: s_mov_b32 s10, s6 ; encoding: [0x06,0x03,0x8a,0xbe] 1197; GFX10-NEXT: s_mov_b32 s11, s7 ; encoding: [0x07,0x03,0x8b,0xbe] 1198; GFX10-NEXT: ; implicit-def: $vcc_hi 1199; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf] 1200; GFX10-NEXT: s_mov_b32 s8, s2 ; encoding: [0x02,0x03,0x88,0xbe] 1201; GFX10-NEXT: s_mov_b32 s9, s3 ; encoding: [0x03,0x03,0x89,0xbe] 1202; GFX10-NEXT: s_mov_b32 s4, s0 ; encoding: [0x00,0x03,0x84,0xbe] 1203; GFX10-NEXT: buffer_load_ushort v0, off, s[8:11], 0 ; encoding: [0x00,0x00,0x28,0xe0,0x00,0x00,0x02,0x80] 1204; GFX10-NEXT: s_mov_b32 s5, s1 ; encoding: [0x01,0x03,0x85,0xbe] 1205; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf] 1206; GFX10-NEXT: v_add_nc_u16_e64 v0, v0, -2 ; encoding: [0x00,0x00,0x03,0xd7,0x00,0x85,0x01,0x00] 1207; GFX10-NEXT: buffer_store_short v0, off, s[4:7], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x01,0x80] 1208; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 1209; 1210; VI-LABEL: add_inline_imm_neg_2_f16: 1211; VI: ; %bb.0: 1212; VI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0 ; encoding: [0x02,0x01,0x0a,0xc0,0x00,0x00,0x00,0x00] 1213; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11] 1214; VI-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] 1215; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0x00,0x8c,0xbf] 1216; VI-NEXT: s_mov_b32 s0, s4 ; encoding: [0x04,0x00,0x80,0xbe] 1217; VI-NEXT: s_mov_b32 s1, s5 ; encoding: [0x05,0x00,0x81,0xbe] 1218; VI-NEXT: s_mov_b32 s4, s6 ; encoding: [0x06,0x00,0x84,0xbe] 1219; VI-NEXT: s_mov_b32 s5, s7 ; encoding: [0x07,0x00,0x85,0xbe] 1220; VI-NEXT: s_mov_b32 s6, s2 ; encoding: [0x02,0x00,0x86,0xbe] 1221; VI-NEXT: s_mov_b32 s7, s3 ; encoding: [0x03,0x00,0x87,0xbe] 1222; VI-NEXT: buffer_load_ushort v0, off, s[4:7], 0 ; encoding: [0x00,0x00,0x48,0xe0,0x00,0x00,0x01,0x80] 1223; VI-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf] 1224; VI-NEXT: v_add_u16_e32 v0, -2, v0 ; encoding: [0xc2,0x00,0x00,0x4c] 1225; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 1226; VI-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 1227; 1228; SI-LABEL: add_inline_imm_neg_2_f16: 1229; SI: ; %bb.0: 1230; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 1231; SI-NEXT: s_mov_b32 s3, 0xf000 1232; SI-NEXT: s_mov_b32 s2, -1 1233; SI-NEXT: s_waitcnt lgkmcnt(0) 1234; SI-NEXT: s_mov_b32 s0, s4 1235; SI-NEXT: s_mov_b32 s1, s5 1236; SI-NEXT: s_mov_b32 s4, s6 1237; SI-NEXT: s_mov_b32 s5, s7 1238; SI-NEXT: s_mov_b32 s6, s2 1239; SI-NEXT: s_mov_b32 s7, s3 1240; SI-NEXT: buffer_load_ushort v0, off, s[4:7], 0 1241; SI-NEXT: s_waitcnt vmcnt(0) 1242; SI-NEXT: v_add_i32_e32 v0, vcc, -2, v0 1243; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 1244; SI-NEXT: s_endpgm 1245 %x = load i16, i16 addrspace(1)* %in 1246 %y = add i16 %x, -2 1247 %ybc = bitcast i16 %y to half 1248 store half %ybc, half addrspace(1)* %out 1249 ret void 1250} 1251 1252define amdgpu_kernel void @add_inline_imm_neg_16_f16(half addrspace(1)* %out, i16 addrspace(1)* %in) { 1253; GFX10-LABEL: add_inline_imm_neg_16_f16: 1254; GFX10: ; %bb.0: 1255; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; encoding: [0x02,0x00,0x08,0xf4,0x00,0x00,0x00,0xfa] 1256; GFX10-NEXT: s_mov_b32 s6, -1 ; encoding: [0xc1,0x03,0x86,0xbe] 1257; GFX10-NEXT: s_mov_b32 s7, 0x31016000 ; encoding: [0xff,0x03,0x87,0xbe,0x00,0x60,0x01,0x31] 1258; GFX10-NEXT: s_mov_b32 s10, s6 ; encoding: [0x06,0x03,0x8a,0xbe] 1259; GFX10-NEXT: s_mov_b32 s11, s7 ; encoding: [0x07,0x03,0x8b,0xbe] 1260; GFX10-NEXT: ; implicit-def: $vcc_hi 1261; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf] 1262; GFX10-NEXT: s_mov_b32 s8, s2 ; encoding: [0x02,0x03,0x88,0xbe] 1263; GFX10-NEXT: s_mov_b32 s9, s3 ; encoding: [0x03,0x03,0x89,0xbe] 1264; GFX10-NEXT: s_mov_b32 s4, s0 ; encoding: [0x00,0x03,0x84,0xbe] 1265; GFX10-NEXT: buffer_load_ushort v0, off, s[8:11], 0 ; encoding: [0x00,0x00,0x28,0xe0,0x00,0x00,0x02,0x80] 1266; GFX10-NEXT: s_mov_b32 s5, s1 ; encoding: [0x01,0x03,0x85,0xbe] 1267; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf] 1268; GFX10-NEXT: v_add_nc_u16_e64 v0, v0, -16 ; encoding: [0x00,0x00,0x03,0xd7,0x00,0xa1,0x01,0x00] 1269; GFX10-NEXT: buffer_store_short v0, off, s[4:7], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x01,0x80] 1270; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 1271; 1272; VI-LABEL: add_inline_imm_neg_16_f16: 1273; VI: ; %bb.0: 1274; VI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0 ; encoding: [0x02,0x01,0x0a,0xc0,0x00,0x00,0x00,0x00] 1275; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11] 1276; VI-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] 1277; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0x00,0x8c,0xbf] 1278; VI-NEXT: s_mov_b32 s0, s4 ; encoding: [0x04,0x00,0x80,0xbe] 1279; VI-NEXT: s_mov_b32 s1, s5 ; encoding: [0x05,0x00,0x81,0xbe] 1280; VI-NEXT: s_mov_b32 s4, s6 ; encoding: [0x06,0x00,0x84,0xbe] 1281; VI-NEXT: s_mov_b32 s5, s7 ; encoding: [0x07,0x00,0x85,0xbe] 1282; VI-NEXT: s_mov_b32 s6, s2 ; encoding: [0x02,0x00,0x86,0xbe] 1283; VI-NEXT: s_mov_b32 s7, s3 ; encoding: [0x03,0x00,0x87,0xbe] 1284; VI-NEXT: buffer_load_ushort v0, off, s[4:7], 0 ; encoding: [0x00,0x00,0x48,0xe0,0x00,0x00,0x01,0x80] 1285; VI-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf] 1286; VI-NEXT: v_add_u16_e32 v0, -16, v0 ; encoding: [0xd0,0x00,0x00,0x4c] 1287; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 1288; VI-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 1289; 1290; SI-LABEL: add_inline_imm_neg_16_f16: 1291; SI: ; %bb.0: 1292; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 1293; SI-NEXT: s_mov_b32 s3, 0xf000 1294; SI-NEXT: s_mov_b32 s2, -1 1295; SI-NEXT: s_waitcnt lgkmcnt(0) 1296; SI-NEXT: s_mov_b32 s0, s4 1297; SI-NEXT: s_mov_b32 s1, s5 1298; SI-NEXT: s_mov_b32 s4, s6 1299; SI-NEXT: s_mov_b32 s5, s7 1300; SI-NEXT: s_mov_b32 s6, s2 1301; SI-NEXT: s_mov_b32 s7, s3 1302; SI-NEXT: buffer_load_ushort v0, off, s[4:7], 0 1303; SI-NEXT: s_waitcnt vmcnt(0) 1304; SI-NEXT: v_add_i32_e32 v0, vcc, -16, v0 1305; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 1306; SI-NEXT: s_endpgm 1307 %x = load i16, i16 addrspace(1)* %in 1308 %y = add i16 %x, -16 1309 %ybc = bitcast i16 %y to half 1310 store half %ybc, half addrspace(1)* %out 1311 ret void 1312} 1313 1314define amdgpu_kernel void @add_inline_imm_63_f16(half addrspace(1)* %out, half %x) { 1315; GFX10-LABEL: add_inline_imm_63_f16: 1316; GFX10: ; %bb.0: 1317; GFX10-NEXT: s_clause 0x1 ; encoding: [0x01,0x00,0xa1,0xbf] 1318; GFX10-NEXT: s_load_dword s2, s[4:5], 0x8 ; encoding: [0x82,0x00,0x00,0xf4,0x08,0x00,0x00,0xfa] 1319; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xfa] 1320; GFX10-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x03,0x83,0xbe,0x00,0x60,0x01,0x31] 1321; GFX10-NEXT: ; implicit-def: $vcc_hi 1322; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf] 1323; GFX10-NEXT: v_add_f16_e64 v0, s2, 63 ; encoding: [0x00,0x00,0x32,0xd5,0x02,0x7e,0x01,0x00] 1324; GFX10-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x03,0x82,0xbe] 1325; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 1326; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 1327; 1328; VI-LABEL: add_inline_imm_63_f16: 1329; VI: ; %bb.0: 1330; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x06,0xc0,0x00,0x00,0x00,0x00] 1331; VI-NEXT: s_load_dword s4, s[4:5], 0x8 ; encoding: [0x02,0x01,0x02,0xc0,0x08,0x00,0x00,0x00] 1332; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11] 1333; VI-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] 1334; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0x00,0x8c,0xbf] 1335; VI-NEXT: v_add_f16_e64 v0, s4, 63 ; encoding: [0x00,0x00,0x1f,0xd1,0x04,0x7e,0x01,0x00] 1336; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 1337; VI-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 1338; 1339; SI-LABEL: add_inline_imm_63_f16: 1340; SI: ; %bb.0: 1341; SI-NEXT: s_load_dword s2, s[0:1], 0xb 1342; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 1343; SI-NEXT: s_mov_b32 s3, 0xf000 1344; SI-NEXT: s_waitcnt lgkmcnt(0) 1345; SI-NEXT: v_cvt_f32_f16_e32 v0, s2 1346; SI-NEXT: s_mov_b32 s2, -1 1347; SI-NEXT: v_add_f32_e32 v0, 0x367c0000, v0 1348; SI-NEXT: v_cvt_f16_f32_e32 v0, v0 1349; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 1350; SI-NEXT: s_endpgm 1351 %y = fadd half %x, 0xH003F 1352 store half %y, half addrspace(1)* %out 1353 ret void 1354} 1355 1356define amdgpu_kernel void @add_inline_imm_64_f16(half addrspace(1)* %out, half %x) { 1357; GFX10-LABEL: add_inline_imm_64_f16: 1358; GFX10: ; %bb.0: 1359; GFX10-NEXT: s_clause 0x1 ; encoding: [0x01,0x00,0xa1,0xbf] 1360; GFX10-NEXT: s_load_dword s2, s[4:5], 0x8 ; encoding: [0x82,0x00,0x00,0xf4,0x08,0x00,0x00,0xfa] 1361; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xfa] 1362; GFX10-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x03,0x83,0xbe,0x00,0x60,0x01,0x31] 1363; GFX10-NEXT: ; implicit-def: $vcc_hi 1364; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf] 1365; GFX10-NEXT: v_add_f16_e64 v0, s2, 64 ; encoding: [0x00,0x00,0x32,0xd5,0x02,0x80,0x01,0x00] 1366; GFX10-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x03,0x82,0xbe] 1367; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 1368; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 1369; 1370; VI-LABEL: add_inline_imm_64_f16: 1371; VI: ; %bb.0: 1372; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x06,0xc0,0x00,0x00,0x00,0x00] 1373; VI-NEXT: s_load_dword s4, s[4:5], 0x8 ; encoding: [0x02,0x01,0x02,0xc0,0x08,0x00,0x00,0x00] 1374; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11] 1375; VI-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] 1376; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0x00,0x8c,0xbf] 1377; VI-NEXT: v_add_f16_e64 v0, s4, 64 ; encoding: [0x00,0x00,0x1f,0xd1,0x04,0x80,0x01,0x00] 1378; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] 1379; VI-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] 1380; 1381; SI-LABEL: add_inline_imm_64_f16: 1382; SI: ; %bb.0: 1383; SI-NEXT: s_load_dword s2, s[0:1], 0xb 1384; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 1385; SI-NEXT: s_mov_b32 s3, 0xf000 1386; SI-NEXT: s_waitcnt lgkmcnt(0) 1387; SI-NEXT: v_cvt_f32_f16_e32 v0, s2 1388; SI-NEXT: s_mov_b32 s2, -1 1389; SI-NEXT: v_add_f32_e32 v0, 0x36800000, v0 1390; SI-NEXT: v_cvt_f16_f32_e32 v0, v0 1391; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 1392; SI-NEXT: s_endpgm 1393 %y = fadd half %x, 0xH0040 1394 store half %y, half addrspace(1)* %out 1395 ret void 1396} 1397 1398; This needs to be emitted as a literal constant since the 16-bit 1399; float values do not work for 16-bit integer operations. 1400define void @mul_inline_imm_0.5_i16(i16 addrspace(1)* %out, i16 %x) { 1401; GFX10-LABEL: mul_inline_imm_0.5_i16: 1402; GFX10: ; %bb.0: 1403; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf] 1404; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb] 1405; GFX10-NEXT: v_mul_lo_u16_e64 v2, 0x3800, v2 ; encoding: [0x02,0x00,0x05,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00] 1406; GFX10-NEXT: ; implicit-def: $vcc_hi 1407; GFX10-NEXT: global_store_short v[0:1], v2, off ; encoding: [0x00,0x80,0x68,0xdc,0x00,0x02,0x7d,0x00] 1408; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb] 1409; GFX10-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x20,0x80,0xbe] 1410; 1411; VI-LABEL: mul_inline_imm_0.5_i16: 1412; VI: ; %bb.0: 1413; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf] 1414; VI-NEXT: v_mul_lo_u16_e32 v2, 0x3800, v2 ; encoding: [0xff,0x04,0x04,0x52,0x00,0x38,0x00,0x00] 1415; VI-NEXT: flat_store_short v[0:1], v2 ; encoding: [0x00,0x00,0x68,0xdc,0x00,0x02,0x00,0x00] 1416; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; encoding: [0x70,0x00,0x8c,0xbf] 1417; VI-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x1d,0x80,0xbe] 1418; 1419; SI-LABEL: mul_inline_imm_0.5_i16: 1420; SI: ; %bb.0: 1421; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1422; SI-NEXT: s_mov_b32 s6, 0 1423; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 1424; SI-NEXT: s_mov_b32 s7, 0xf000 1425; SI-NEXT: s_mov_b32 s4, s6 1426; SI-NEXT: s_mov_b32 s5, s6 1427; SI-NEXT: v_mul_u32_u24_e32 v2, 0x3800, v2 1428; SI-NEXT: buffer_store_short v2, v[0:1], s[4:7], 0 addr64 1429; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) 1430; SI-NEXT: s_setpc_b64 s[30:31] 1431 %y = mul i16 %x, bitcast (half 0.5 to i16) 1432 store i16 %y, i16 addrspace(1)* %out 1433 ret void 1434} 1435 1436define void @mul_inline_imm_neg_0.5_i16(i16 addrspace(1)* %out, i16 %x) { 1437; GFX10-LABEL: mul_inline_imm_neg_0.5_i16: 1438; GFX10: ; %bb.0: 1439; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf] 1440; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb] 1441; GFX10-NEXT: v_mul_lo_u16_e64 v2, 0xffffb800, v2 ; encoding: [0x02,0x00,0x05,0xd7,0xff,0x04,0x02,0x00,0x00,0xb8,0xff,0xff] 1442; GFX10-NEXT: ; implicit-def: $vcc_hi 1443; GFX10-NEXT: global_store_short v[0:1], v2, off ; encoding: [0x00,0x80,0x68,0xdc,0x00,0x02,0x7d,0x00] 1444; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb] 1445; GFX10-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x20,0x80,0xbe] 1446; 1447; VI-LABEL: mul_inline_imm_neg_0.5_i16: 1448; VI: ; %bb.0: 1449; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf] 1450; VI-NEXT: v_mul_lo_u16_e32 v2, 0xffffb800, v2 ; encoding: [0xff,0x04,0x04,0x52,0x00,0xb8,0xff,0xff] 1451; VI-NEXT: flat_store_short v[0:1], v2 ; encoding: [0x00,0x00,0x68,0xdc,0x00,0x02,0x00,0x00] 1452; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; encoding: [0x70,0x00,0x8c,0xbf] 1453; VI-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x1d,0x80,0xbe] 1454; 1455; SI-LABEL: mul_inline_imm_neg_0.5_i16: 1456; SI: ; %bb.0: 1457; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1458; SI-NEXT: s_mov_b32 s6, 0 1459; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 1460; SI-NEXT: s_mov_b32 s7, 0xf000 1461; SI-NEXT: s_mov_b32 s4, s6 1462; SI-NEXT: s_mov_b32 s5, s6 1463; SI-NEXT: v_mul_u32_u24_e32 v2, 0xb800, v2 1464; SI-NEXT: buffer_store_short v2, v[0:1], s[4:7], 0 addr64 1465; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) 1466; SI-NEXT: s_setpc_b64 s[30:31] 1467 %y = mul i16 %x, bitcast (half -0.5 to i16) 1468 store i16 %y, i16 addrspace(1)* %out 1469 ret void 1470} 1471 1472define void @mul_inline_imm_1.0_i16(i16 addrspace(1)* %out, i16 %x) { 1473; GFX10-LABEL: mul_inline_imm_1.0_i16: 1474; GFX10: ; %bb.0: 1475; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf] 1476; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb] 1477; GFX10-NEXT: v_mul_lo_u16_e64 v2, 0x3c00, v2 ; encoding: [0x02,0x00,0x05,0xd7,0xff,0x04,0x02,0x00,0x00,0x3c,0x00,0x00] 1478; GFX10-NEXT: ; implicit-def: $vcc_hi 1479; GFX10-NEXT: global_store_short v[0:1], v2, off ; encoding: [0x00,0x80,0x68,0xdc,0x00,0x02,0x7d,0x00] 1480; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb] 1481; GFX10-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x20,0x80,0xbe] 1482; 1483; VI-LABEL: mul_inline_imm_1.0_i16: 1484; VI: ; %bb.0: 1485; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf] 1486; VI-NEXT: v_mul_lo_u16_e32 v2, 0x3c00, v2 ; encoding: [0xff,0x04,0x04,0x52,0x00,0x3c,0x00,0x00] 1487; VI-NEXT: flat_store_short v[0:1], v2 ; encoding: [0x00,0x00,0x68,0xdc,0x00,0x02,0x00,0x00] 1488; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; encoding: [0x70,0x00,0x8c,0xbf] 1489; VI-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x1d,0x80,0xbe] 1490; 1491; SI-LABEL: mul_inline_imm_1.0_i16: 1492; SI: ; %bb.0: 1493; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1494; SI-NEXT: s_mov_b32 s6, 0 1495; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 1496; SI-NEXT: s_mov_b32 s7, 0xf000 1497; SI-NEXT: s_mov_b32 s4, s6 1498; SI-NEXT: s_mov_b32 s5, s6 1499; SI-NEXT: v_mul_u32_u24_e32 v2, 0x3c00, v2 1500; SI-NEXT: buffer_store_short v2, v[0:1], s[4:7], 0 addr64 1501; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) 1502; SI-NEXT: s_setpc_b64 s[30:31] 1503 %y = mul i16 %x, bitcast (half 1.0 to i16) 1504 store i16 %y, i16 addrspace(1)* %out 1505 ret void 1506} 1507 1508define void @mul_inline_imm_neg_1.0_i16(i16 addrspace(1)* %out, i16 %x) { 1509; GFX10-LABEL: mul_inline_imm_neg_1.0_i16: 1510; GFX10: ; %bb.0: 1511; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf] 1512; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb] 1513; GFX10-NEXT: v_mul_lo_u16_e64 v2, 0xffffbc00, v2 ; encoding: [0x02,0x00,0x05,0xd7,0xff,0x04,0x02,0x00,0x00,0xbc,0xff,0xff] 1514; GFX10-NEXT: ; implicit-def: $vcc_hi 1515; GFX10-NEXT: global_store_short v[0:1], v2, off ; encoding: [0x00,0x80,0x68,0xdc,0x00,0x02,0x7d,0x00] 1516; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb] 1517; GFX10-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x20,0x80,0xbe] 1518; 1519; VI-LABEL: mul_inline_imm_neg_1.0_i16: 1520; VI: ; %bb.0: 1521; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf] 1522; VI-NEXT: v_mul_lo_u16_e32 v2, 0xffffbc00, v2 ; encoding: [0xff,0x04,0x04,0x52,0x00,0xbc,0xff,0xff] 1523; VI-NEXT: flat_store_short v[0:1], v2 ; encoding: [0x00,0x00,0x68,0xdc,0x00,0x02,0x00,0x00] 1524; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; encoding: [0x70,0x00,0x8c,0xbf] 1525; VI-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x1d,0x80,0xbe] 1526; 1527; SI-LABEL: mul_inline_imm_neg_1.0_i16: 1528; SI: ; %bb.0: 1529; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1530; SI-NEXT: s_mov_b32 s6, 0 1531; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 1532; SI-NEXT: s_mov_b32 s7, 0xf000 1533; SI-NEXT: s_mov_b32 s4, s6 1534; SI-NEXT: s_mov_b32 s5, s6 1535; SI-NEXT: v_mul_u32_u24_e32 v2, 0xbc00, v2 1536; SI-NEXT: buffer_store_short v2, v[0:1], s[4:7], 0 addr64 1537; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) 1538; SI-NEXT: s_setpc_b64 s[30:31] 1539 %y = mul i16 %x, bitcast (half -1.0 to i16) 1540 store i16 %y, i16 addrspace(1)* %out 1541 ret void 1542} 1543 1544define void @shl_inline_imm_2.0_i16(i16 addrspace(1)* %out, i16 %x) { 1545; GFX10-LABEL: shl_inline_imm_2.0_i16: 1546; GFX10: ; %bb.0: 1547; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf] 1548; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb] 1549; GFX10-NEXT: v_lshlrev_b16_e64 v2, v2, 0x4000 ; encoding: [0x02,0x00,0x14,0xd7,0x02,0xff,0x01,0x00,0x00,0x40,0x00,0x00] 1550; GFX10-NEXT: ; implicit-def: $vcc_hi 1551; GFX10-NEXT: global_store_short v[0:1], v2, off ; encoding: [0x00,0x80,0x68,0xdc,0x00,0x02,0x7d,0x00] 1552; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb] 1553; GFX10-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x20,0x80,0xbe] 1554; 1555; VI-LABEL: shl_inline_imm_2.0_i16: 1556; VI: ; %bb.0: 1557; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf] 1558; VI-NEXT: s_movk_i32 s4, 0x4000 ; encoding: [0x00,0x40,0x04,0xb0] 1559; VI-NEXT: v_lshlrev_b16_e64 v2, v2, s4 ; encoding: [0x02,0x00,0x2a,0xd1,0x02,0x09,0x00,0x00] 1560; VI-NEXT: flat_store_short v[0:1], v2 ; encoding: [0x00,0x00,0x68,0xdc,0x00,0x02,0x00,0x00] 1561; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; encoding: [0x70,0x00,0x8c,0xbf] 1562; VI-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x1d,0x80,0xbe] 1563; 1564; SI-LABEL: shl_inline_imm_2.0_i16: 1565; SI: ; %bb.0: 1566; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1567; SI-NEXT: s_mov_b32 s6, 0 1568; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 1569; SI-NEXT: s_mov_b32 s7, 0xf000 1570; SI-NEXT: s_mov_b32 s4, s6 1571; SI-NEXT: s_mov_b32 s5, s6 1572; SI-NEXT: v_lshl_b32_e32 v2, 0x4000, v2 1573; SI-NEXT: buffer_store_short v2, v[0:1], s[4:7], 0 addr64 1574; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) 1575; SI-NEXT: s_setpc_b64 s[30:31] 1576 %y = shl i16 bitcast (half 2.0 to i16), %x 1577 store i16 %y, i16 addrspace(1)* %out 1578 ret void 1579} 1580 1581define void @shl_inline_imm_neg_2.0_i16(i16 addrspace(1)* %out, i16 %x) { 1582; GFX10-LABEL: shl_inline_imm_neg_2.0_i16: 1583; GFX10: ; %bb.0: 1584; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf] 1585; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb] 1586; GFX10-NEXT: v_lshlrev_b16_e64 v2, v2, 0xffffc000 ; encoding: [0x02,0x00,0x14,0xd7,0x02,0xff,0x01,0x00,0x00,0xc0,0xff,0xff] 1587; GFX10-NEXT: ; implicit-def: $vcc_hi 1588; GFX10-NEXT: global_store_short v[0:1], v2, off ; encoding: [0x00,0x80,0x68,0xdc,0x00,0x02,0x7d,0x00] 1589; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb] 1590; GFX10-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x20,0x80,0xbe] 1591; 1592; VI-LABEL: shl_inline_imm_neg_2.0_i16: 1593; VI: ; %bb.0: 1594; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf] 1595; VI-NEXT: s_movk_i32 s4, 0xc000 ; encoding: [0x00,0xc0,0x04,0xb0] 1596; VI-NEXT: v_lshlrev_b16_e64 v2, v2, s4 ; encoding: [0x02,0x00,0x2a,0xd1,0x02,0x09,0x00,0x00] 1597; VI-NEXT: flat_store_short v[0:1], v2 ; encoding: [0x00,0x00,0x68,0xdc,0x00,0x02,0x00,0x00] 1598; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; encoding: [0x70,0x00,0x8c,0xbf] 1599; VI-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x1d,0x80,0xbe] 1600; 1601; SI-LABEL: shl_inline_imm_neg_2.0_i16: 1602; SI: ; %bb.0: 1603; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1604; SI-NEXT: s_mov_b32 s6, 0 1605; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 1606; SI-NEXT: s_mov_b32 s7, 0xf000 1607; SI-NEXT: s_mov_b32 s4, s6 1608; SI-NEXT: s_mov_b32 s5, s6 1609; SI-NEXT: v_lshl_b32_e32 v2, 0xffffc000, v2 1610; SI-NEXT: buffer_store_short v2, v[0:1], s[4:7], 0 addr64 1611; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) 1612; SI-NEXT: s_setpc_b64 s[30:31] 1613 %y = shl i16 bitcast (half -2.0 to i16), %x 1614 store i16 %y, i16 addrspace(1)* %out 1615 ret void 1616} 1617 1618define void @mul_inline_imm_4.0_i16(i16 addrspace(1)* %out, i16 %x) { 1619; GFX10-LABEL: mul_inline_imm_4.0_i16: 1620; GFX10: ; %bb.0: 1621; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf] 1622; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb] 1623; GFX10-NEXT: v_mul_lo_u16_e64 v2, 0x4400, v2 ; encoding: [0x02,0x00,0x05,0xd7,0xff,0x04,0x02,0x00,0x00,0x44,0x00,0x00] 1624; GFX10-NEXT: ; implicit-def: $vcc_hi 1625; GFX10-NEXT: global_store_short v[0:1], v2, off ; encoding: [0x00,0x80,0x68,0xdc,0x00,0x02,0x7d,0x00] 1626; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb] 1627; GFX10-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x20,0x80,0xbe] 1628; 1629; VI-LABEL: mul_inline_imm_4.0_i16: 1630; VI: ; %bb.0: 1631; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf] 1632; VI-NEXT: v_mul_lo_u16_e32 v2, 0x4400, v2 ; encoding: [0xff,0x04,0x04,0x52,0x00,0x44,0x00,0x00] 1633; VI-NEXT: flat_store_short v[0:1], v2 ; encoding: [0x00,0x00,0x68,0xdc,0x00,0x02,0x00,0x00] 1634; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; encoding: [0x70,0x00,0x8c,0xbf] 1635; VI-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x1d,0x80,0xbe] 1636; 1637; SI-LABEL: mul_inline_imm_4.0_i16: 1638; SI: ; %bb.0: 1639; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1640; SI-NEXT: s_mov_b32 s6, 0 1641; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 1642; SI-NEXT: s_mov_b32 s7, 0xf000 1643; SI-NEXT: s_mov_b32 s4, s6 1644; SI-NEXT: s_mov_b32 s5, s6 1645; SI-NEXT: v_mul_u32_u24_e32 v2, 0x4400, v2 1646; SI-NEXT: buffer_store_short v2, v[0:1], s[4:7], 0 addr64 1647; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) 1648; SI-NEXT: s_setpc_b64 s[30:31] 1649 %y = mul i16 %x, bitcast (half 4.0 to i16) 1650 store i16 %y, i16 addrspace(1)* %out 1651 ret void 1652} 1653 1654define void @mul_inline_imm_neg_4.0_i16(i16 addrspace(1)* %out, i16 %x) { 1655; GFX10-LABEL: mul_inline_imm_neg_4.0_i16: 1656; GFX10: ; %bb.0: 1657; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf] 1658; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb] 1659; GFX10-NEXT: v_mul_lo_u16_e64 v2, 0xffffc400, v2 ; encoding: [0x02,0x00,0x05,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0xff,0xff] 1660; GFX10-NEXT: ; implicit-def: $vcc_hi 1661; GFX10-NEXT: global_store_short v[0:1], v2, off ; encoding: [0x00,0x80,0x68,0xdc,0x00,0x02,0x7d,0x00] 1662; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb] 1663; GFX10-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x20,0x80,0xbe] 1664; 1665; VI-LABEL: mul_inline_imm_neg_4.0_i16: 1666; VI: ; %bb.0: 1667; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf] 1668; VI-NEXT: v_mul_lo_u16_e32 v2, 0xffffc400, v2 ; encoding: [0xff,0x04,0x04,0x52,0x00,0xc4,0xff,0xff] 1669; VI-NEXT: flat_store_short v[0:1], v2 ; encoding: [0x00,0x00,0x68,0xdc,0x00,0x02,0x00,0x00] 1670; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; encoding: [0x70,0x00,0x8c,0xbf] 1671; VI-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x1d,0x80,0xbe] 1672; 1673; SI-LABEL: mul_inline_imm_neg_4.0_i16: 1674; SI: ; %bb.0: 1675; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1676; SI-NEXT: s_mov_b32 s6, 0 1677; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 1678; SI-NEXT: s_mov_b32 s7, 0xf000 1679; SI-NEXT: s_mov_b32 s4, s6 1680; SI-NEXT: s_mov_b32 s5, s6 1681; SI-NEXT: v_mul_u32_u24_e32 v2, 0xc400, v2 1682; SI-NEXT: buffer_store_short v2, v[0:1], s[4:7], 0 addr64 1683; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) 1684; SI-NEXT: s_setpc_b64 s[30:31] 1685 %y = mul i16 %x, bitcast (half -4.0 to i16) 1686 store i16 %y, i16 addrspace(1)* %out 1687 ret void 1688} 1689 1690define void @mul_inline_imm_inv2pi_i16(i16 addrspace(1)* %out, i16 %x) { 1691; GFX10-LABEL: mul_inline_imm_inv2pi_i16: 1692; GFX10: ; %bb.0: 1693; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf] 1694; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb] 1695; GFX10-NEXT: v_mul_lo_u16_e64 v2, 0x3118, v2 ; encoding: [0x02,0x00,0x05,0xd7,0xff,0x04,0x02,0x00,0x18,0x31,0x00,0x00] 1696; GFX10-NEXT: ; implicit-def: $vcc_hi 1697; GFX10-NEXT: global_store_short v[0:1], v2, off ; encoding: [0x00,0x80,0x68,0xdc,0x00,0x02,0x7d,0x00] 1698; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb] 1699; GFX10-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x20,0x80,0xbe] 1700; 1701; VI-LABEL: mul_inline_imm_inv2pi_i16: 1702; VI: ; %bb.0: 1703; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf] 1704; VI-NEXT: v_mul_lo_u16_e32 v2, 0x3118, v2 ; encoding: [0xff,0x04,0x04,0x52,0x18,0x31,0x00,0x00] 1705; VI-NEXT: flat_store_short v[0:1], v2 ; encoding: [0x00,0x00,0x68,0xdc,0x00,0x02,0x00,0x00] 1706; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; encoding: [0x70,0x00,0x8c,0xbf] 1707; VI-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x1d,0x80,0xbe] 1708; 1709; SI-LABEL: mul_inline_imm_inv2pi_i16: 1710; SI: ; %bb.0: 1711; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1712; SI-NEXT: s_mov_b32 s6, 0 1713; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 1714; SI-NEXT: s_mov_b32 s7, 0xf000 1715; SI-NEXT: s_mov_b32 s4, s6 1716; SI-NEXT: s_mov_b32 s5, s6 1717; SI-NEXT: v_mul_u32_u24_e32 v2, 0x3118, v2 1718; SI-NEXT: buffer_store_short v2, v[0:1], s[4:7], 0 addr64 1719; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) 1720; SI-NEXT: s_setpc_b64 s[30:31] 1721 %y = mul i16 %x, bitcast (half 0xH3118 to i16) 1722 store i16 %y, i16 addrspace(1)* %out 1723 ret void 1724} 1725